CN118216004A

CN118216004A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN118216004A
Application number: CN202280070581.9A
Authority: CN
Inventors: 陈柏玮
Original assignee: Innoscience Zhuhai Technology Co Ltd
Current assignee: Innoscience Zhuhai Technology Co Ltd
Priority date: 2022-08-26
Filing date: 2022-08-26
Publication date: 2024-06-18
Also published as: WO2024040600A1

Abstract

A semiconductor device includes first and second nitride-based semiconductor layers, a drain, a source, a gate, a plurality of field plates, a conductive layer and at least one contact through hole. The field plate is disposed on the second nitride-based semiconductor layer and between the gate and the drain. The gate is not covered by the field plate. The conductive layer is disposed on the field plate. The at least one contact through hole connects one of the field plates to the conductive layer, so that the field plate and the contact through hole have substantially the same voltage level.

Description

Semiconductor device and method for manufacturing the same

Technical Field

In general, the present invention relates to nitride-based semiconductor devices. More particularly, the present disclosure relates to nitride-based semiconductor devices having contact vias with stripe profiles.

Background

In recent years, research into High Electron Mobility Transistors (HEMTs) has been increasingly popular, particularly for high power switches and high frequency applications. Group III nitride based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2 DEG) region, meeting the requirements of high power/frequency devices. Examples of devices having a heterostructure include Heterojunction Bipolar Transistors (HBTs), heterojunction Field Effect Transistors (HFETs) and modulation doped FETs (MODFETs) in addition to HEMTs.

Disclosure of Invention

In one aspect, the present invention provides a semiconductor device. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a drain electrode, a source electrode, a gate electrode, a plurality of field plates, a conductive layer, and at least one contact via. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a band gap larger than that of the first nitride-based semiconductor layer. The drain electrode and the source electrode are disposed on the second nitride-based semiconductor layer. The gate electrode is disposed on the second nitride-based semiconductor layer and between the drain electrode and the source electrode. The field plate is disposed on the second nitride-based semiconductor layer and between the gate electrode and the drain electrode. The gate is not covered by the field plate. The conductive layer is disposed on the field plate. The at least one contact via connects one of the field plates to the conductive layer such that the field plates and the contact via have substantially the same voltage level.

In another aspect, the present invention provides a method for manufacturing a semiconductor device. The method comprises the following steps. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A source electrode and a drain electrode are formed on the second nitride-based semiconductor layer. The gate electrode is formed on the second nitride-based semiconductor layer and between the source electrode and the drain electrode. A plurality of field plates are formed on the second nitride-based semiconductor layer. The field plate is formed between the gate and the drain. A dielectric layer is formed to cover the gate, source and drain. The field plate is embedded in the dielectric layer. At least a portion of the dielectric layer is removed to expose a top surface of the at least one field plate. At least one contact via is formed to contact the exposed first field plate. The conductive layer is formed to contact the contact via such that the conductive layer is electrically coupled to the first field plate through the contact via.

In yet another aspect, the present invention provides a semiconductor device. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a drain electrode, a source electrode, a gate electrode, a plurality of field plates, a conductive layer, at least one connection member, and a dielectric layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a larger band gap than the first nitride-based semiconductor layer. The drain electrode and the source electrode are disposed on the second nitride-based semiconductor layer. The gate electrode is disposed on the second nitride-based semiconductor layer and between the drain electrode and the source electrode. The field plate is disposed on the second nitride-based semiconductor layer and between the gate electrode and the drain electrode. The conductive layer extends horizontally over the gate and the field plate. The at least one connection member extends in a vertical direction to contact one of the field plate and the conductive layer. The dielectric layer covers the gate, source and drain. A portion of the dielectric layer is located between each field plate and the gate such that each field plate is spaced apart from the gate by the dielectric layer.

With the above configuration, in the present disclosure, a plurality of field plates are located between the gate electrode and the drain electrode. Each field plate is horizontally spaced apart from the gate electrode so that the gate electrode is not covered by the field plate. In this way, parasitic/stray capacitance between the gate and the field plate can be reduced. The field plate is configured to adjust an electric field distribution in the device. Therefore, the nitride-based semiconductor device of the present invention has good reliability and is suitable for high-frequency devices. Furthermore, the field plate may be electrically connected to a voltage source through contact vias/components. In some embodiments, the contact vias/features extend in one direction to have a bar profile; accordingly, the contact area between the contact via/member and the field plate can be enlarged, thereby improving the voltage distribution uniformity of the field plate. Thus, the nitride-based semiconductor device of the present disclosure can achieve a desired electric field distribution.

Drawings

Various aspects of the invention can be readily appreciated from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity. Embodiments of the invention are described in more detail below with reference to the attached drawing figures, wherein:

fig. 1A is a top view of a semiconductor device according to some embodiments of the present disclosure;

fig. 1B is a vertical cross-sectional view of the semiconductor device in fig. 1A;

fig. 2A, 2B, and 2C illustrate different stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure;

Fig. 3A is a top view of a semiconductor device according to some embodiments of the present disclosure;

Fig. 3B is a vertical cross-sectional view of the semiconductor device of fig. 3A;

Fig. 4A is a top view of a semiconductor device according to some embodiments of the present disclosure;

fig. 4B is a vertical cross-sectional view of the semiconductor device in fig. 4A;

Fig. 5 is a top view of a semiconductor device according to some embodiments of the present disclosure;

fig. 6A is a top view of a semiconductor device according to some embodiments of the present disclosure;

fig. 6B is a vertical cross-sectional view of the semiconductor device in fig. 6A;

Fig. 7 is a top view of a semiconductor device according to some embodiments of the present disclosure;

fig. 8 is a top view of a semiconductor device according to some embodiments of the present disclosure;

fig. 9 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

fig. 10 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

fig. 11 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

fig. 12 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

fig. 13 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

fig. 14 is a top view of a semiconductor device according to some embodiments of the present disclosure;

fig. 15 is a top view of a semiconductor device according to some embodiments of the present disclosure;

fig. 16A is a top view of a semiconductor device according to some embodiments of the present disclosure;

Fig. 16B is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and

Fig. 17 is a top view of a semiconductor device 1P according to some embodiments of the present disclosure.

Detailed Description

The same reference indicators will be used throughout the drawings and the detailed description to refer to the same or like parts. Embodiments of the present invention will be readily understood from the following detailed description in conjunction with the accompanying drawings.

Spatial descriptions such as "upper," "lower," "left," "right," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," etc., are intended to be relative to a certain component or group of components, or a plane of a component or group of components, for the orientation of the components shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that specific implementations of the structures described herein may be spatially arranged in any orientation or manner without departing from the spirit of the present invention.

Further, it should be noted that, subject to device manufacturing conditions, in an actual device, the actual shape of the various structures depicted as being approximately rectangular may be curved, or have rounded corners, or have a slightly non-uniform thickness, etc. Straight lines and right angles are only used to facilitate the presentation of layers and features.

In the following description, a semiconductor device/die/package and a method for manufacturing the same are set forth as preferred examples. It will be apparent that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the invention. Specific details may be omitted to avoid obscuring. However, the present invention was written in order to enable any person skilled in the art to practice the teachings thereof without undue experimentation.

Fig. 1A is a top view of a semiconductor device 1A according to some embodiments of the present disclosure. Fig. 1B is a vertical sectional view of the semiconductor device 1A in fig. 1A. Referring to fig. 1A and 1B, a semiconductor device 1A may be located in a space defined by directions D1, D2, and D3. The direction D1 (e.g., width direction) is perpendicular to the direction D2, the direction D2 (e.g., perpendicular/thickness direction) is perpendicular to the direction D3, and the direction D3 (e.g., length direction) is perpendicular to the direction D1. The semiconductor device 1A may include a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14, 16, a gate structure GS, electrodes 22, 24, field plates 32, 34, 36, contact vias/features 40A (i.e., conductive vias), a conductive layer 38, and a dielectric layer 42.

The substrate 10 may be a semiconductor substrate. Exemplary materials for substrate 10 may include, but are not limited to, si, siGe, siC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) or other suitable substrate materials. In some embodiments, the substrate 10 may include, but is not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound). In other embodiments, the substrate 10 may include, but is not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof.

The buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 14. The buffer layer 12 may be configured to reduce lattice and thermal mismatch between the substrate 10 and the nitride-based semiconductor layer 14, thereby overcoming defects caused by mismatch/difference. The buffer layer may include a III-V compound. The III-V compounds may include, but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, exemplary materials for buffer layer 12 may further include, but are not limited to GaN, alN, alGaN, inAlGaN or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown). A nucleation layer may be formed between the substrate 10 and the buffer layer 12. The nucleation layer may be configured to provide a transition to accommodate the mismatch/difference between the III-nitride layers of the substrate 10 and the buffer layer 12. Exemplary materials for the nucleation layer may include, but are not limited to, alN or any alloy thereof.

A nitride-based semiconductor layer 14 may be disposed on the buffer layer 12. The nitride-based semiconductor layer 16 may be disposed on the nitride-based semiconductor layer 14. Exemplary materials for nitride-based semiconductor layer 14 may include, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in _xAl_yGa_(1-x-y) N (where x+y.ltoreq.1), or Al _xGa_(1-x) N (where x.ltoreq.1). Exemplary materials for nitride-based semiconductor layer 16 may include, but are not limited to, nitrides or III-V compounds, such as GaN, alN, in _xAl_yGa_(1-x-y) N (where x+y.ltoreq.1), or Al _yGa_(1-y) N (where y.ltoreq.1).

The exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the band gap (i.e., the forbidden band width) of the nitride-based semiconductor layer 16 is greater than the band gap of the nitride-based semiconductor layer 14, thereby making their electron affinities different from each other and forming a heterojunction therebetween. For example, when nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of about 3.4eV, nitride-based semiconductor layer 16 may be selected to be a GaN layer having a bandgap of about 4.0 eV. In this way, the nitride-based semiconductor layers 14 and 16 may function as a channel layer and a barrier layer, respectively. A triangular trap potential is generated at the bonding interface between the channel and the barrier layer such that electrons accumulate in the triangular trap, thereby creating a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A may be used to include at least one GaN-based High Electron Mobility Transistor (HEMT).

Electrodes 22 and 24 may be disposed on nitride-based semiconductor layer 16. The electrodes 22 and 24 may be in contact with the nitride-based semiconductor layer 16. In some embodiments, electrode 22 may serve as a source. In some embodiments, electrode 22 may function as a drain. In some embodiments, electrode 24 may serve as a source. In some embodiments, electrode 24 may function as a drain. The roles of the electrodes 22 and 24 depend on the device design.

In some embodiments, electrodes 22 and 24 may include, but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. Exemplary materials for electrodes 22 and 24 may include, but are not limited to, ti, alSi, tiN, or combinations thereof. Each electrode 22 and 24 may be a single layer or multiple layers of the same or different composition. The electrodes 22 and 24 form ohmic contacts with the nitride-based semiconductor layer 16. In addition, ohmic contact may be achieved by applying Ti, al, or other suitable materials to the electrodes 22 and 24. In some embodiments, each electrode 22 and 24 is formed from at least one conformal layer and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials for the conformal layer may include, but are not limited to, ti, ta, tiN, al, au, alSi, ni, pt, or combinations thereof. Exemplary materials for the conductive filler may include, but are not limited to AlSi, alCu, or combinations thereof.

The gate structure GS is disposed on the nitride-based semiconductor layer 16. The gate structure GS includes a doped nitride-based semiconductor layer 18 and a gate 20. A doped nitride-based semiconductor layer 18 is disposed on the nitride-based semiconductor layer 16. The doped nitride-based semiconductor layer 18 is in contact with the nitride-based semiconductor layer 16. A doped nitride-based semiconductor layer 18 is disposed between the nitride-based semiconductor layer 16 and the gate electrode 20. The gate electrode 20 is disposed on the doped nitride-based semiconductor layer 18 and the nitride-based semiconductor layer 16. The gate electrode 20 is in contact with the doped nitride-based semiconductor layer 18. The gate 20 is located between the electrodes 22, 24.

The width of the doped nitride-based semiconductor layer 18 is greater than the width of the gate 20. In some embodiments, the width of doped nitride-based semiconductor layer 18 is substantially the same as the width of gate 20. The profile of the doped nitride-based semiconductor layer 18 and the gate 20 is identical, for example, a rectangular profile. In other embodiments, the profiles of the doped nitride-based semiconductor layer 18 and the gate 20 may be different from each other, for example, the profile of the doped nitride-based semiconductor layer 18 may be a trapezoidal profile, while the profile of the gate 20 may be a rectangular profile.

In the exemplary illustration of fig. 1A, semiconductor device 1A is an enhancement mode device that is in a normally off state when gate 20 is at approximately zero bias. Specifically, doped nitride-based semiconductor layer 18 may create at least one p-n junction with nitride-based semiconductor layer 16 to deplete the 2DEG region such that at least one zone of the 2DEG region under gate 20 has a different characteristic (e.g., a different electron concentration) than the rest of the 2DEG region, and is thus blocked.

Due to this mechanism, the semiconductor device 1A has normally-off characteristics. In other words, when no voltage is applied to the gate 20 or the voltage applied to the gate 20 is less than the threshold voltage (i.e., the minimum voltage required to form an inversion layer under the gate 20), the band of the 2DEG region under the gate 20 remains blocked, and thus no current flows.

In some embodiments, the doped nitride-based semiconductor layer 18 may be omitted such that the semiconductor device 1A is a depletion mode device, meaning that the semiconductor device 1A is in a normally-on state at zero gate-source voltage.

The doped nitride-based semiconductor layer 18 may be a p-type doped III-V semiconductor layer. Exemplary materials for doped nitride-based semiconductor layer 18 may include, but are not limited to, p-doped group III-V nitride-based semiconductor materials such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped material is achieved by using p-type impurities (e.g., be, zn, cd, and Mg). In some embodiments, nitride-based semiconductor layer 14 comprises undoped GaN, nitride-based semiconductor layer 16 comprises AlGaN, and doped nitride-based semiconductor layer 18 is a p-type doped GaN layer that can bend the underlying band structure upward and deplete the corresponding band of the 2DEG region, thereby placing semiconductor device 1A in an off state.

Exemplary materials for gate 20 may include metals or metal compounds. The gate electrode 20 may be formed as a single layer or multiple layers of the same or different composition. Exemplary materials for the metal or metal compound may include, but are not limited to, W, au, pd, ti, ta, co, ni, pt, mo, tiN, taN, metal alloys or compounds thereof, or other metal compounds.

To avoid breakdown phenomena caused by strong peak electric fields in the device, field plates are used to adjust the electric field distribution therein. The configuration of the field plates may cause unwanted parasitic/stray capacitances, which limit the maximum operating frequency of the device, thereby reducing its electrical performance and reliability.

Furthermore, in order to achieve a desired electric field distribution in the device, the voltage level distribution of the field plate is an important factor in determining the desired electric field distribution in the device. Under ideal conditions, the voltage source may be electrically connected to the field plate such that the field plate has substantially the same voltage level as the voltage source. However, due to the relationship between the geometry and area of the field plates, the voltage distribution of the field plates is non-uniform, and thus the electric field distribution in the device deviates from the desired electric field distribution, resulting in poor device performance. Therefore, there is a need for improved device performance.

To at least solve the above-described problems, the present disclosure provides a novel structure.

The field plates 32, 34 and 36 are disposed on the nitride-based semiconductor layer 16. Field plates 32, 34 and 36 are located between gate 20 and electrode 24. The field plates 32, 34, 36 are configured to adjust the electric field distribution in the region between the gate 20 and the electrode 24.

The field plates 32, 34 and 36 are each located at a different height. The field plate 32 is the field plate closest to the gate 20 and is the lowest positioned field plate of the field plates 32, 34 and 36. The field plate 34 is the second closest field plate to the gate 20 and is the second lowest field plate in position among the field plates 32, 34 and 36. The field plate 36 is the field plate furthest from the gate 20 and is the field plate located highest in the field plates 32, 34 and 36. The field plate 34 extends to the top of the field plate 32 to vertically overlap a portion of the field plate 32 such that the edge of the field plate 32 is covered by the field plate 34. The field plate 36 extends to the top of the field plate 34 to vertically overlap a portion of the field plate 34 such that the edge of the field plate 34 is covered by the field plate 36. By the above-described configuration of the field plates 32, 34, and 36, the electric field distribution in the semiconductor device 1A can be well adjusted.

Each of the field plates 32, 34 and 36 is horizontally spaced apart from the gate 20 such that the gate 20 is not covered by any of the field plates 32, 34 and 36, thereby mitigating parasitic/stray capacitance between the gate 20 and the field plates 32/34/36. Therefore, the semiconductor device 1A can be applied to a high-frequency device and has good device performance.

Exemplary materials for field plates 32, 34, and 36 may include, but are not limited to, conductive materials such as Ti, ta, tiN, taN, or combinations thereof. In some embodiments, other conductive materials, such as Al, cu doped Si, and alloys including these materials, may also be used.

A conductive layer 38 is disposed on the field plates 32, 34 and 36 and the gate structure GS. A conductive layer 38 extends horizontally over the field plates 32, 34, 36 and the gate 20. In this embodiment, conductive layer 38 extends from a position P1 between electrode 22 and gate 20 to a position P2 between gate 20 and electrode 24 such that conductive layer 38 spans gate 20. The field plates 32, 34 and 36 are located directly under the conductive layer 38.

The contact via 40A is disposed above the field plate 34. The contact via 40A extends vertically in the direction D2 (i.e., the vertical direction) such that both ends of the contact via 40A are in contact with one of the field plates 32, 34, 36 and the conductive layer 38, respectively. In this embodiment, the contact via 40A extends vertically such that both ends of the contact via 40A are in contact with the field plate 34 and the conductive layer 38. The contact via 40A extends vertically downward. Since the contact via 40A connects the field plate 34 and the conductive layer 38, the contact via 40A can be used as a connection member.

Referring to fig. 1A, the contact via 40A extends in the direction D3 such that the contact via 40A has a bar-shaped profile in a top view of the semiconductor device 1A. The extension length of the contact via 40A in the direction D3 may be substantially the same as the extension length of the field plate 34. With this structure, the contact area between the contact via 40A and the field plate 34 can be increased, so that the contact resistance between the contact via 40A and the field plate 34 can be reduced. Thus, the conductive via 40A connects the field plate 34 and the conductive layer 38 such that the field plate 34 and the conductive layer 38 may have substantially the same voltage level. Therefore, the voltage distribution of the field plate 34 can be more uniform, so that the electric field distribution of the semiconductor device 1A is less likely to deviate from the desired electric field distribution. Accordingly, the semiconductor device 1A of the present disclosure can have good device performance.

Furthermore, in one aspect, the contact via 40A may act as a portion of a field plate extending in the vertical direction D2, and the contact via 40A having a bar-shaped profile may further mitigate the effect of high drain voltages on the gate 20.

In some embodiments, conductive layer 38 may be electrically coupled to a ground voltage level, so the voltage levels of conductive layer 38 and field plate 34 may be ground voltage levels. In other embodiments, conductive layer 38 may be electrically coupled to other suitable voltage levels, although the invention is not so limited.

Referring again to fig. 1A, each of the gate 20, electrodes 22, 24 extends in the direction D3 such that each of the gate 20, electrodes 22, 24 has a stripe-shaped profile in a top view of the semiconductor device 1A. That is, the contact via 40A, the gate 20, and the electrodes 22, 24 are substantially parallel to each other.

A dielectric layer 42 is disposed over the gate 20, electrodes 22, 24 and nitride-based semiconductor layer 16. Dielectric layer 42 covers gate 20, electrodes 22, 24 and nitride-based semiconductor layer 16 to protect these elements. Dielectric layer 42 may be referred to as a protective layer. The field plates 32, 34 and 36 are embedded in a dielectric layer 42. Each of the field plates 32, 34, and 36 is spaced apart from the gate 20 by at least a portion of the dielectric layer 42. The contact via 40A is disposed within the dielectric layer 42.

The material of dielectric layer 42 may include, but is not limited to, a dielectric material. For example, dielectric layer 42 may include, but is not limited to, siN _x,SiO_x,Si₃N₄, siON, siC, siBN, siCBN, oxide, nitride, plasma Enhanced Oxide (PEOX), or combinations thereof. In some embodiments, the dielectric layer 42 may be a multi-layer structure, such as a composite dielectric layer of Al ₂O₃/SiN,Al2O3/SiO₂,AlN/SiN,AlN/SiO₂ or a combination thereof. In some embodiments, the optional dielectric layer may be formed of a single layer or multiple layers of dielectric material. Exemplary dielectric materials may include, but are not limited to, one or more oxide layers, siO _x layers, siN _x layers, high-k dielectric materials (e.g., ,HfO₂,Al₂O₃,TiO₂,HfZrO,Ta₂O₃,HfSiO₄,ZrO₂,ZrSiO₂, etc.), or combinations thereof.

In addition, dielectric layer 42 may be used as a planarizing layer having a horizontal top surface to support other layers/elements. In some embodiments, dielectric layer 42 may be formed as a thicker layer and a planarization process (e.g., a Chemical Mechanical Polishing (CMP) process) is performed on dielectric layer 42 to remove excess portions, thereby forming a horizontal top surface.

In addition, the thickness of the dielectric layer 42 and the magnitude of the drain voltage of the semiconductor device 1A are factors that determine whether the conductive layer 38 is a field plate. In some cases, the thickness of dielectric layer 42 is small enough and/or the drain voltage of semiconductor device 1A is large enough that conductive layer 38 may significantly affect the electric field distribution of semiconductor device 1A. In this case, the conductive layer 38 covers the gate 20 so that the electric field peaks near the gate edge can be divided into more peaks, thereby achieving a more uniform electric field distribution. That is, in some cases, the conductive layer 38 may be used as the furthest field plate in the semiconductor device 1A. While the foregoing configuration may create parasitic/stray capacitance between gate 20 and conductive layer 38, conductive layer 38 is designed to be located higher than the other field plates 32, 34, and 36, thereby minimizing the negative effects of parasitic/stray capacitance between gate 20 and conductive layer 38.

In fig. 2A, 2B and 2C described below, different stages of a method for manufacturing the semiconductor device 1A are shown. Hereinafter, deposition techniques may include, but are not limited to, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), metal Organic CVD (MOCVD), plasma Enhanced CVD (PECVD), low Pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other processes.

Referring to fig. 2A, a substrate 10 is provided. A buffer layer 12 is formed on the substrate 10. A nitride-based semiconductor layer 14 is formed on the substrate 10 and the buffer layer 12. The nitride-based semiconductor layer 16 is formed on the nitride-based semiconductor layer 14. Electrodes 22, 24 are formed on the nitride-based semiconductor layer 16. A doped nitride-based semiconductor layer 18 is formed on the nitride-based semiconductor layer 16, wherein the doped nitride-based semiconductor layer 18 is located between the electrodes 22, 24. The gate electrode 20 is formed on the doped nitride-based semiconductor layer 18 and the nitride-based semiconductor layer 16. A plurality of field plates 30, 32 and 34 are formed on the nitride-based semiconductor layer 16. The field plates 30, 32 and 34 are located between the gate 20 and the electrode 24.

A blanket dielectric layer is then formed to cover the gate 20 and electrodes 22, 24 with the field plates 30, 32, 34 embedded in the dielectric layer 42. A mask layer ML is provided to cover a top surface of the blanket dielectric layer, thereby exposing at least a portion of the top surface of the blanket dielectric layer. An etching process is performed on the blanket dielectric layer to remove at least a portion of the blanket dielectric layer to form a trench T, thereby exposing a top surface of at least one field plate (e.g., field plate 34). The shape and location of the trench T also define the shape and location of the contact via 40A, where the trench T may be a stripe-shaped trench.

Referring to fig. 2B, a contact via 40A is formed to fill the trench T to contact the exposed field plate 34.

Referring to fig. 2C, conductive layer 38 is formed to contact via 40A such that conductive layer 38 is electrically coupled to one field plate (e.g., field plate 34) through contact via 40A. Conductive layer 38 covers field plates 32, 34 and 36 between gate 20 and electrode 24. In this way, the semiconductor device 1A in fig. 1A can be obtained.

Fig. 3A is a top view of a semiconductor device 1B according to some embodiments of the present disclosure. Fig. 3B is a vertical sectional view of the semiconductor device 1B in fig. 3A. The semiconductor device 1B is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the contact via 40B is located between the field plate 32 closest to the gate 20 and the conductive layer 38. The contact via 40B extends vertically such that both ends of the contact via 40B are in contact with the field plate 32 and the conductive layer. Thus, field plate 32 and conductive layer 38 have substantially the same voltage level.

Fig. 4A is a top view of a semiconductor device 1C according to some embodiments of the present disclosure. Fig. 4B is a vertical sectional view of the semiconductor device 1C in fig. 4A. The semiconductor device 1C is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the contact via 40C is located between the field plate 36 and the conductive layer 38 furthest from the gate 20, and thus the field plate 36 and the conductive layer 38 have substantially the same voltage level. In this way, the negative effects of parasitic/stray capacitance between the contact via 40C and the gate 20 can be further mitigated.

In the present disclosure, by simply adjusting the position of the contact via, the semiconductor device can achieve different electric field distributions to meet different device requirements.

Fig. 5 is a top view of a semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the contact via 40D includes a plurality of separate portions. Portions of the contact via 40D are separated from each other by a dielectric layer 42. Portions of the contact vias 40D are densely arranged in the direction D3 so that the contact area between the contact vias 40B and the field plate 34 can still be maintained at a high level. The portions of the contact through holes 40D are arranged at equal intervals in the direction D3.

Fig. 6A is a top view of a semiconductor device 1E according to some embodiments of the present disclosure. Fig. 6B is a vertical sectional view of the semiconductor device 1E in fig. 6A. The semiconductor device 6C is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the semiconductor device 1E includes at least two different types of contact vias 40E1, 40E2. The contact via 40E1 may have a stripe-shaped profile in a top view of the semiconductor device 1E, and the contact via 40E1 connects the conductive layer 38 and the field plate 34. The contact via 40E2 includes a plurality of separated portions arranged in the direction D3, and the contact via 40E2 connects the conductive layer 38 and the field plate 36. Thus, the field plates 34, 36 and the conductive layer 38 have substantially the same voltage level.

Fig. 7 is a top view of a semiconductor device 1F according to some embodiments of the present disclosure. The semiconductor device 1F is similar to the semiconductor device 1E described and illustrated with reference to fig. 6A and 6B, except that the semiconductor device 1F includes at least two contact vias 40F1, 40F2. The contact vias 40F1, 40F2 are of the same type, for example, in a top view of the semiconductor device 1F, they all have a bar-shaped profile.

Fig. 8 is a top view of a semiconductor device 1G according to some embodiments of the present disclosure. The semiconductor device 1G is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the semiconductor device 1G further includes a connection structure CS. Each of the field plates 32, 34, 36 and the conductive layer 38 are connected to a ground voltage level by a connection structure CS.

Fig. 9 is a vertical cross-sectional view of a semiconductor device 1H according to some embodiments of the present disclosure. The semiconductor device 1H is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the contact via 40H extends obliquely downward.

Fig. 10 is a vertical cross-sectional view of a semiconductor device 11 according to some embodiments of the present disclosure. The semiconductor device 11 is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the width of the contact via 40I is greater than the width of the gate 20.

Fig. 11 is a vertical cross-sectional view of a semiconductor device 1J according to some embodiments of the present disclosure. The semiconductor device 1J is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the width of the contact via 40J decreases in the opposite direction to the direction D2. The contact via 40J has an inverted trapezoidal profile in a vertical cross-sectional view of the semiconductor device 1J.

Fig. 12 is a vertical cross-sectional view of a semiconductor device 1K according to some embodiments of the present disclosure. The semiconductor device 1K is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the contact via 40K has a funnel-shaped profile in a vertical cross-sectional view of the semiconductor device 1K.

For the semiconductor devices 1J and 1K, since the area of the top surface of the trench of the dielectric layer 42 is larger than the area of the bottom surface, the contact via 40J/40K can be easily filled with the trench during the fabrication thereof.

Fig. 13 is a vertical cross-sectional view of a semiconductor device 1L according to some embodiments of the present disclosure. The semiconductor device 11 is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that a conductive layer 38L extends between the gate 20 and the electrode 24. Gate 20 is not covered by conductive layer 38L. In this way, the negative effects of parasitic/stray capacitance between the conductive layer 38L and the gate 20 can be further mitigated.

Fig. 14 is a top view of a semiconductor device 1M according to some embodiments of the present disclosure. The semiconductor device 1M is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the contact via 14M has at least one inclined surface in a top view of the semiconductor device 1M. Specifically, the contact via hole 14M has a parallelogram profile in a top view of the semiconductor device 1M. In some embodiments, the contact via 14M has a trapezoidal profile in a top view of the semiconductor device. In some embodiments, the contact via may have at least one curved surface in a top view of the semiconductor device. By the configuration, different equipment requirements can be met.

Fig. 15 is a top view of a semiconductor device 1N according to some embodiments of the present disclosure. The semiconductor device 1N is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the semiconductor device 1N further includes a plurality of contact via holes CV, each of which has a circular profile in a top view. The conductive layer 38 may be electrically connected to the field plate 32 through a contact via CV. Conductive layer 38 may be electrically connected to field plate 36 through another contact via CV.

In some embodiments, the conductive layer 38 may be electrically connected to the field plate 32 through a plurality of contact vias CV. Similarly, conductive layer 38 may be electrically connected to field plate 36 through a plurality of contact vias CV. But the present disclosure is not limited thereto.

Fig. 16A is a top view of a semiconductor device 1O according to some embodiments of the present disclosure. Fig. 16B is a vertical cross-sectional view of a semiconductor device 1O according to some embodiments of the present disclosure. The semiconductor device 1O is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the semiconductor device 1O comprises at least three contact vias 40O1, 40O2, 40O3. The contact vias 40O1, 40O2 and 40O3 are of the same type, for example, in a top view of the semiconductor device 1O, they all have a stripe-shaped profile. The conductive layer 38 may be electrically connected to the field plates 32, 34, 36 by contact vias 40O3, 40O1, 40O2, respectively.

Fig. 17 is a top view of a semiconductor device 1P according to some embodiments of the present disclosure. The semiconductor device 1P is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A and 1B, except that the contact via 40P includes different portions having different widths in the direction D1, and the contact area between the contact via 40P and the field plate can be further increased.

The different embodiments showing the structure of the device can be flexibly combined so that more requirements can be met. By leaving the gate vertically uncovered by the field plate, flexibility of the device can be achieved.

Based on the above, in the present invention, before the step of forming the conductive layer on the field plate, an etching process is performed on the dielectric layer to form a trench accommodating the contact via, thereby achieving a large contact area between the contact via and the field plate. The voltage distribution of the field plate may be more uniform and thus the device may have a desired electric field distribution.

Furthermore, the field plate is located between the gate and the drain, rather than on top of the gate. Thus, parasitic/stray capacitance between the gate and the field plate can be reduced. The semiconductor device of the present disclosure may be suitable for high frequency applications.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially," "essentially," "about," and "approximately" are used to describe and illustrate minor variations. When used in connection with an event or circumstance, the term can include instances where the event or circumstance occurs precisely and instances where it occurs approximately. For example, when used in conjunction with a numerical value, these terms may encompass a variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces lying along a same plane within a micrometer-scale distance, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm lying along the same plane.

As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may encompass a situation in which a previous component is disposed directly on (e.g., in physical contact with) a subsequent component, as well as a situation in which one or more intermediate components are located between the previous component and the subsequent component.

While the invention has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations are not necessarily drawn to scale. There may be a distinction between artistic reproductions and actual devices in the present invention due to manufacturing processes and tolerances. Further, it should be understood that the actual devices and layers may deviate from the rectangular layer depiction of the drawings due to fabrication processes such as conformal deposition, etching, etc., and may include corner surfaces or edges, rounded corners, etc. Other embodiments of the invention not specifically shown are possible. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present invention. All such modifications are intended to be included within the scope of the following claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present invention. Thus, unless specifically indicated herein, the order and grouping of operations is not limiting.

Claims

1. A semiconductor device comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer, wherein a band gap of the second nitride-based semiconductor layer is greater than a band gap of the first nitride-based semiconductor layer;

A drain electrode and a source electrode are disposed on the second nitride-based semiconductor layer;

A gate electrode disposed on the second nitride-based semiconductor layer and located between the drain electrode and the source electrode;

a plurality of field plates disposed on the second nitride-based semiconductor layer and located between the gate and the drain, wherein the gate is not covered by the field plates;

a conductive layer disposed on the field plate; and

At least one contact via connects one of the field plates to the conductive layer such that the field plate and the conductive layer have substantially the same voltage level.

2 . The semiconductor device according to claim 1 , wherein the contact via extends along a first direction such that the contact via has a stripe-shaped profile in a top view of the semiconductor device.

3. The semiconductor device according to claim 1, wherein each of the gate, drain and source electrodes extends in a first direction so that each of the gate, drain and source electrodes has a stripe-shaped profile in a top view of the semiconductor device.

4 . The semiconductor device according to claim 1 , wherein the contact via comprises a plurality of separated portions, and the separated portions are arranged along a first direction.

5 . The semiconductor device according to claim 4 , wherein the separation portions are arranged at equal intervals along the first direction.

The semiconductor device according to claim 1 , wherein the contact via extends downward to contact one of the field plates.

The semiconductor device according to claim 6 , wherein the contact via extends vertically downward.

The semiconductor device according to claim 6 , wherein the contact via extends obliquely downward.

9 . The semiconductor device according to claim 1 , wherein a width of the contact via is greater than a width of the gate.

10 . The semiconductor device according to claim 1 , wherein the conductive layer extends horizontally over the field plate.

11 . The semiconductor device of claim 1 , wherein each of the field plates is horizontally spaced apart from the gate.

12 . The semiconductor device of claim 1 , wherein the field plate is located directly below the conductive layer.

The semiconductor device according to claim 1 , wherein the field plates are located at different heights, respectively.

14. The semiconductor device of claim 1, wherein one of the field plates and the conductive layer are electrically coupled to a ground voltage level.

15. The semiconductor device of claim 1, further comprising a dielectric layer covering the gate, drain and source, wherein the field plate is embedded in the dielectric layer.

16. A method for manufacturing a semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming a source electrode and a drain electrode on the second nitride-based semiconductor layer;

forming a gate electrode on the second nitride-based semiconductor layer and between the source electrode and the drain electrode;

forming a plurality of field plates on the second nitride-based semiconductor layer, wherein the field plates are located between the gate and the drain;

forming a dielectric layer to cover the gate, source and drain, wherein the field plate is embedded in the dielectric layer;

removing at least a portion of the dielectric layer to expose a top surface of at least one of the field plates; and

forming at least one contact via to contact the exposed field plate; and

A conductive layer is formed to contact the contact via so that the conductive layer is electrically coupled to one of the field plates through the contact via.

17. The method of claim 16, wherein the step of removing at least a portion of the dielectric layer comprises:

An etching process is performed to form at least one trench in the dielectric layer to define the location of the contact via.

The method according to claim 17 , wherein the grooves are stripe-shaped grooves.

The method of claim 17 , wherein the contact via fills the trench.

20. The method of claim 16, wherein the field plate is directly beneath the conductive layer.

21. A semiconductor device comprising:

a first nitride-based semiconductor layer;

a plurality of field plates disposed on the second nitride-based semiconductor layer and between the gate and the drain;

a conductive layer extending horizontally over the gate and the field plate;

at least one connection member extending in a vertical direction to contact one of the field plates and the conductive layer; and

A dielectric layer covers the gate, source, and drain, wherein a portion of the dielectric layer is between each field plate and the gate such that each field plate is spaced apart from the gate by the dielectric layer.

22. The semiconductor device of claim 21, wherein the field plate is embedded in the dielectric layer.

23. The semiconductor device according to claim 21, wherein the at least one connection feature comprises a first connection feature connecting the conductive layer to one of the field plates and a second connection feature connecting the conductive layer to another of the field plates.

24 . The semiconductor device of claim 21 , further comprising a connection structure, wherein the connection structure grounds each of the field plates and the conductive layer.

25 . The semiconductor device according to claim 21 , wherein a width of the connection member decreases in a direction opposite to the vertical direction.