CN118201358A

CN118201358A - Semiconductor device and manufacturing method thereof, and electronic device

Info

Publication number: CN118201358A
Application number: CN202410606499.4A
Authority: CN
Inventors: 朱正勇; 康卜文; 赵超
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2024-05-15
Filing date: 2024-05-15
Publication date: 2024-06-14
Anticipated expiration: 2044-05-15
Also published as: CN118201358B; WO2025236563A1

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, relate to the field of semiconductor technology, and include: a multi-layer storage unit, a first word line, a second word line, and a third word line that penetrate the multi-layer; the second word line and the third word line are distributed along the second direction, and the storage unit includes a first transistor and a second transistor distributed along the first direction; the first transistor includes a first semiconductor layer that partially surrounds a first gate electrode and a second gate electrode that is arranged on the side of the first semiconductor layer away from the first gate electrode; the first gate electrodes at the same position of different layers extend vertically and are distributed at intervals; the partial area of the first gate electrode that is not surrounded by the first semiconductor layer is connected to the second semiconductor layer of the second transistor; the third word line is formed with a plurality of first grooves that are distributed at intervals and open toward the second word line, the first groove is distributed with a second semiconductor layer, and the second word line is formed with a protrusion that faces the first groove. The above scheme can realize the gating of a group of storage units without the need for a gating transistor, thereby simplifying the process.

Description

Semiconductor device, manufacturing method thereof and electronic equipment

Technical Field

Embodiments of the present disclosure relate to device design and fabrication thereof, and more particularly to a semiconductor device, a fabrication method thereof, and an electronic device.

Background

With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing, so that any minor differences in process production may affect the performance of the devices.

In order to reduce the cost of the product as much as possible, it is desirable to make as many device cells as possible on a limited substrate. Since moore's law emerged, various semiconductor structural designs and process optimizations have been proposed in the industry to meet the needs of people for current products.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The application provides a semiconductor device, a manufacturing method thereof and electronic equipment.

The present application provides a semiconductor device including: a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, a first word line extending in the direction perpendicular to the substrate penetrating the memory cells at the same position of the plurality of layers, a second word line extending in the direction perpendicular to the substrate penetrating the memory cells at the same position of the plurality of layers, and a third word line extending in the direction perpendicular to the substrate penetrating the memory cells at the same position of the plurality of layers;

the memory cell includes: a first transistor and a second transistor distributed along a first direction parallel to the substrate; the second word lines and the third word lines are distributed along a second direction parallel to the substrate, and the first direction and the second direction are intersected;

The first transistor includes: the first gate electrodes of the memory cells at the same positions of different layers extend along the direction perpendicular to the substrate and are distributed at intervals; the first semiconductor layer partially surrounds the first gate electrode; the second gate electrode is arranged on one side of the first semiconductor layer, which is away from the first gate electrode, and the second gate electrode of the first transistor at the same position of different layers is a part of the first word line;

The second transistor includes: a second semiconductor layer; a partial region of the first gate electrode, which is not surrounded by the first semiconductor layer, is connected to the second semiconductor layer; the second semiconductor layer partially surrounds the second word line; the third word line is provided with a plurality of first grooves with openings facing the second word line and distributed at intervals along the direction perpendicular to the substrate, the bottom wall and the side wall of the first grooves are distributed with the second semiconductor layer, and the second word line is provided with a plurality of protrusions facing the first grooves respectively.

In some embodiments, the first semiconductor layer includes a first semiconductor sub-layer and a second semiconductor sub-layer disposed on a side of the first semiconductor sub-layer facing away from the first gate electrode, the first semiconductor sub-layer partially surrounding the first gate electrode, the second semiconductor sub-layer having a doping concentration greater than that of the first semiconductor sub-layer, the second semiconductor sub-layer including a first portion and a second portion disposed at intervals on a surface of the first semiconductor sub-layer facing away from the first gate electrode.

In some embodiments, the first word line is distributed in a region between the first portion and the second portion on a sidewall of the first semiconductor sub-layer on a side facing away from the first gate electrode.

In some embodiments, the first transistor further includes a first electrode and a second electrode, the first electrode is connected to the first portion, the second electrode is connected to the second portion, the second portion surrounds the second electrode, and the second electrode connections of the first transistor at the same position of different layers form an integral structure extending in a direction perpendicular to the substrate.

In some embodiments, the first portions of the first transistors of a same column of the same layer distributed along the second direction are interconnected to form a unitary structure, and the second portions of the first transistors of a same column of the same layer distributed along the second direction are separated from each other.

In some embodiments, the first electrodes of the first transistors of a same column distributed along the second direction are connected to form a first bit line extending along the second direction.

In some embodiments, the second electrode and the first word line are disposed on the same side of the first portion and on the same side of the first gate electrode.

In some embodiments, the semiconductor device further comprises an isolation layer extending through the plurality of layers of the first transistor; the first gate electrode parts at the same positions of different layers encircle the isolation layer and are sequentially distributed in different areas of the side wall of the isolation layer along the direction vertical to the substrate.

In some embodiments, the first transistor further includes a first gate insulating layer disposed between the first gate electrode and the first semiconductor sub-layer, the first gate insulating layers of the first transistor at the same location of different layers being connected to form an integral structure extending in a direction perpendicular to the substrate.

In some embodiments, the semiconductor device further comprises:

The insulating layers and the conductive layers are alternately distributed from top to bottom in sequence along the direction vertical to the substrate;

a first hole, a second hole, and a third hole penetrating the insulating layer and the conductive layer;

The first hole is sequentially provided with the first semiconductor sub-layer, the first gate insulating layer, the first gate electrode and the isolation layer from outside to inside, and the isolation layer fills the first hole;

The second holes are sequentially distributed with a second grid insulating layer and the first word lines from outside to inside, and the first word lines fill the second holes;

only signal lines are distributed in the third holes, and the signal lines fill the third holes, and the second electrodes of the first transistors at the same positions of different layers are part of the signal lines.

In some embodiments, the first hole falls within the orthographic projection of the sub-hole of the insulating layer in the substrate, near the boundary of the first word line, near the boundary of the second word line, away from the boundary of the second word line, within the orthographic projection of the sub-hole of the first hole in the conductive layer, away from the boundary of the first word line, onto the boundary of the sub-hole of the first hole in the conductive layer in the orthographic projection of the substrate.

In some embodiments, the semiconductor device further comprises: the fourth hole penetrates through the insulating layer and the conducting layer, the second semiconductor layer, the third gate insulating layer and the second word line are sequentially distributed in the fourth hole from outside to inside, the second word line is filled in the fourth hole, the first gate electrode is exposed by the side wall of the fourth hole, the fourth hole is in orthographic projection of the insulating layer, the boundary close to the first gate electrode and the boundary close to the third word line fall into the orthographic projection of the conducting layer in the subhole of the conducting layer, the boundary away from the first gate electrode and the boundary away from the third word line fall on the boundary of the orthographic projection of the conducting layer in the substrate.

In some embodiments, the semiconductor device further includes a second groove disposed on a side of the second word line facing away from the first gate electrode and extending in a second direction, the second groove communicating with the fourth hole, an opening of the second groove facing away from the second word line and the third word line, and the second semiconductor layer further being distributed on a sidewall and a bottom wall of the second groove.

In some embodiments, the second semiconductor layers of the second transistors of the same column distributed along the second direction are disconnected.

In some embodiments, the semiconductor device further comprises: and second bit lines distributed in and filling the second grooves provided with the second semiconductor layer.

In some embodiments, the semiconductor device further comprises: a fifth hole penetrating through the insulating layer and the conductive layer, wherein a fourth gate insulating layer and the third word line are sequentially distributed in the fifth hole from outside to inside, and the third word line fills the fifth hole; and the boundary close to the second bit line and the boundary close to the second word line of the fifth hole in the orthographic projection of the sub-hole of the conducting layer on the substrate fall into the orthographic projection of the sub-hole of the fifth hole on the insulating layer on the substrate, and the boundary away from the second bit line and the boundary away from the second word line fall onto the boundary of the sub-hole of the fifth hole on the insulating layer on the orthographic projection of the substrate.

The embodiment of the disclosure provides a manufacturing method of a semiconductor device, comprising the following steps:

Providing a substrate, forming a stacked structure comprising alternately arranged functional layers and sacrificial layers on the substrate, wherein the stacked structure comprises a plurality of memory cell regions, and the memory cell regions comprise a first transistor region and a second transistor region which are distributed along a first direction parallel to the substrate;

Forming a first gate electrode and a first semiconductor layer which are arranged on the functional layer in the first transistor region, and forming a first word line penetrating through each layer along the direction perpendicular to a substrate, wherein the first semiconductor layer partially surrounds the first gate electrode, the first word line is arranged on one side of the first semiconductor layer, which is away from the first gate electrode, the first gate electrodes of the memory cells at the same position of different layers are stacked and distributed at intervals along the direction perpendicular to the substrate, and the second gate electrodes of the first transistors at the same position of different layers are part of the first word line;

forming a second word line, a third word line and a second semiconductor layer in the second transistor region; the first gate electrode is connected with the second semiconductor layer; the second semiconductor layer partially surrounds the second word line; the third word line is provided with a plurality of first grooves with openings facing the second word line and distributed at intervals along the direction perpendicular to the substrate, the bottom wall and the side wall of the first grooves are distributed with the second semiconductor layer, and the second word line is provided with a plurality of protrusions facing the first grooves respectively.

In some embodiments, forming a stacked structure including alternately arranged functional layers and sacrificial layers on the substrate includes:

sequentially depositing a semiconductor film and a sacrificial layer film on the substrate to form a stacked structure comprising alternately arranged semiconductor structure layers and sacrificial layers;

Patterning the stacked structure to form a T-shaped first trench penetrating through each layer, the first trench including a first sub-trench extending in a first direction and a second sub-trench extending from a non-end of the first sub-trench in a second direction parallel to the substrate; the memory cell area is arranged between adjacent first sub-grooves which are distributed at intervals along the second direction, and the first transistor area and the second transistor area are respectively arranged at two sides of the second sub-groove; the first direction and the second direction intersect;

And forming a first hole penetrating through the stacked structure in the direction perpendicular to the substrate at a first sub-groove of the first transistor region, which is close to one first groove, wherein the first sub-groove is exposed by the side wall of the first hole, removing the sacrificial layer through the first hole etching, and replacing the sacrificial layer with an insulating layer.

In some embodiments, forming a first gate electrode and a first semiconductor layer disposed on the functional layer in the first transistor region, and forming a first word line penetrating the layers in a direction perpendicular to the substrate includes:

etching the semiconductor structure layer in a direction parallel to the substrate based on the first hole; forming a plurality of first semiconductor sublayers, a first gate insulating layer, a plurality of gate electrodes and an isolation layer within the first hole; the first gate electrodes are distributed at intervals along the direction perpendicular to the substrate, the first semiconductor sublayers partially encircle the first gate electrodes and are distributed at intervals along the direction perpendicular to the substrate, the first gate insulating layer is arranged between the first semiconductor sublayers and the first gate electrodes, the first gate electrodes partially encircle the isolating layer, and the isolating layer fills the first holes;

Forming a second hole penetrating through the stacked structure in a direction perpendicular to the substrate at a first sub-trench of the first transistor region adjacent to another first trench, etching the semiconductor structure layer based on the second hole in a direction parallel to the substrate to expose the first semiconductor sub-layer, and sequentially forming a second gate insulating layer and a first word line filling the second hole in the second hole; the first and second holes space the semiconductor structure layer of the first transistor region into a second semiconductor sub-layer comprising separate first and second portions;

the method further comprises the steps of:

A third hole penetrating the stacked structure in a direction perpendicular to the substrate is formed between the second hole and the second sub-trench in the first transistor region, a sidewall of the third hole exposes a second portion of the second semiconductor sub-layer, and a signal line filling the third hole and contacting the second portion of the second semiconductor sub-layer is formed in the third hole.

In some embodiments, forming the second word line, the third word line, and the second semiconductor layer in the second transistor region includes:

Forming a fourth hole penetrating through the stacked structure in a direction perpendicular to the substrate in the second transistor region, and etching the semiconductor structure layer, the first semiconductor sub-layer and the first gate insulating layer to expose the first gate electrode based on the fourth hole in a direction parallel to the substrate to form a lateral groove; sequentially forming a second semiconductor layer, a third gate insulating layer and a second word line filling the fourth hole in the sequential fourth hole, wherein the second semiconductor layer is formed on the bottom wall and the side wall of the transverse groove;

Forming a fifth hole penetrating through the stacked structure in the direction perpendicular to the substrate in the second transistor region, wherein the fifth hole and the fourth hole are distributed in the second direction, etching the semiconductor structure layer, the insulating layer to expose the third gate insulating layer and the second semiconductor layer based on the fifth hole in the direction parallel to the substrate, and sequentially forming a fourth gate insulating layer and a third word line filling the fifth hole in the fifth hole.

In some embodiments, further comprising:

Forming second trenches penetrating each layer between adjacent first transistor regions along a first direction, the second trenches extending along a second direction; and laterally etching the semiconductor structure layer in the second groove without exposing the first semiconductor sub-layer to form a first lateral groove, and forming a first bit line filling the first lateral groove in the first lateral groove.

In some embodiments, further comprising:

Forming a third trench extending in the second direction penetrating each layer between second transistor regions adjacent in the first direction; laterally etching the semiconductor structure layer in the third groove to form a second lateral groove which is communicated with the fourth hole;

Forming the second semiconductor layer in the fourth hole, and forming the second semiconductor layer on the inner wall of the second lateral trench; and forming a second bit line filling the second lateral groove in the second lateral groove with the second semiconductor layer.

An embodiment of the present disclosure provides an electronic device including any one of the semiconductor devices described above, or a semiconductor device formed according to the method for manufacturing any one of the semiconductor devices described above.

The application includes a semiconductor device, a method of manufacturing the same, and an electronic apparatus, the semiconductor device including: a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, a first word line extending in the direction perpendicular to the substrate penetrating the memory cells at the same position of the plurality of layers, a second word line extending in the direction perpendicular to the substrate penetrating the memory cells at the same position of the plurality of layers, and a third word line extending in the direction perpendicular to the substrate penetrating the memory cells at the same position of the plurality of layers; the memory cell includes: a first transistor and a second transistor distributed along a first direction parallel to the substrate; the second word lines and the third word lines are distributed along a second direction parallel to the substrate, and the first direction and the second direction are intersected; the first transistor includes: a first gate electrode, a second gate electrode, and a first semiconductor layer; the first gate electrodes extend along the direction vertical to the substrate, and the first gate electrodes of the memory cells at the same position of different layers are stacked along the direction vertical to the substrate and distributed at intervals; the first semiconductor layer partially surrounds the first gate electrode; the second gate electrode is arranged on one side of the first semiconductor layer, which is away from the first gate electrode, and the second gate electrode of the first transistor at the same position of different layers is a part of the first word line; the second transistor includes: a second semiconductor layer; a partial region of the first gate electrode, which is not surrounded by the first semiconductor layer, is connected to the second semiconductor layer; the second semiconductor layer partially surrounds the second word line; the third word line is provided with a plurality of first grooves with openings facing the second word line and distributed at intervals along the direction perpendicular to the substrate, the bottom wall and the side wall of the first grooves are distributed with the second semiconductor layer, and the second word line is provided with a plurality of protrusions facing the first grooves respectively. The embodiment of the disclosure provides a 3D stacked semiconductor device of memory cells including transistors with double word lines, which can gate the corresponding memory cells by applying an electric signal on the corresponding word lines without separately setting a gating transistor to realize the gating of the memory cells, and can simplify the peripheral gating circuit structure and the manufacturing process of the memory cells.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the principles of the application, and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the principles of the application.

Fig. 1A is a top view of a semiconductor device provided in some embodiments, fig. 1B is a cross-sectional view perpendicular to a substrate along the direction AA ' in fig. 1A, fig. 1C is a cross-sectional view perpendicular to a substrate along the direction BB ' in fig. 1A, fig. 1D is a cross-sectional view perpendicular to a substrate along the direction CC ' in fig. 1A, fig. 1E is a cross-sectional view perpendicular to a substrate along the direction DD ' in fig. 1A, and fig. 1F is a cross-sectional view parallel to a substrate along the direction FF ' in fig. 1B; fig. 1G is an equivalent circuit diagram of a semiconductor device provided by an exemplary embodiment;

FIG. 2A is a top view of a stack formed in accordance with some embodiments, and FIG. 2B is a cross-sectional view perpendicular to the substrate taken along the AA' direction in FIG. 2A;

Fig. 3A is a top view of a first trench and a first insulating layer formed in accordance with some embodiments, and fig. 3B is a cross-sectional view perpendicular to the substrate along the direction EE' in fig. 3A;

FIG. 4A is a top view of some embodiments after formation of a first initial aperture, and FIG. 4B is a cross-sectional view perpendicular to the substrate taken along the direction AA' in FIG. 4A;

FIG. 5A is a top view of a second insulating layer formed in accordance with some embodiments, and FIG. 5B is a cross-sectional view perpendicular to the substrate taken along the direction AA' in FIG. 5A;

FIG. 6A is a top view of some embodiments after exposure of the first initial aperture, and FIG. 6B is a cross-sectional view perpendicular to the substrate taken along the direction AA' in FIG. 6A;

FIG. 7A is a top view of some embodiments after forming a first recess, and FIG. 7B is a cross-sectional view perpendicular to the substrate taken along the direction AA' in FIG. 7A;

FIG. 8A is a top view of a first semiconductor structure layer formed in accordance with some embodiments, and FIG. 8B is a cross-sectional view perpendicular to the substrate taken along the direction AA' in FIG. 8A;

Fig. 9A is a top view of a first semiconductor sub-layer formed in accordance with some embodiments, and fig. 9B is a cross-sectional view perpendicular to the substrate along direction AA' in fig. 9A;

Fig. 10A is a top view of a first conductive layer and a first gate insulating layer formed in accordance with some embodiments, and fig. 10B is a cross-sectional view perpendicular to the substrate along the direction AA' in fig. 10A;

FIG. 11A is a top view of a first gate electrode formed in accordance with some embodiments, and FIG. 11B is a cross-sectional view perpendicular to the substrate taken along the direction AA' in FIG. 11A;

FIG. 12A is a top view of a second initial via and third recess formed in accordance with some embodiments, FIG. 12B is a cross-sectional view perpendicular to the substrate taken along the BB 'direction in FIG. 12A, and FIG. 12C is a cross-sectional view perpendicular to the substrate taken along the CC' direction in FIG. 12A;

Fig. 13A is a top view of a second gate insulating layer and a first word line formed in accordance with some embodiments, fig. 13B is a cross-sectional view perpendicular to the substrate along the direction BB 'in fig. 13A, and fig. 13C is a cross-sectional view perpendicular to the substrate along the direction CC' in fig. 13A;

FIG. 14A is a top view of the third hole formed in accordance with some embodiments, and FIG. 14B is a cross-sectional view perpendicular to the substrate taken along the BB' direction in FIG. 14A;

FIG. 15A is a top view of a signal line formed in accordance with some embodiments, and FIG. 15B is a cross-sectional view perpendicular to the substrate taken along the BB' direction in FIG. 15A;

FIG. 16A is a top view of the second trench formed as provided in some embodiments, and FIG. 16B is a cross-sectional view perpendicular to the substrate taken along the BB' direction in FIG. 16A;

FIG. 17A is a top view of a first bit line layer formed in accordance with some embodiments, and FIG. 17B is a cross-sectional view perpendicular to the substrate taken along the BB' direction in FIG. 17A;

FIG. 18A is a top view of a first bit line and a fourth insulating layer formed in accordance with some embodiments, and FIG. 18B is a cross-sectional view perpendicular to the substrate taken along the BB' direction in FIG. 18A;

FIG. 19A is a top view of a fourth initial via and third trench formed as provided in some embodiments, FIG. 19B is a cross-sectional view perpendicular to the substrate along the direction AA 'in FIG. 19A, and FIG. 19C is a cross-sectional view perpendicular to the substrate along the direction DD' in FIG. 19A;

FIG. 20A is a top view of a fifth recess formed in accordance with some embodiments, FIG. 20B is a cross-sectional view taken along the direction AA 'of FIG. 20A and perpendicular to the substrate, and FIG. 20C is a cross-sectional view taken along the direction DD' of FIG. 20A;

Fig. 21A is a top view of a third semiconductor structure layer formed in accordance with some embodiments, fig. 21B is a cross-sectional view perpendicular to the substrate along direction AA 'in fig. 21A, and fig. 21C is a cross-sectional view perpendicular to the substrate along direction DD' in fig. 21A;

Fig. 22A is a top view of a second semiconductor layer formed in accordance with some embodiments, fig. 22B is a cross-sectional view perpendicular to the substrate along direction AA 'in fig. 22A, and fig. 22C is a cross-sectional view perpendicular to the substrate along direction DD' in fig. 22A;

FIG. 23A is a top view of a sixth recess formed in accordance with some embodiments, and FIG. 23B is a cross-sectional view perpendicular to the substrate taken along the direction AA' in FIG. 23A;

FIG. 24A is a top view of a second bit line layer formed in accordance with some embodiments, and FIG. 24B is a cross-sectional view perpendicular to the substrate taken along the direction AA' in FIG. 24A;

FIG. 25A is a top view after formation of a second bit line, and FIG. 25B is a cross-sectional view perpendicular to the substrate taken along the direction AA' in FIG. 25A, as provided by some embodiments;

fig. 26A is a top view of a second word line and a third gate insulating layer formed in accordance with some embodiments, fig. 26B is a cross-sectional view perpendicular to the substrate along the direction AA 'in fig. 26A, and fig. 26C is a cross-sectional view perpendicular to the substrate along the direction DD' in fig. 26A;

Fig. 27A is a top view of a fifth initial via formed in accordance with some embodiments, fig. 27B is a cross-sectional view perpendicular to the substrate along the direction BB 'in fig. 27A, and fig. 27C is a cross-sectional view perpendicular to the substrate along the direction DD' in fig. 27A.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments of the present disclosure and features in the embodiments may be arbitrarily combined with each other without collision.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs.

Embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, the shapes and sizes of the various components in the drawings do not reflect true proportions. Furthermore, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or the numerical values shown in the drawings.

The ordinal numbers of "first", "second", "third", etc. in the present disclosure are provided to avoid intermixing of constituent elements, and do not denote any order, quantity, or importance.

In the present disclosure, for convenience, terms such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe positional relationships of the constituent elements with reference to the drawings, only for convenience in describing the present specification and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the disclosure, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, it may be a physical connection or a signal connection, it may be a contact connection or an integral connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Thus, in this disclosure, the "source electrode" and the "drain electrode" may be interchanged.

In this disclosure, "connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, for example, and thus, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, for example, and thus includes a state in which an angle is 85 ° or more and 95 ° or less.

The "a and B integrated structure" in the embodiments of the present disclosure may refer to a microstructure without obvious boundary interfaces such as obvious faults or gaps. Typically, the connected film layers are patterned on one film layer as one piece. For example, a and B use the same material to form a film and simultaneously form a structure with a connection relationship through the same patterning process.

In the embodiment of the disclosure, the "the front projection of B is located within the range of the front projection of a" means that the boundary of the front projection of B falls within the boundary range of the front projection of a, or the boundary of the front projection of a overlaps with the boundary of the front projection of B.

Fig. 1A is a top view of a semiconductor device according to some embodiments, and fig. 1B is a cross-sectional view perpendicular to a substrate 1 along the AA' direction in fig. 1A; fig. 1C is a sectional view perpendicular to the substrate 1 along the direction BB ' in fig. 1A, fig. 1D is a sectional view perpendicular to the substrate 1 along the direction DD ' in fig. 1A, and fig. 1E is a sectional view perpendicular to the substrate 1 along the direction DD ' in fig. 1A. Fig. 1F is a sectional view parallel to the substrate 1 along the FF' direction in fig. 1B. As shown in fig. 1A to 1F, the embodiment of the present disclosure provides a semiconductor device including a multi-layered memory cell array vertically stacked on a substrate 1, which may be distributed along a third direction Z. The third direction Z may be perpendicular to the substrate 1.

The memory cell array may include a plurality of first bit lines 31, a plurality of second bit lines 32, a plurality of first word lines 40a, a plurality of second word lines 40b, a plurality of third word lines 40c, and a plurality of memory cells. Each of the memory cell arrays may include a plurality of memory cells distributed in an array in a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y may intersect. Every two columns of memory cells are grouped.

As shown in fig. 1B and 1C, the first bit line 31 may be a conductive line extending in a second direction Y parallel to the substrate 1. The second bit lines 32 may be conductive lines extending in a second direction Y parallel to the substrate 1. The plurality of first bit lines 31 of the same memory cell array may be spaced apart from each other, and the plurality of first bit lines 31 of the same memory cell array may be spaced apart along the first direction X. The plurality of second bit lines 32 of the same memory cell array may be spaced apart from each other, and the plurality of second bit lines 32 of the same memory cell array may be spaced apart along the first direction X. The first bit lines 31 of different memory cell arrays may be stacked on the substrate 1, with the first bit lines 31 of the same position of different layers being spaced apart from each other. The second bit lines 32 of different memory cell arrays may be stacked on the substrate 1, with the second bit lines 32 of the same position of different layers being spaced apart from each other.

Each column of memory cells is connected to the same first bit line 31 and the same second bit line 32, and two second bit lines 32 respectively connected to two columns of memory cells of the same group are provided between two first bit lines 31 respectively connected to two columns of memory cells of the group.

The memory cell includes a first transistor and a second transistor. The first and second transistors of the same memory cell may be distributed along the first direction X.

The first, second and third word lines 40a, 40b, 40c may extend in the third direction Z, and a plurality of memory cells stacked in the vertical direction at the same position of different layers share one first word line 40a, one second word line 40b, and one third word line 40c; different memory cells of the same layer correspond to different first word lines 40a, and to different second word lines 40b, and to different third word lines 40c.

The following description will be given by taking a semiconductor device including a plurality of vertically stacked memory cells in the same position as an example, and taking 2T0C as an example.

As shown in fig. 1A to 1F, the embodiment of the present disclosure provides a semiconductor device including:

A substrate 1, at least one memory cell disposed on the substrate 1, the memory cell may include a first transistor and a second transistor, the first transistor may include a first gate electrode 26a, a second gate electrode 26b, a first electrode 51 and a second electrode 52, and a first semiconductor layer 23a. The second transistor may include a third gate electrode 26c, a fourth gate electrode 26d, a third electrode 53, and a fourth electrode 54, a second semiconductor layer 23b. The second semiconductor layer 23b partially surrounds the second word line 40b; the third word line 40c is formed with a plurality of first grooves which are open toward the second word line 40b and are spaced apart in a direction perpendicular to the substrate 1, the bottom wall and the side wall of the first grooves are distributed with the second semiconductor layer 23b, and the second word line 40b is formed with a plurality of protrusions which are open toward the plurality of first grooves, respectively.

According to the scheme provided by the embodiment, the second transistor of the corresponding memory cell is gated by the double word lines, the gating transistor is not required to be independently arranged, the gating of the corresponding memory cell in the memory array can be realized, and the peripheral gating circuit structure and the manufacturing process of the memory array can be simplified.

The first gate electrode 26a may extend in a direction perpendicular to the substrate 1, the first gate electrode 26a may form a recess having an opening direction facing away from the first word line 40a, and the recess formed by the first gate electrode 26a may include a bottom wall extending in the direction perpendicular to the substrate 1 and two sidewalls extending in the direction perpendicular to the substrate 1. The first gate electrodes 26a of the memory cells at the same position of different layers extend in a direction perpendicular to the substrate 1 and are spaced apart.

For example, the first gate electrode 26a may include one bottom wall extending in parallel to the first direction X and perpendicular to the substrate 1, and two side walls extending in parallel to the second direction Y and perpendicular to the substrate 1.

The first semiconductor layer 23a may include a first semiconductor sub-layer 231 and a second semiconductor sub-layer 232, and the first semiconductor sub-layer 231 may extend in a direction perpendicular to the substrate 1, and the first semiconductor sub-layer 231 is distributed on an outer sidewall of a groove (i.e., an outer surface of the groove) formed by the first gate electrode 26a and partially surrounds the first gate electrode 26a.

The second semiconductor sublayer 232 is disposed on a side of the first semiconductor sublayer 231 facing away from the first gate electrode 26a, the doping concentration of the second semiconductor sublayer 232 is greater than that of the first semiconductor sublayer 231, and the second semiconductor sublayer 232 may include a first portion 2321 and a second portion 2322 disposed at intervals on a surface of the first semiconductor sublayer 231 facing away from the first gate electrode 26 a. According to the scheme, the sub-layer with high doping concentration is arranged on the outer side wall of the sub-layer with low doping concentration, so that the sub-layer with low doping concentration and the sub-layer with high doping concentration are formed in advance, additional complicated doping operation in the manufacturing process of the semiconductor device is avoided, and the process is simplified.

The second semiconductor sublayer 232 may be a heavily doped semiconductor film layer, and the first semiconductor sublayer 231 may be a lightly doped or undoped semiconductor film layer, so that the first semiconductor sublayer 231 is conveniently used as a channel region of the first transistor, and two parts of the second semiconductor sublayer 232 are respectively used as a source contact region and a drain contact region of the second transistor and are respectively contacted with a source electrode and a drain electrode.

In some embodiments, the height of the first portion 2321 of the second semiconductor sub-layer 232 along a direction perpendicular to the substrate 1 may be the same or substantially the same as the height of the second portion 2322 of the second semiconductor sub-layer 232 along a direction perpendicular to the substrate 1.

The first electrode 51 is connected to the first portion 2321 of the second semiconductor sublayer 232, and the first electrode 51 is disposed on a side of the first portion 2321 facing away from the first gate electrode 26 a.

In some embodiments, the second semiconductor sublayer 232 may extend in a second direction Y parallel to the substrate 1. The solution facilitates the second semiconductor sub-layer 232 to be obtained by stacking the semiconductor film layers with high doping concentration and etching the semiconductor film layers without doping the semiconductor layers of different layers.

In some embodiments, as shown in fig. 1F, the first portions 2321 of the second semiconductor sub-layers 232 of the first transistors of the same column of the same layer distributed along the second direction Y direction may be connected to form a unitary structure. The unitary structure may extend in the second direction Y. The embodiments of the present disclosure are not limited thereto and the first portions 2321 of the second semiconductor sub-layers 232 of the same column of transistors, which are arranged in the second direction Y direction, of the same layer may be separated from each other.

In some embodiments, as shown in fig. 1F, the second portions 2322 of the second semiconductor sub-layers 232 of the first transistors of the same column of the same layer distributed along the second direction Y direction may be separated from each other.

In some embodiments, the first bit line 31 may be a stripe-shaped electrode parallel to the substrate 1, a portion of the stripe-shaped electrode may be the first electrode 51 of the first transistor, a sidewall of the stripe-shaped electrode is connected with the first portion 2321 of the second semiconductor sub-layer 232, or the first bit line 31 may have a branch integrally designed, and the branch is connected with the first portion 2321 of the second semiconductor sub-layer 232, wherein an extension direction of the branch intersects with, such as is approximately perpendicular to, an extension direction of the first bit line 31, and the branch may be the first electrode 51 of the first transistor.

The branches may be a plurality of branches on one sidewall of the first bit line 31, each branch being correspondingly connected to the first portion 2321 of the second semiconductor sub-layer 232 of one first transistor.

In some embodiments, a first gate insulating layer 24a extending in a direction perpendicular to the substrate 1 is disposed between the first semiconductor sublayer 231 and the first gate electrode 26 a.

In some embodiments, the first gate insulating layers 24a of the plurality of first transistors at the same position of different layers may be connected to form a unitary structure. The solution provided in this embodiment facilitates the formation of the first gate insulating layers 24a of the plurality of first transistors at one time, and can simplify the process.

In some embodiments, the first gate electrodes 26a of the plurality of first transistors at the same location in different layers are spaced apart from each other, e.g., physically disconnected.

In some embodiments, the semiconductor device may further include an isolation layer 13 extending through the plurality of first transistors in a direction perpendicular to the substrate 1, the first gate electrode 26a partially surrounds the isolation layer 13, the plurality of first gate electrodes 26a of the plurality of first transistors at the same position of different layers partially surrounds different regions of the isolation layer 13, that is, the plurality of first gate electrodes 26a of the plurality of first transistors at the same position of different layers are sequentially distributed in different regions of a sidewall of the isolation layer 13 in the direction perpendicular to the substrate 1, the first gate insulating layer 24a partially surrounds the isolation layer 13, and the first semiconductor sub-layer 231 partially surrounds the isolation layer 13.

In some embodiments, as shown in fig. 1F, the isolation layer 13 is close to one first sub-trench, the first gate electrode 26a partially surrounds the isolation layer 13, and does not surround the isolation layer 13 toward the side of the close first sub-trench, i.e., the first gate electrode 26a surrounds three sidewalls of the isolation layer 13; the first gate insulating layer 24a surrounds the isolation layer 13 and has a notch only on a side facing the second transistor region to expose the first gate electrode 26a; the first semiconductor sub-layer 231 is distributed on the outer sidewall of the first gate electrode 26a and has a notch on the side facing the second transistor to expose the first gate electrode 26a. A partial region of the first gate electrode 26a which is not surrounded by the first semiconductor layer 23a is connected to the second semiconductor layer 23 b. The second semiconductor layer 23b and the first semiconductor sublayer 231 are separated by a first gate insulating layer 24 a.

In some embodiments, the second electrode 52 is connected to the second portion 2322 of the second semiconductor sublayer 232, which second portion 2322 may surround the second electrode 52. In some embodiments, the second portion 2322 may completely surround the second electrode 52, or partially surround the second electrode 52. When the second portion 2322 partially surrounds the second electrode 52, the area occupied by the second portion 2322 is smaller, which may reduce the device area.

In some embodiments, the second gate electrode 26b may be part of a first word line 40a, and the second gate electrode 26b of the first transistor in the same location in different layers may be part of the same first word line 40 a.

In some embodiments, the first word line 40a may be distributed in a region between the first portion 2321 and the second portion 2322 on a sidewall of the first semiconductor sublayer 231 on a side facing away from the first gate electrode 26 a.

In some embodiments, the second electrode 52 and the first word line 40a may be disposed on the same side of the first portion 2321, and on the same side of the first gate electrode 26 a.

In some embodiments, the third gate electrode 26c may be part of the second word line 40b, and the third gate electrode 26c of the second transistor in the same location in a different layer may be part of the same second word line 40 b.

In some embodiments, the fourth gate electrode 26d may be part of the third word line 40c, and the fourth gate electrode 26d of the second transistor in the same location in a different layer may be part of the same third word line 40 c.

In some embodiments, the first electrode 51 may be connected to the first bit line 31, or the first electrode 51 may be a part of the first bit line 31. The first electrodes 51 of the first transistors of the memory cells of the same column of the same memory cell array may be connected to the same first bit line 31. That is, the first electrodes 51 of the first transistors of the same column distributed along the second direction Y are connected to form a first bit line 31 extending along the second direction Y. The first electrodes 51 of the transistors of the memory cells of adjacent columns of the same memory cell array may be connected to different first bit lines 31.

In some embodiments, the fourth electrode 54 may be connected to the second bit line 32, or the fourth electrode 54 may be part of the second bit line 32. The fourth electrodes 54 of the first transistors of the memory cells of the same column of the same memory cell array may be connected to the same second bit line 32. That is, the fourth electrodes 54 of the first transistors of the same column distributed along the second direction Y are connected to form a second bit line 32 extending along the second direction Y. The fourth electrodes 54 of the transistors of the memory cells of adjacent columns of the same memory cell array may be connected to different second bit lines 32.

In some embodiments, the first gate electrode 26a may be connected to the third electrode 53, or the first gate electrode 26a and the third electrode 53 may multiplex the same electrode.

The second electrodes 52 of the first transistors at the same location of the different layers may be connected. The semiconductor device may further include a signal line 52 'extending in a direction perpendicular to the substrate 1, the signal line 52' being formed by connecting the second electrodes 52 at the same positions of different layers.

In some embodiments, the semiconductor device may include a T-shaped first trench T1 extending through the layers in a direction perpendicular to the substrate 1, the first trench T1 may include a first sub-trench extending in a first direction X and a second sub-trench extending from a non-end of the first sub-trench in a second direction Y parallel to the substrate; adjacent first sub-grooves distributed at intervals along the second direction Y define a storage unit area, two sides of the second sub-groove in the storage unit area are respectively called a first transistor area and a second transistor area, and the first transistor area and the second transistor area are communicated and are not completely separated by the second sub-groove. The first trench T1 may be filled with the first insulating layer 11. The first gate electrode 26a, the first word line 40a, and the signal line 52' may be disposed in a first transistor region, the third word line 40c may be disposed in a second transistor region, the second semiconductor layer 23b may be disposed in the second transistor region, and the second word line 40b may be disposed in the second transistor region and extend from the second transistor region to the first transistor region to be connected to the first gate electrode 26 a. The first word lines 40a, the signal lines 52', and the third word lines 40c may be distributed along the first direction X, and the first gate electrodes 26a and the second word lines 40b may be distributed along the first direction X. This arrangement makes it possible to distribute the first word line 40a, the signal line 52', and the third word line 40c in the first direction X while satisfying the connection of the first gate electrode 26a and the second semiconductor layer 23b, to make the layout as compact as possible, and to reduce the device area.

In some embodiments, the semiconductor device may further include:

Insulating layers and conductive layers alternately distributed in turn from top to bottom along a direction perpendicular to the substrate 1;

the first holes are sequentially distributed with the first semiconductor sub-layer 231, the first gate insulating layer 24a, the first gate electrode 26a and the isolation layer 13 from outside to inside, and the isolation layer 13 fills the first holes;

the second holes are sequentially distributed with a second gate insulating layer 24b and the first word lines 40a from outside to inside, and the first word lines 40a fill the second holes;

only the signal lines 52 'are distributed in the third holes, and the signal lines 52' fill the third holes.

In some embodiments, the first hole falls within the orthographic projection of the sub-hole of the insulating layer on the substrate 1, near the boundary of the first word line 40a, near the boundary of the second word line 40b, and away from the boundary of the second word line 40b, and the boundary of the first hole falls within the orthographic projection of the sub-hole of the conductive layer on the substrate 1, and away from the boundary of the first word line 40a, and the boundary of the sub-hole of the conductive layer falls on the orthographic projection of the first hole on the substrate 1. That is, one sidewall of the first hole exposes the first insulating layer 11 located in the first sub-trench, and the first hole extends straight toward the boundary of the first sub-trench in a direction perpendicular to the substrate 1. According to the scheme provided by the embodiment, the size of the first transistor area along the second direction can be reduced as much as possible, and the area of the device is reduced.

In some embodiments, the second hole may have a smaller pore diameter than the sub-hole of the insulating layer.

In some embodiments, the aperture of the sub-aperture of the third aperture in the insulating layer may be equal to the aperture of the sub-aperture of the third aperture in the conductive layer. According to the scheme provided by the embodiment, the third hole can be formed at one time, and the process is simple.

In some embodiments, the semiconductor device may further include: the fourth hole penetrates through the insulating layer and the conductive layer, the second semiconductor layer 23b, the third gate insulating layer 24c and the second word line 40b are sequentially distributed in the fourth hole from outside to inside, the second word line 40b fills the fourth hole, the side wall of the fourth hole exposes the first gate electrode 26a, the boundary of the fourth hole close to the first gate electrode 26a and the boundary of the third word line 40c fall into the orthographic projection of the fourth hole in the conductive layer in the substrate 1, and the boundary of the sub hole away from the first gate electrode 26a and the boundary of the sub hole away from the third word line 40c fall onto the boundary of the fourth hole in the orthographic projection of the conductive layer in the substrate 1. As shown in fig. 1B, the fourth hole extends straight away from the sidewall of the first gate electrode 26a in the insulating layer and the conductive layer in a direction perpendicular to the substrate 1. As shown in fig. 1E, one sidewall of the fourth hole exposes the first insulating layer 11 located in the first sub-trench, and the fourth hole extends straight in the insulating layer and the conductive layer in a direction perpendicular to the substrate 1 toward the sidewall of the first sub-trench (i.e., away from the sidewall of the third word line 40 c). According to the scheme provided by the embodiment, the size of the second transistor area along the second direction can be reduced as much as possible, and the area of the device is reduced.

In some embodiments, the semiconductor device may further include a second groove disposed at a side of the second word line 40b facing away from the first gate electrode 26a and extending in a second direction, the second groove communicating with the fourth hole, an opening of the second groove facing away from the second word line 40b and the third word line 40c, and the second semiconductor layer 23b further distributed at a sidewall and a bottom wall of the second groove. The second bit lines are distributed in and fill the second grooves, so that the second bit lines 32 can be connected with the second semiconductor layer 23b distributed at the bottom wall and the side walls of the second grooves.

In some embodiments, the second semiconductor layers 23b of the second transistors of the same column distributed along the second direction Y are disconnected from each other. As shown in fig. 1F, the second semiconductor layers 23b are distributed at partial regions of the second holes toward the sidewalls of the adjacent first sub-trenches, so that the second semiconductor layers 23b of the second transistors adjacent in the second direction are disconnected.

In some embodiments, the semiconductor device may further include: a fifth hole penetrating through the insulating layer and the conductive layer, wherein the fifth hole is sequentially provided with a fourth gate insulating layer 24b and a third word line 40c from outside to inside, and the third word line 40c fills the fifth hole; and the boundary near the second bit line 32 and the boundary near the second word line 40b of the fifth hole in the front projection of the sub-hole of the conductive layer on the substrate 1 fall within the front projection of the sub-hole of the fifth hole on the insulating layer on the substrate 1, and the boundary away from the second bit line 32 and the boundary away from the second word line 40b fall on the boundary of the fifth hole on the front projection of the sub-hole of the insulating layer on the substrate 1. As shown in fig. 1C, the side walls of the fifth holes facing away from the second bit lines 32 extend straight in the insulating layer and the conductive layer in a direction perpendicular to the substrate 1. As shown in fig. 1E, the side wall of the fifth hole facing away from the second word line 40b extends straight in the insulating layer and the conductive layer in a direction perpendicular to the substrate 1.

Fig. 1G is an equivalent circuit schematic diagram of a memory cell of a semiconductor device according to an exemplary embodiment. As shown in fig. 1G, the memory cell may include a first transistor T1 and a second transistor T2, wherein a first electrode 51 of the first transistor T1 is connected to the first bit line 31, a second electrode 52 is connected to the reference voltage terminal Vrefn, a second gate electrode 26b is connected to the first word line 40a, and a first gate electrode 26a is connected to a third electrode 53 of the second transistor T2; the fourth electrode 54 of the second transistor T2 is connected to the second bit line 32, the third gate electrode 26c (for distinction from the first gate electrode 26a and the second gate electrode 26b of the first transistor, it does not represent that the second transistor T2 has three gate electrodes, the subsequent fourth gate electrode 26d is similar) is connected to the second word line 40b, and the fourth gate electrode 26d is connected to the third word line 40c. The memory cell may further include a storage node SN, which may include the first gate electrode 26a of the first transistor T1.

In some embodiments, the first transistor T1 may be a read transistor, the second transistor T2 may be a write transistor, the first bit line 31 may be a read bit line RBL, the second bit line 32 may be a write bit line WBL, the first word line 40a may be a read word line, the second word line 40b may be a first write word line WWL1, and the third word line 40c may be a second write word line WWL2. In this circuit, when the first write word line WWL1 and the second write word line WWL2 both load an activation signal, the second transistor T2 is turned on, and when at least one of the first write word line WWL1 and the second write word line WWL2 loads an deactivation signal, the second transistor T2 is turned off.

Taking the first transistor T1 and the second transistor T2 as N-type transistors as an example. When the first write word line WWL1 and the second write word line WWL2 are both loaded with a high level signal, that is, when the third gate electrode 26c and the fourth gate electrode 26d of the second transistor T2 are both loaded with a high level signal, the second transistor T2 is turned on. When at least one of the first write word line WWL1 and the second write word line WWL2 is loaded with a low level signal, the second transistor T2 is turned off. In another exemplary embodiment, when the first transistor T1 and the second transistor T2 are P-type transistors, the second transistor T2 is turned on when the first write word line WWL1 and the second write word line WWL2 are both loaded with a low level signal, and the second transistor T2 is turned off when at least one of the first write word line WWL1 and the second write word line WWL2 is loaded with a high level signal.

In some embodiments, the second word lines 40b of the same row distributed along the first direction X may be connected together, i.e., to one first common word line, and the third word lines 40c of the same column distributed along the second direction Y may be connected together, i.e., to one second common word line; or the second word lines 40b of the same column distributed along the second direction Y may be connected together, i.e., to one first common word line, and the third word lines 40c of the same row distributed along the first direction X may be connected together, i.e., to one second common word line. In this scheme, by activating a first common word line and a second common word line, a memory cell of a vertical column (i.e., a group of memory cells in the same position in different layers) can be selected.

The technical scheme of the present embodiment is further described below through the manufacturing process of the semiconductor device of the present embodiment. The "patterning process" in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, photoresist stripping, etc., and is a well-known manufacturing process in the related art. The "photolithography process" described in this embodiment includes coating a film layer, mask exposure and development, and is a well-known manufacturing process in the related art. The deposition may be performed by known processes such as sputtering, vapor deposition, chemical vapor deposition, etc., the coating may be performed by known coating processes, and the etching may be performed by known methods, which are not particularly limited herein. In the description of the present embodiment, it is to be understood that "thin film" refers to a thin film manufactured by depositing or coating a certain material on a substrate. The "thin film" may also be referred to as a "layer" if the "thin film" does not require a patterning process or a photolithography process throughout the manufacturing process. If the "thin film" also requires a patterning process or a photolithography process throughout the manufacturing process, it is referred to as a "thin film" before the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

In an exemplary embodiment, the manufacturing process of the semiconductor device may include:

1) Forming a stacked structure;

The forming of the stacked structure may include: providing a substrate 1, alternately depositing a first semiconductor thin film and a sacrificial layer thin film on the substrate 1, and forming a stacked structure including a plurality of second semiconductor structure layers 232' and sacrificial layers 10 alternately arranged;

A hard mask film is deposited to form a hard mask layer 9. At this time, the stacked structure includes a plurality of second semiconductor construction layers 232' and sacrificial layers 10 alternately arranged, and a hard mask layer 9 disposed on a side of the sacrificial layer 10 on the topmost layer remote from the substrate 1, the hard mask layer 9 covering the sacrificial layer 10, as shown in fig. 2A and 2B. Fig. 2A is a top view of a stack structure formed according to some embodiments, and fig. 2B is a cross-sectional view perpendicular to the substrate 1 along the direction AA' in fig. 2A. The AA' direction may be parallel to the first direction X.

In some embodiments, the substrate 1 may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductor material.

In some embodiments, the first semiconductor thin film may be a heavily doped semiconductor thin film layer, and the second semiconductor structure layer 232' may be formed to form a second semiconductor sub-layer 232.

In some embodiments, the sacrificial layer film may be a semiconductor material, such as SiGe or the like. The use of semiconductor materials herein facilitates epitaxial growth of the first semiconductor film. The sacrificial layer film is replaced with an insulating film later.

In some embodiments, the hard mask layer 9 includes, but is not limited to, at least one of: carbon, polysilicon, silicon oxide, and the like.

The stacked structure shown in fig. 2B includes three second semiconductor construction layers 232 'and three sacrificial layers 10, by way of example only, and in other embodiments, the stacked structure may include more or fewer second semiconductor construction layers 232' and sacrificial layers 10 alternately.

2) Forming a first trench T1 and a first insulating layer 11;

etching the plurality of stacked structures to form a plurality of first trenches T1 penetrating the stacked structures; the plurality of first grooves T1 are distributed at intervals along a first direction X and a second direction Y, and a storage unit area is defined between every two adjacent first grooves T1 along the second direction Y, wherein the first grooves T1 are T-shaped grooves; the T-shaped groove comprises a first sub-groove which extends in a first direction X and a second sub-groove which extends from the middle of the first sub-groove along a second direction Y.

Depositing a first insulating film in each first trench T1 and planarizing to form a first insulating layer 11 filling the first trench T1; the first insulating layer 11 may be flush with the hard mask layer 9. As shown in fig. 3A and 3B, where fig. 3A is a top view after forming the first trench T1 and the first insulating layer 11 provided in some embodiments, fig. 3B is a cross-sectional view perpendicular to the substrate 1 along the direction EE' in fig. 3A. The EE' direction may be parallel to the first direction X. The first insulating layer 11 may isolate a plurality of memory cells to be formed later.

In some embodiments, the first insulating film may be a low-K dielectric layer including, but not limited to, silicon oxide, such as silicon dioxide (SiO ₂), or the like.

3) Forming a first preliminary hole K1;

The stacked structure is etched from the top layer to the bottom layer by dry etching (etching is stopped on the substrate 1) to form a first initial hole K1, and at this time, the first initial hole K1 has a uniform pore diameter between the second sub-hole of the second semiconductor structure layer 232 'and the first sub-hole of the sacrificial layer 10, as shown in fig. 4A and fig. 4B, where fig. 4A is a top view after the first initial hole K1 is formed, and fig. 4B is a cross-sectional view perpendicular to the substrate 1 along the direction AA' in fig. 4A provided in some embodiments.

One sidewall of the first preliminary hole K1 exposes the first insulating layer 11 located in the linear sub-groove of the T-shaped groove adjacent to the first preliminary hole K1. The remaining sidewalls of the first preliminary hole K1 do not expose the first insulating layer 11, i.e., the remaining sidewalls expose the second semiconductor construction layer 232', the sacrificial layer 10 and the hard mask layer 9. And along a first direction X, the first initial hole K1 is positioned at one side of the sub-groove extending along a second direction Y of the T-shaped groove.

In some embodiments, the front projection of the first initial hole K1 on the substrate 1 is, for example, square. But is not limited thereto and may be other shapes.

4) Forming a second insulating layer 12;

removing the sacrificial layer 10 by transverse etching based on the first initial hole K1;

A second insulating film is deposited on the substrate 1 with the foregoing structure, and a second insulating layer 12 is formed to fill the first initial hole K1 and the area where the sacrificial layer 10 is located, as shown in fig. 5A and 5B, where fig. 5A is a top view after forming the second insulating layer 12, and fig. 5B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in fig. 5A, provided in some embodiments. The second insulating layer 12 may isolate memory cells of different layers.

In some embodiments, the second insulating layer 12 may be a film layer having an etching selectivity with the first insulating layer 11, such as SiN, etc.

5) Exposing the first preliminary hole K1;

The second insulating layer 12 in the first initial hole K1 is etched and removed along a direction perpendicular to the substrate 1, and the first initial hole K1 is exposed, as shown in fig. 6A and 6B, where fig. 6A is a top view after the first initial hole K1 is exposed, and fig. 6B is a cross-sectional view perpendicular to the substrate 1 along a direction AA' in fig. 6A, provided in some embodiments.

6) Forming a first groove V1;

Based on the first initial hole K1, the second semiconductor structure layer 232 'is laterally etched (i.e., along a direction parallel to the substrate 1), so as to form a lateral first groove V1, such that a front projection of the first hole on the substrate 1 of the sub-hole of the second insulating layer 12 falls into a front projection of the sub-hole on the sacrificial layer 10 on the substrate 1, as shown in fig. 7A and fig. 7B, where fig. 7A is a top view after the first groove V1 is formed, and fig. 7B is a cross-sectional view perpendicular to the substrate 1 along a direction AA' in fig. 7A. The aforementioned first hole includes a first preliminary hole K1 and a first groove V1.

Referring to fig. 7A, the area indicated by the dashed line around the first preliminary hole K1 is the outer boundary of the first recess V1, where one of the two sidewalls spaced apart along the first direction X exposes the second semiconductor structure layer 232', the other exposes the second semiconductor structure layer 232', and the other exposes the first insulating layer 11, and one of the two sidewalls exposes the first insulating layer 11, and the other exposes the second semiconductor structure layer 232', that is, when etching laterally along the second direction Y, part of the second semiconductor structure layer 232' is etched away, and the first insulating layer 11 is not exposed, and when etching laterally along the first direction X, etching to the sub-trench of the T-shaped trench extending along the second direction Y.

7) Forming a first semiconductor structure layer 231';

A second semiconductor thin film is deposited on the substrate 1 with the foregoing structure to form a first semiconductor structure layer 231' filling the first hole, as shown in fig. 8A and 8B, where fig. 8A is a top view after forming the first semiconductor structure layer 231' and fig. 8B is a cross-sectional view perpendicular to the substrate 1 along the AA ' direction in fig. 8A provided in some embodiments.

The first semiconductor structure layer 231' may be a lightly doped or undoped semiconductor material.

In some embodiments, the depositing the second semiconductor film may be epitaxially growing the second semiconductor film.

In an exemplary embodiment of the present disclosure, the material of the second semiconductor thin film may be silicon or polysilicon having a band gap of less than 1.65eV, or may be a wide band gap material such as a metal oxide material having a band gap of greater than 1.65 eV.

For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and the like. Of course, compounds containing other elements, such as N, si, are not excluded from the metal oxide; nor does it exclude other minor doping elements.

In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: materials such as indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (inallzno), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be specifically adjusted as long as the leakage current of the transistor can be ensured.

The band gap of these materials is wider and has lower leakage current, for example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 ^-15 a, whereby the operation performance of the dynamic memory can be improved.

The material of the above-mentioned metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

8) Forming a first semiconductor sub-layer 231;

Etching to remove the first semiconductor structure layer 231 'except the region of the first recess V1 in the first hole, i.e., to retain only the first semiconductor structure layer 231' located in the first recess V1; so that the first semiconductor construction layer 231' is divided into a plurality of portions respectively located at different layers;

And laterally etching the first semiconductor structure layer 231' based on the first initial hole to form a second groove V2, and reserving a part of the first semiconductor structure layer 231', wherein the reserved first semiconductor structure layer 231' is the first semiconductor sub-layer 231 of the plurality of transistors. As shown in fig. 9A and 9B, fig. 9A is a top view after forming the first semiconductor sublayer 231 according to some embodiments, and fig. 9B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in fig. 9A. Referring to fig. 9A, at this time, the first semiconductor sublayer 231 includes two independent portions, which are separated by the first insulating layer 11 in the first trench T1. When the second semiconductor layer 23b is formed later, the first semiconductor sublayer 231 and the second semiconductor layer 23b can be prevented from being connected.

The area shown by the broken line with reference to fig. 9A is the outer boundary of the second groove V2.

9) Forming a first conductive layer 26a' and a first gate insulating layer 24a;

Sequentially depositing a first gate insulating film and a first gate electrode film on the substrate 1 having the aforementioned structure, forming a first gate insulating layer 24a and a first conductive layer 26a'; the first conductive layer 26a ' fills the first preliminary hole K1 and the second recess V2, as shown in fig. 10A and 10B, wherein fig. 10A is a top view of some embodiments after forming the first conductive layer 26a ' and the first gate insulating layer 24a, and fig. 10B is a cross-sectional view perpendicular to the substrate 1 along the direction AA ' in fig. 10A.

The first gate insulating layer 24a covers bottom walls and sidewalls of the first preliminary hole K1 and the second groove V2.

In some embodiments, the material of the first gate insulating layer 24a may comprise one or more layers of High-K dielectric material. In some embodiments, oxides of one or more of hafnium, aluminum, lanthanum, zirconium, and the like may be included. Exemplary, for example, may include, but is not limited to, at least one of: hafnium oxide (HfO ₂), aluminum oxide (Al ₂O₃), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO ₂), and the like. The materials of the second gate insulating layer 24b, the third gate insulating layer 24c and the fourth gate insulating layer 24d are similar, and will not be described again.

In some embodiments, the first gate electrode film may be one or more of the following different types of materials:

For example, metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; may be a metal alloy containing the aforementioned metals;

or can be metal oxide, metal nitride, metal silicide, metal carbide, etc., such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (Aluminum doped Zinc Oxide, AZO), etc. metal oxide materials with higher conductivity; for example, a metal nitride material such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or the like;

or may be a polysilicon material, a conductively-doped semiconductor material, etc., such as conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium, etc.; other materials that exhibit electrical conductivity, and the like.

The materials of the second gate electrode film, the third gate electrode film, the fourth gate electrode film, the first conductive film, the second conductive film and the third conductive film are similar, and the detailed description is omitted.

10 A) forming a first gate electrode 26a;

Etching to remove the first conductive layer 26a ' in the first initial hole K1, and reserving the first conductive layers 26a ' in the plurality of second grooves V2, wherein the first conductive layer 26a ' in each second groove V2 is the first gate electrode 26a of one first transistor; the first gate electrode 26a of the first transistor at the same position of the different layers is turned off. The first gate electrode 26a is also multiplexed to the third electrode 53 of the second transistor, and the storage node SN comprises the first gate electrode 26a.

A third insulating film is deposited to form an isolation layer 13, and the isolation layer 13 fills the first initial hole K1, as shown in fig. 11A and 11B, where fig. 11A is a top view after forming the first gate electrode 26a provided in some embodiments, and fig. 11B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in fig. 11A.

In some embodiments, the isolation layer 13 may be a low-K dielectric layer including, but not limited to, silicon oxide, such as silicon dioxide (SiO ₂), or the like.

11 A second preliminary hole K2 and a third groove V3 are formed;

The stacked structure is etched from the top layer to the bottom layer by dry etching (etching is stopped on the substrate 1), a second initial hole K2 is formed, the second initial hole K2 is close to a first groove T1 far away from the first initial hole K1 in two adjacent first grooves T1 along a second direction Y, the side wall of the second initial hole K2 does not expose the first insulating layer 11, and the second initial hole K2 and the first initial hole K1 are positioned on the same side of a sub-groove extending along the second direction Y of the first groove T1.

The third recess V3 is formed by laterally etching the second semiconductor structure layer 232' based on the second initial hole K2, as shown in fig. 12A, 12B and 12C, wherein fig. 12A is a top view after forming the second initial hole K2 and the third recess V3, and fig. 12B is a cross-sectional view perpendicular to the substrate 1 along the BB ' direction in fig. 12A, and fig. 12C is a cross-sectional view perpendicular to the substrate 1 along the CC ' direction in fig. 12A, provided in some embodiments. Two sidewalls of the third groove V3 are spaced apart along the second direction Y, wherein one sidewall exposes the first insulating layer 11 located in the in-line sub-groove, and the other sidewall exposes the first semiconductor layer 231; the second semiconductor structure layer 232' is exposed by two sidewalls spaced apart along the first direction X. The lateral etching is performed to expose the first semiconductor layer 231 so that the first word line 40a formed later can control the first transistor. The aforementioned second hole includes the second preliminary hole K2 and the third groove V3.

In some embodiments, the orthographic projection of the second initial hole K2 on the substrate 1 is, for example, square. But is not limited thereto and may be other shapes.

12 A) forming a second gate insulating layer 24b and a first word line 40a;

Sequentially depositing a second gate insulating film and a second gate electrode film on the substrate 1 having the aforementioned structure, forming a second gate insulating layer 24b and a first word line 40a; the second gate insulating layer 24B covers bottom walls and sidewalls of the second preliminary hole K2 and the third recess V3, and the first word line 40a fills the second preliminary hole K2 and the third recess V3, as shown in fig. 13A, 13B, and 13C, wherein fig. 13A is a top view after forming the second gate insulating layer 24B and the first word line 40a, and fig. 13B is a cross-sectional view perpendicular to the substrate 1 along the BB 'direction in fig. 13A, and fig. 13C is a cross-sectional view perpendicular to the substrate 1 along the CC' direction in fig. 13A, which are provided in some embodiments. The second gate electrode 26b of the first transistor at the same location in a different layer is part of the first word line 40 a.

13 Forming a third hole K3;

The stacked structure is etched from the top layer to the bottom layer (etching is stopped on the substrate 1) by dry etching, a third hole K3 is formed, the third hole K3 is disposed between the second preliminary hole K2 and the sub-trench of the first trench T1 extending in the second direction Y, and is disposed between the first preliminary hole K1 and the linear sub-trench of the first trench T1, a sidewall of the third hole K3 extending in the first direction X and away from the first preliminary hole K1 may expose the first insulating layer 11 located in the linear sub-trench of the first trench T1, the remaining sidewalls may expose the second semiconductor structure layer 232', and the second gate insulating layer 24b is not exposed, the first semiconductor sub-layer 231, and the first insulating layer 11 located in the linear sub-trench of the first trench T1 extending in the second direction. As shown in fig. 14A and 14B, fig. 14A is a top view after forming the third hole K3 according to some embodiments, and fig. 14B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in fig. 14A.

In some embodiments, the orthographic projection of the third hole K3 on the substrate 1 is, for example, square. But is not limited thereto and may be other shapes.

14 Forming a signal line 52';

Performing metal silicide on the second semiconductor structure layer 232' exposed from the side wall of the third hole K3 to form metal silicide;

A first conductive film is deposited to form a signal line 52 'filling the third hole K3, and the second electrode 52 of the first transistor at a different layer relative position is a part of the signal line 52'. As shown in fig. 15A and 15B, fig. 15A is a top view after forming the signal line 52 'provided in some embodiments, and fig. 15B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in fig. 15A. The second semiconductor structure layer 232 'surrounding the signal line 52' is the second portion 2322 of the second semiconductor sublayer 232, and the first portion 2321 and the second portion 2322 are spaced apart.

15 Forming a second trench T2;

The stacked structure is etched from the top layer to the bottom layer, so as to form a second trench T2 penetrating the stacked structure, the second trench T2 extends along a second direction Y, a group of memory cells is defined between the second trenches T2 adjacent along the first direction X, each group of memory cells includes two columns of memory cells, as shown in fig. 16A and 16B, where fig. 16A is a top view after the second trench T2 is formed, and fig. 16B is a cross-sectional view perpendicular to the substrate 1 along a BB' direction in fig. 16A provided in some embodiments.

16 A fourth groove V4 and a first bit line layer 31';

The second semiconductor structure layer 232' is laterally etched based on the second trench T2, and the second semiconductor structure layer 232' is not completely etched (the second gate insulating layer 24b is not exposed), so as to form a fourth groove V4, wherein the fourth groove V4 extends along the second direction Y, and at this time, the second semiconductor structure layer 232' located on the side of the first semiconductor sub-layer 231 facing the second groove V2 serves as the first portion 2321 of the second semiconductor sub-layer 232.

Performing metal silicide treatment on the second semiconductor sub-layer 232 to form metal silicide so as to reduce the contact resistance between the second semiconductor sub-layer 232 and the first bit line layer 31' to be formed;

depositing a second conductive film to form a first bit line layer 31', wherein the first bit line layer 31' fills the second groove T2 and the fourth groove V4; as shown in fig. 17A and 17B, where fig. 17A is a top view after forming the first bit line layer 31 'provided in some embodiments, fig. 17B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in fig. 17A.

17 A) forming a first bit line 31 and a fourth insulating layer 14;

etching to remove the first bit line layer 31' in the second trench T2, and reserving the first bit line layer 31' in the fourth trench V4, wherein the first bit line layer 31' is divided into a plurality of first bit lines 31 in different layers, and the plurality of first bit lines 31 are disconnected;

a fourth insulating film is deposited to form a fourth insulating layer 14 filling the second trench T2, and the fourth insulating layer 14 spaces between different groups of memory cells, as shown in fig. 18A and 18B, where fig. 18A is a top view after forming the first bit line 31 and the fourth insulating layer 14, and fig. 18B is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in fig. 18A, provided in some embodiments.

In some embodiments, the fourth insulating layer 14 may be a low-K dielectric layer including, but not limited to, silicon oxide, such as silicon dioxide (SiO ₂), or the like.

18 A fourth preliminary hole K4 and a third trench T3 are formed;

The stacked structure is etched from the top layer to the bottom layer by dry etching (etching is stopped on the substrate 1), and a fourth initial hole K4 and a third trench T3 are formed, as shown in fig. 19A, 19B and 19C, where fig. 19A is a top view after forming the fourth initial hole K4 and the third trench T3 provided in some embodiments, fig. 19B is a cross-sectional view perpendicular to the substrate 1 along the AA 'direction in fig. 19A, and fig. 19C is a cross-sectional view perpendicular to the substrate 1 along the DD' direction in fig. 19A.

The third trenches T3 extend along the second direction Y, and the third trenches T3 are spaced apart from two columns of memory cells in the same group. The fourth initial hole K4 is located at one side of the first initial hole K1 facing the sub-groove of the first groove T1 extending along the second direction Y, the fourth initial hole K4 and the first initial hole K1 are close to the same linear groove of the first groove T1, and one side wall of the fourth initial hole K4 exposes the first insulating layer 11 in the adjacent linear sub-groove of the first groove T1.

In some embodiments, the orthographic projection of the fourth initial hole K4 on the substrate 1 is, for example, square. But is not limited thereto and may be other shapes.

19 A fifth groove V5 is formed;

Forming a fifth groove V5 by laterally etching the second semiconductor structure layer 232' and the first semiconductor sub-layer 231 and the first gate insulating layer 24a based on the fourth initial hole K4 and the third trench T3, wherein the sidewall of the fifth groove V5 exposes the first gate electrode 26a, so that the first gate electrode 26a is connected with the second semiconductor layer 23b formed subsequently, and after the lateral etching, the fourth initial hole K4 is communicated with the third trench T3, and the sidewall of the fifth groove V5 exposes the sidewall of the first insulating layer 11 in the first sub-trench toward the third trench T3; as shown in fig. 20A, 20B, and 20C, fig. 20A is a top view after forming the fifth groove V5, fig. 20B is a cross-sectional view perpendicular to the substrate 1 along the AA 'direction in fig. 20A, and fig. 20C is a cross-sectional view perpendicular to the substrate 1 along the DD' direction in fig. 20A, which are provided in some embodiments.

20 A) forming a third semiconductor construction layer 23b';

Sequentially depositing a third semiconductor thin film and a fifth insulating thin film on the substrate 1 having the aforementioned structure, forming a third semiconductor construction layer 23b' and a fifth insulating layer 15; the third semiconductor construction layer 23b' covers the sidewalls and bottom wall of the fourth preliminary hole K4 and the third trench T3, and covers the inner walls (sidewalls and bottom wall) of the fifth trench V5, and the fifth insulating layer 15 fills the fourth preliminary hole K4, the third trench T3, and the fifth trench V5; as shown in fig. 21A, 21B, and 21C, fig. 21A is a top view of the third semiconductor structure layer 23B ' formed according to some embodiments, fig. 21B is a cross-sectional view perpendicular to the substrate 1 along the AA ' direction in fig. 21A, and fig. 21C is a cross-sectional view perpendicular to the substrate 1 along the DD ' direction in fig. 21A.

In some embodiments, the fifth insulating film may be a low-K dielectric layer including, but not limited to, silicon oxide, such as silicon dioxide (SiO ₂), or the like.

21 A second semiconductor layer 23b is formed;

Etching to remove the third semiconductor structure layer 23b ' and the fifth insulating layer 15 in the fourth initial hole K4 and the third trench T3, and reserving the third semiconductor structure layer 23b ' and the fifth insulating layer 15 in the fifth groove V5, so that the third semiconductor structure layer 23b ' is divided into a plurality of parts respectively located in different layers, each part is the second semiconductor layer 23b of one second transistor, and thus the second semiconductor layers 23b of the second transistors in the same positions of the different layers are disconnected;

A sixth insulating film is deposited to form a sixth insulating layer 16, and the sixth insulating layer 16 fills the fourth preliminary hole K4 and the third trench T3, as shown in fig. 22A, 22B, and 22C, where fig. 22A is a top view after forming the second semiconductor layer 23B provided in some embodiments, fig. 22B is a cross-sectional view perpendicular to the substrate 1 along the AA 'direction in fig. 22A, and fig. 22C is a cross-sectional view perpendicular to the substrate 1 along the DD' direction in fig. 22A.

In some embodiments, the sixth insulating film may be a film layer having an etching selectivity to the fifth insulating layer, including, but not limited to, siN, etc.

22A sixth groove V6 is formed;

Etching to remove the sixth insulating layer 16 in the third trench T3;

forming a sixth groove V6 by laterally etching the fifth insulating layer 15 based on the third trench T3; the sixth recess V6 exposes the sixth insulating layer 16 located in the fourth preliminary hole K4; as shown in fig. 23A and 23B, fig. 23A is a top view after forming the sixth groove V6, and fig. 23B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in fig. 23A, provided in some embodiments.

The sixth groove V6 may be a part of the fifth groove V5, and a part of the fifth groove V5 other than the sixth groove V6 is referred to as a seventh groove V7.

23 Forming a second bit line layer 32';

Depositing a third conductive film to form a second bit line layer 32', wherein the second bit line layer 32' fills the third trench T3 and the sixth groove V4; as shown in fig. 24A and 24B, fig. 24A is a top view after forming the second bit line layer 32 'according to some embodiments, and fig. 24B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in fig. 24A.

24 Forming a second bit line 32;

etching to remove the second bit line layer 32' in the third trench T3, and reserving the second bit line layer 32' in the sixth trench V6, wherein the second bit line layer 32' is divided into a plurality of second bit lines 32 in different layers, and the plurality of second bit lines 32 are disconnected;

A seventh insulating film is deposited to form a seventh insulating layer 17 filling the third trench T3, and the seventh insulating layer 17 spaces two rows of memory cells in the same group, as shown in fig. 25A and 25B, where fig. 25A is a top view after forming the second bit line 32, and fig. 25B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in fig. 25A according to some embodiments.

In some implementations, the seventh insulating film may be a low-K dielectric layer including, but not limited to, silicon oxide, such as silicon dioxide (SiO ₂), and the like.

25 A second word line 40b and a third gate insulating layer 24 c);

etching to remove the sixth insulating layer 16 in the fourth initial hole K4, and removing the fifth insulating layer 15 in the seventh groove V7 based on the fourth initial hole K4 by lateral etching;

Sequentially depositing a third gate insulating film and a third gate electrode film on the substrate 1 having the aforementioned structure, forming a third gate insulating layer 24c and a second word line 40b; the third gate insulating layer 24C covers the bottom wall and the side wall of the fourth preliminary hole K4, and the bottom wall and the side wall of the seventh recess V7, and the third gate electrode film fills the fourth preliminary hole K4 and the seventh recess V7, as shown in fig. 26A, 26B, and 26C, wherein fig. 26A is a top view after forming the second word line 40B and the third gate insulating layer 24C provided in some embodiments, fig. 26B is a cross-sectional view perpendicular to the substrate 1 along the AA 'direction in fig. 26A, and fig. 26C is a cross-sectional view perpendicular to the substrate 1 along the DD' direction in fig. 26A. The aforementioned fourth hole may include a fourth preliminary hole K4 and a seventh groove V7.

26 Forming a fifth preliminary hole K5;

etching the stacked structure from the top layer to the bottom layer (etching is stopped on the substrate 1) by dry etching to form a fifth initial hole K5; the fifth initial hole K5 and the third hole K3 are respectively arranged at two sides of the second sub-groove of the first groove T1 extending along the second direction Y; sidewalls of the fifth preliminary holes K5 expose the second semiconductor structure layer 232' and the second semiconductor layer 23b; and the fifth initial hole K5 is adjacent to a trench far from the fourth initial hole K4, such as two adjacent first trenches T1 and a fourth initial hole K4 in the second direction Y, among the two first trenches T1 defining the memory cell in which the fifth initial hole K5 is located, the fourth initial hole K4 is adjacent to one of the first trenches, and the fifth initial hole K5 is adjacent to the other first trench.

Forming a region V8 by laterally etching the second semiconductor construction layer 232 'and the second insulating layer 12 based on the fifth preliminary hole K5, the bottom wall of the region V8 exposing the first insulating layer 11 and the seventh insulating layer 17, i.e., laterally etching the second semiconductor construction layer 232' in the first direction X and the second direction Y exposing the first insulating layer 11; the second insulating layer 12 is etched laterally along the first direction X, exposing the first insulating layer 11 and the seventh insulating layer 17, and the second insulating layer 12 is etched laterally along the second direction Y, exposing the first insulating layer 11 and the third gate insulating layer 24C, as shown in fig. 27A, 27B and 27C, wherein fig. 27A is a top view after forming a fifth preliminary hole K5 provided in some embodiments, fig. 27B is a cross-sectional view perpendicular to the substrate 1 along the direction BB 'in fig. 27A, and fig. 27C is a cross-sectional view perpendicular to the substrate 1 along the direction DD' in fig. 27A. The aforementioned fifth holes include a fifth initial hole K5 and a region V8.

In some embodiments, the front projection of the fifth initial hole K5 on the substrate 1 is, for example, square. But is not limited thereto and may be other shapes.

27 A third word line 40c and a fourth gate insulating layer 24 d);

Sequentially depositing a fourth gate insulating film and a fourth gate electrode film on the substrate 1 having the aforementioned structure, forming a fourth gate insulating layer 24d and a third word line 40c; the fourth gate insulating layer 24D covers the bottom wall and the side wall of the fifth preliminary hole K5, and the bottom wall and the side wall of the region V8, and the fourth gate electrode thin film fills the fifth preliminary hole K5 and the region V8 as shown in fig. 1A, 1B, 1C, 1D, 1E, and 1F.

The embodiment of the disclosure also provides an electronic device, which comprises the semiconductor device of any one of the embodiments or the semiconductor device formed by the method for manufacturing the semiconductor device of any one of the embodiments. The electronic device may be: storage, smart phones, computers, tablet computers, artificial intelligence devices, wearable devices or mobile power sources, etc. The storage device may include, without limitation, memory in a computer, and the like.

Although the embodiments of the present invention are described above, the embodiments are only used for facilitating understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is to be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that it comprises: a plurality of memory cells stacked in a direction perpendicular to a substrate, a first word line extending in a direction perpendicular to the substrate and penetrating the plurality of memory cells at the same position in the plurality of layers, a second word line extending in a direction perpendicular to the substrate and penetrating the plurality of memory cells at the same position in the plurality of layers, and a third word line extending in a direction perpendicular to the substrate and penetrating the plurality of memory cells at the same position in the plurality of layers;

The memory cell comprises: a first transistor and a second transistor, wherein the first transistor and the second transistor are distributed along a first direction parallel to the substrate; the second word line and the third word line are distributed along a second direction parallel to the substrate, wherein the first direction intersects the second direction;

The first transistor comprises: a first gate electrode, a second gate electrode and a first semiconductor layer; the first gate electrodes of the memory cells at the same position in different layers extend in a direction perpendicular to the substrate and are spaced apart; the first semiconductor layer partially surrounds the first gate electrode; the second gate electrode is arranged at a side of the first semiconductor layer away from the first gate electrode, and the second gate electrodes of the first transistors at the same position in different layers are part of the first word line;

The second transistor includes: a second semiconductor layer; a partial area of the first gate electrode not surrounded by the first semiconductor layer is connected to the second semiconductor layer; the second semiconductor layer partially surrounds the second word line; the third word line is formed with a plurality of first grooves opening toward the second word line and distributed in a direction perpendicular to the substrate, the second semiconductor layer is distributed on the bottom wall and side walls of the first groove, and the second word line is formed with a plurality of protrusions facing the plurality of first grooves respectively.

2. The semiconductor device according to claim 1 is characterized in that the first semiconductor layer includes a first semiconductor sublayer and a second semiconductor sublayer arranged on a side of the first semiconductor sublayer away from the first gate electrode, the first semiconductor sublayer partially surrounds the first gate electrode, the doping concentration of the second semiconductor sublayer is greater than the doping concentration of the first semiconductor sublayer, and the second semiconductor sublayer includes a first part and a second part spaced apart on a surface of the first semiconductor sublayer away from the first gate electrode.

3 . The semiconductor device according to claim 2 , wherein the first word line is distributed in a region between the first portion and the second portion on a side wall of the first semiconductor sublayer facing away from the first gate electrode.

4. The semiconductor device according to claim 2 is characterized in that the first transistor also includes a first electrode and a second electrode, the first electrode is connected to the first part, the second electrode is connected to the second part, the second part surrounds the second electrode, and the second electrodes of the first transistors at the same position in different layers are connected to form an integrated structure extending in a direction perpendicular to the substrate.

5. The semiconductor device according to claim 4 is characterized in that the first parts of the first transistors in the same column and in the same layer distributed along the second direction are interconnected to form an integrated structure, and the second parts of the first transistors in the same column and in the same layer distributed along the second direction are separated from each other.

6 . The semiconductor device according to claim 5 , wherein the first electrodes of the first transistors in the same column distributed along the second direction are connected to form a first bit line extending along the second direction.

7 . The semiconductor device according to claim 4 , wherein the second electrode and the first word line are arranged on the same side of the first portion and on the same side of the first gate electrode.

8. The semiconductor device according to claim 2 is characterized in that the semiconductor device also includes an isolation layer that penetrates multiple layers of the first transistor; the first gate electrode parts at the same position in different layers surround the isolation layer and are sequentially distributed in different areas of the side wall of the isolation layer along a direction perpendicular to the substrate.

9. The semiconductor device according to claim 8 is characterized in that the first transistor also includes a first gate insulating layer arranged between the first gate electrode and the first semiconductor sublayer, and the first gate insulating layers of the first transistors at the same position in different layers are connected to form an integrated structure extending in a direction perpendicular to the substrate.

10. The semiconductor device according to claim 9, characterized in that the semiconductor device further comprises:

Insulating layers and conductive layers are alternately distributed from top to bottom in a direction perpendicular to the substrate;

The first semiconductor sublayer, the first gate insulating layer, the first gate electrode, and the isolation layer are sequentially distributed in the first hole from outside to inside, and the isolation layer fills the first hole;

The second hole is sequentially provided with a second gate insulating layer and the first word line from outside to inside, and the first word line fills the second hole;

Only a signal line is distributed in the third hole, and the signal line fills the third hole, and the second electrode of the first transistor at the same position in different layers is a part of the signal line.

11. The semiconductor device according to claim 10 is characterized in that, in the orthographic projection of the sub-hole of the first hole in the insulating layer on the substrate, the boundary close to the first word line, the boundary close to the second word line, and the boundary away from the second word line fall within the orthographic projection of the sub-hole of the first hole in the conductive layer on the substrate, and the boundary away from the first word line falls on the boundary of the orthographic projection of the sub-hole of the first hole in the conductive layer on the substrate.

12. The semiconductor device according to claim 10 is characterized in that the semiconductor device further comprises: a fourth hole penetrating the insulating layer and the conductive layer, and the second semiconductor layer, the third gate insulating layer, and the second word line are sequentially distributed in the fourth hole from the outside to the inside, the second word line fills the fourth hole, the sidewall of the fourth hole exposes the first gate electrode, and the boundary of the sub-hole of the fourth hole in the insulating layer close to the first gate electrode and the boundary close to the third word line fall within the orthographic projection of the sub-hole of the fourth hole in the conductive layer on the substrate, and the boundary away from the first gate electrode and the boundary away from the third word line fall on the boundary of the orthographic projection of the sub-hole of the fourth hole in the conductive layer on the substrate.

13. The semiconductor device according to claim 12 is characterized in that the semiconductor device also includes a second groove arranged on the side of the second word line away from the first gate electrode and extending along the second direction, the second groove is connected to the fourth hole, the opening of the second groove is away from the second word line and the third word line, and the second semiconductor layer is also distributed on the side wall and bottom wall of the second groove.

14 . The semiconductor device according to claim 13 , wherein the second semiconductor layers of the second transistors in the same column distributed along the second direction are disconnected.

15 . The semiconductor device according to claim 13 , further comprising: a second bit line distributed in the second groove in which the second semiconductor layer is disposed and filling the second groove.

16. The semiconductor device according to claim 15 is characterized in that the semiconductor device further comprises: a fifth hole penetrating the insulating layer and the conductive layer, and the fourth gate insulating layer and the third word line are sequentially distributed on the fifth hole from the outside to the inside, and the third word line fills the fifth hole; and in the orthographic projection of the sub-hole of the fifth hole in the conductive layer on the substrate, the boundary close to the second bit line and the boundary close to the second word line fall within the orthographic projection of the sub-hole of the fifth hole in the insulating layer on the substrate, and the boundary away from the second bit line and the boundary away from the second word line fall on the boundary of the orthographic projection of the sub-hole of the fifth hole in the insulating layer on the substrate.

17. A method for manufacturing a semiconductor device, comprising:

Providing a substrate, forming a stack structure including alternating functional layers and sacrificial layers on the substrate, the stack structure including a plurality of memory cell regions, the memory cell region including a first transistor region and a second transistor region distributed along a first direction parallel to the substrate;

A first gate electrode and a first semiconductor layer are formed in the first transistor region and are arranged in the functional layer. A first word line is formed that runs through each layer in a direction perpendicular to the substrate. The first semiconductor layer partially surrounds the first gate electrode. The first word line is arranged on a side of the first semiconductor layer away from the first gate electrode. The first gate electrodes of the memory cells at the same position in different layers are stacked and spaced apart in a direction perpendicular to the substrate. The second gate electrodes of the first transistors at the same position in different layers are part of the first word line.

A second word line, a third word line and a second semiconductor layer are formed in the second transistor area; the first gate electrode is connected to the second semiconductor layer; the second semiconductor layer partially surrounds the second word line; the third word line is formed with a plurality of first grooves opening toward the second word line and spaced apart in a direction perpendicular to the substrate, the second semiconductor layer is distributed on the bottom wall and side wall of the first groove, and the second word line is formed with a plurality of protrusions facing the plurality of first grooves respectively.

18. The method for manufacturing a semiconductor device according to claim 17, wherein forming a stacked structure including alternating functional layers and sacrificial layers on the substrate comprises:

Depositing a semiconductor thin film and a sacrificial layer thin film on the substrate in sequence to form a stacked structure including semiconductor structure layers and sacrificial layers arranged alternately;

The stacked structure is patterned to form a T-shaped first trench penetrating each layer, wherein the first trench includes a first sub-trench extending along a first direction and a second sub-trench extending from a non-end portion of the first sub-trench along a second direction parallel to the substrate; the memory cell region is included between adjacent first sub-trenches spaced apart along the second direction, and the first transistor region and the second transistor region are respectively arranged on both sides of the second sub-trench; and the first direction intersects with the second direction;

A first hole is formed at a first sub-trench near a first trench in the first transistor region and penetrates the stack structure in a direction perpendicular to the substrate, wherein the sidewall of the first hole exposes the first sub-trench, and the sacrificial layer is removed by etching through the first hole and replaced with an insulating layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein forming a first gate electrode and a first semiconductor layer disposed on the functional layer in the first transistor region, and forming a first word line penetrating through each layer in a direction perpendicular to the substrate comprises:

Based on the first hole, the semiconductor structure layer is etched along a direction parallel to the substrate; a plurality of first semiconductor sublayers, a first gate insulating layer, a plurality of gate electrodes and an isolation layer are formed in the first hole; the plurality of first gate electrodes are spaced apart in a direction perpendicular to the substrate, the plurality of first semiconductor sublayers partially surround the first gate electrode and are spaced apart in a direction perpendicular to the substrate, the first gate insulating layer is arranged between the first semiconductor sublayer and the first gate electrode, the first gate electrode partially surrounds the isolation layer, and the isolation layer fills the first hole;

A second hole is formed at a first sub-groove near another first groove in the first transistor region, penetrating the stacked structure in a direction perpendicular to the substrate; based on the second hole, the semiconductor structure layer is etched in a direction parallel to the substrate to expose the first semiconductor sub-layer; a second gate insulating layer and a first word line filling the second hole are sequentially formed in the second hole; the first hole and the second hole separate the semiconductor structure layer in the first transistor region into a second semiconductor sub-layer including an independent first part and a second part;

The method further comprises:

A third hole is formed between the second hole and the second sub-groove in the first transistor region and penetrates the stack structure in a direction perpendicular to the substrate, the sidewall of the third hole exposes the second portion of the second semiconductor sublayer, and a signal line is formed in the third hole, filling the third hole and contacting the second portion of the second semiconductor sublayer.

20. The method for manufacturing a semiconductor device according to claim 19, wherein forming the second word line, the third word line and the second semiconductor layer in the second transistor region comprises:

A fourth hole is formed in the second transistor region and penetrates the stacked structure in a direction perpendicular to the substrate; based on the fourth hole, the semiconductor structure layer, the first semiconductor sublayer, and the first gate insulating layer are etched in a direction parallel to the substrate to expose the first gate electrode to form a transverse groove; a second semiconductor layer, a third gate insulating layer, and a second word line filling the fourth hole are sequentially formed in the fourth hole, and the second semiconductor layer is formed on the bottom wall and side wall of the transverse groove;

A fifth hole is formed in the second transistor region and penetrates the stacked structure in a direction perpendicular to the substrate, the fifth hole and the fourth hole are distributed in the second direction, the semiconductor structure layer and the insulating layer are etched in a direction parallel to the substrate based on the fifth hole to expose the third gate insulating layer and the second semiconductor layer, and a fourth gate insulating layer and a third word line filling the fifth hole are sequentially formed in the fifth hole.

21. The method for manufacturing a semiconductor device according to claim 19, further comprising:

A second trench penetrating each layer is formed between first transistor regions adjacent to each other along a first direction, and the second trench extends along a second direction; the semiconductor structure layer is laterally etched in the second trench without exposing the first semiconductor sublayer to form a first transverse trench, and a first bit line filling the first transverse trench is formed in the first transverse trench.

22. The method for manufacturing a semiconductor device according to claim 20, further comprising:

Forming a third trench extending along the second direction and penetrating through each layer between the second transistor regions adjacent to each other along the first direction; laterally etching the semiconductor structure layer in the third trench to form a second transverse trench, wherein the second transverse trench is connected to the fourth hole;

When the second semiconductor layer is formed in the fourth hole, the second semiconductor layer is also formed on the inner wall of the second transverse trench; and a second bit line filling the second transverse trench is formed in the second transverse trench having the second semiconductor layer formed therein.

23. An electronic device, characterized in that it comprises the semiconductor device according to any one of claims 1 to 16, or a semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 17 to 22.