CN118201209A - Printed circuit board on printed circuit board assembly - Google Patents

Abstract

The present application relates to printed circuit boards on printed circuit board assemblies. An electronic system assembly comprising: a first circuit substrate having a surface, wherein the surface has a two-dimensional area defined in a first dimension and a second dimension; a plurality of first semiconductor chip packages mounted on and electrically coupled to the surface; a plurality of second circuit substrates positioned over the surface, wherein each first semiconductor chip package is arranged between the surface and a respective second circuit substrate in a third dimension; a plurality of conductive interconnect structures extending in the third dimension, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups, and wherein each interconnect group connects a different second circuit substrate to the first circuit substrate; and a plurality of second semiconductor chip packages, wherein each second semiconductor chip package is mounted and electrically coupled to a respective second circuit substrate.

Description

Printed circuit board on printed circuit board assembly

Cross reference to related applications

This patent application claims priority to U.S. provisional patent application No. 63/387,422, filed on 12 months 14 of 2022, and entitled "printed circuit board (PRINTED CIRCUIT BOARD OVER PRINTED CIRCUIT BOARD ASSEMBLY) on a printed circuit board assembly. The disclosure of the prior application is considered part of the present patent application and is incorporated by reference into the present patent application.

Technical Field

The present disclosure relates generally to semiconductor devices and methods of forming semiconductor devices. For example, the present disclosure relates to a Printed Circuit Board (PCB) on a PCB assembly.

Background

A semiconductor package includes a semiconductor substrate, one or more semiconductor electronic components coupled to and/or embedded in the semiconductor substrate, and a housing formed over the semiconductor substrate to encapsulate the one or more semiconductor electronic components. One or more semiconductor electronic components are interconnected by electrical interconnects to form one or more semiconductor devices, such as one or more Integrated Circuits (ICs) (e.g., one or more dies or chips). For example, semiconductor electronic components and electrical interconnects may be fabricated on a semiconductor wafer prior to dicing into dies or chips to form one or more ICs and then packaged. The semiconductor package may be referred to as a semiconductor chip package including one or more ICs. Semiconductor packages protect semiconductor electronic components and electrical interconnects from damage and include means for connecting the semiconductor electronic components and electrical interconnects to external components (e.g., circuit substrates), such as via balls, pins, leads, contact pads, or other electrical interconnect structures. The semiconductor device assembly may be or include a semiconductor package or one or more components of a semiconductor package (e.g., one or more semiconductor devices with or without a housing).

An electronic system assembly may include a plurality of semiconductor packages electrically coupled to a carrier substrate (e.g., a circuit substrate). The electronic system assembly may include additional system components electrically coupled to the carrier substrate. The carrier substrate may include electrical interconnects and conductive paths for interconnecting system components, including multiple semiconductor packages and other system components of the electronic system assembly. Thus, the plurality of semiconductor packages may be electrically connected to each other and/or to one or more additional system components via the carrier substrate to form an electronic system assembly. For example, other system components may include passive components such as storage capacitors, processing units such as Central Processing Units (CPUs), graphics Processing Units (GPUs), microprocessors and/or microcontrollers, control units such as microcontrollers, memory controllers, and/or power management controllers, or one or more other electronic components.

Disclosure of Invention

Embodiments of the present disclosure provide an electronic system assembly, comprising: a first circuit substrate having a first surface, wherein the first surface has a two-dimensional area defined in a first dimension and a second dimension; a plurality of first semiconductor chip packages mounted on and electrically coupled to the first surface; a plurality of second circuit substrates positioned over the first surface, wherein each first semiconductor chip package of the plurality of first semiconductor chip packages is arranged in a third dimension between the first surface and a respective second circuit substrate of the plurality of second circuit substrates; a plurality of conductive interconnect structures extending in the third dimension, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups, and wherein each interconnect group of the plurality of interconnect groups connects a different one of the plurality of second circuit substrates to the first circuit substrate; and a plurality of second semiconductor chip packages, wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to a respective second circuit substrate of the plurality of second circuit substrates.

Another embodiment of the present disclosure provides an electronic system assembly, comprising: a first circuit substrate having a first surface, wherein the first surface has a two-dimensional area defined in a first dimension and a second dimension; a plurality of semiconductor chip packages mounted on and electrically coupled to the first surface; a plurality of second circuit substrates disposed over the first surface, wherein each semiconductor chip package of the plurality of semiconductor chip packages is disposed between the first surface and a respective second circuit substrate of the plurality of second circuit substrates in a third dimension; a plurality of conductive interconnect structures extending in the third dimension, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups, and wherein each interconnect group of the plurality of interconnect groups connects a different one of the plurality of second circuit substrates to the first circuit substrate; and a plurality of storage capacitors, wherein each storage capacitor of the plurality of storage capacitors is mounted and electrically coupled to a respective second circuit substrate of the plurality of second circuit substrates.

Yet another embodiment of the present disclosure provides a method of manufacturing an electronic system assembly, the method comprising: mounting a plurality of first semiconductor chip packages onto a surface of a first circuit substrate to be in electrical contact with the first circuit substrate, wherein the surface of the first circuit substrate has a two-dimensional area defined in a first dimension and a second dimension; mounting a plurality of second semiconductor chip packages to a plurality of second circuit substrates, wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to a respective second circuit substrate of the plurality of second circuit substrates; coupling a plurality of conductive interconnect structures to the plurality of second circuit substrates, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups and each interconnect group of the plurality of interconnect groups is coupled to a different second circuit substrate of the plurality of second circuit substrates to form a different bridge structure of a plurality of bridge structures; and coupling each bridge structure of the plurality of bridge structures to the first circuit substrate, wherein the plurality of second circuit substrates are arranged over the surface of the first circuit substrate, wherein the plurality of conductive interconnect structures extend in a third dimension that is substantially perpendicular to the two-dimensional region, and wherein each first semiconductor chip package of the plurality of first semiconductor chip packages is arranged between the surface of the first circuit substrate and a respective second circuit substrate of the plurality of second circuit substrates in the third dimension.

Drawings

FIG. 1 is a diagram of an example apparatus that may be fabricated using the techniques described herein.

FIG. 2 is a diagram of an example memory device that can be fabricated using the techniques described herein.

FIG. 3A illustrates a side view of an example electronic system assembly in accordance with one or more implementations.

Fig. 3B illustrates a top view of the electronic system assembly shown in fig. 3A in accordance with one or more implementations.

FIG. 4 illustrates a side view of an example electronic system assembly in accordance with one or more implementations.

FIG. 5A illustrates a side view of an example electronic system assembly in accordance with one or more implementations.

FIG. 5B illustrates a side view of an example electronic system assembly in accordance with one or more implementations.

Fig. 6A and 6B illustrate example bridge structures in accordance with one or more implementations.

FIG. 7 is a flow chart of an example method of forming an electronic system assembly.

Detailed Description

Component densities on current and future Printed Circuit Board (PCB) assemblies are continually increasing and lead to problems with placement of components on PCBs. For example, current PCB designs for modules and Solid State Devices (SSDs) are subject to space constraints due to increasing component counts. Computing fast link ^TM(CXL^TM), an open standard for high speed Central Processing Unit (CPU) to device and CPU to memory connections, is one example of a module that does not have enough space to accommodate enough memory, such as Dynamic Random Access Memory (DRAM), on an area of the PCB.

In addition, as more components are added to the PCB, signal lines on the PCB may become longer (e.g., due to increasing distances between components), more complex (e.g., due to more complex routing designs), and/or more densely arranged (e.g., due to increasing numbers of signal lines per unit area). Thus, the signal integrity of signals transmitted along signal lines may be more susceptible to electrical interference, such as signal crosstalk between adjacent signal lines, higher resistance caused by longer signal lines, and electromagnetic interference caused by nearby components and adjacent signal lines.

Some implementations disclosed herein relate to an electronic system assembly having a main circuit substrate, such as a PCB, and an auxiliary circuit substrate mounted over the main circuit substrate. For example, some implementations relate to the use of three-dimensional (3D) space over a main circuit substrate by mounting an auxiliary circuit substrate over components mounted (directly) to the main circuit substrate, allowing for higher component densities and shorter signal paths in a two-dimensional footprint. For example, a conductive interconnect structure extending in a third dimension that is substantially perpendicular to the two-dimensional region of the primary circuit substrate may be used to mechanically and electrically couple the secondary circuit substrate to the primary circuit substrate. A system component, such as a plurality of first semiconductor chip packages, may be mounted to the primary circuit substrate, and an additional system component, such as a plurality of second semiconductor chip packages and/or storage capacitors, may be mounted to the secondary circuit substrate. Thus, the secondary circuit substrate serves to expand the amount of space available for mounting the system components in the third dimension, which is otherwise limited to the two-dimensional area of the primary circuit substrate. In some implementations, the two-dimensional footprint of the primary circuit substrate may be reduced due to the additional space provided by the secondary circuit substrate.

In addition, the conductive interconnect structure may enable vertical routing of signal lines to shorten signal paths between system components, which may improve signal integrity by reducing electrical interference. Furthermore, in some implementations, various chipset stacks (e.g., DRAM, NAND memory, and/or power management ICs) may be used in a 3D space formed by auxiliary circuit substrates to provide additional system capability that would otherwise be limited by the two-dimensional area of the auxiliary circuit substrate. In some implementations, the storage capacitor may be provided in a 3D space formed by the auxiliary circuit substrate by mounting the storage capacitor to the main circuit substrate and/or the auxiliary circuit substrate. In some implementations, stacked module routing and/or connection pins may be used to facilitate immunity from electromagnetic interference, signal crosstalk, and other electrical interference. The auxiliary circuit substrate may provide an opportunity to position the power and ground planes closer to the system components than would otherwise be possible. Furthermore, by increasing the separation of the secondary circuit substrate from the primary circuit substrate in the third dimension, the thermal performance of the individual system components and electronic system assemblies may be improved overall.

FIG. 1 is a diagram of an example apparatus 100 that may be fabricated using the techniques described herein. Apparatus 100 may comprise any type of device or system that includes one or more integrated circuits 105. For example, apparatus 100 may include memory devices, flash memory devices, NAND memory devices, NOR memory devices, random Access Memory (RAM) devices, read Only Memory (ROM) devices, dynamic RAM (DRAM) devices, static RAM (SRAM) devices, solid State Drives (SSDs), microchips, and/or system-on-a-chip (SoC), among other examples. In some cases, apparatus 100 may be referred to as a semiconductor package, assembly, semiconductor device assembly, or integrated assembly.

As shown in fig. 1, the apparatus 100 may include one or more integrated circuits 105, shown as a first integrated circuit 105-1 and a second integrated circuit 105-2, disposed on a substrate 110. Integrated circuit 105 may include any type of circuit, such as analog circuits, digital circuits, radio Frequency (RF) circuits, power supplies, power management circuits, input-output (I/O) chips, application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs), and/or memory devices (e.g., NAND memory devices, NOR memory devices, RAM devices, or ROM devices). The integrated circuit 105 may be mounted or otherwise disposed on a surface of the substrate 110. Although apparatus 100 is shown as including two integrated circuits 105 as an example, apparatus 100 may include a different number of integrated circuits 105.

In some implementations, the integrated circuit 105 may include a plurality of semiconductor dies 115 (sometimes referred to as dies), shown as 5 semiconductor dies 115-1 through 115-5. As shown in fig. 1, the dies 115 may be stacked on top of each other to reduce the footprint of the apparatus 100. Stacked dies 115 may include three-dimensional electrical interconnects, such as Through Silicon Vias (TSVs), to route electrical signals between dies 115. Although integrated circuit 105-2 is shown as including 5 dies 115, integrated circuit 105 may include a different number of dies 115 (e.g., at least two dies 115). A first die 115-1 (sometimes referred to as a bottom die or base die) may be disposed on the substrate 110, a second die 115-2 may be disposed on the first die 115-1, and so on.

The apparatus 100 may include a housing 120 that protects the internal components of the apparatus 100 (e.g., the integrated circuit 105) from damage and environmental factors (e.g., particulates) that may cause the apparatus 100 to malfunction. The housing 120 may be plastic (e.g., epoxy), ceramic, or another type of material, depending on the functional requirements of the device 100.

In some implementations, the apparatus 100 may be included as part of a higher-level system (e.g., a computer, mobile phone, network device, SSD, vehicle, or internet of things device), for example, by electrically connecting the apparatus 100 to a circuit board 125, such as a printed circuit board. For example, the substrate 110 may be disposed on the circuit board 125 such that the electrical contacts 130 (e.g., bond pads) of the substrate 110 are electrically connected to the electrical contacts 135 (e.g., bond pads) of the circuit board 125.

In some implementations, the substrate 110 may be mounted on the circuit board 125 using solder balls 140 (e.g., arranged in a ball grid array), and the solder balls 140 may be melted to form physical and electrical connections between the substrate 110 and the circuit board 125. Additionally or alternatively, the substrate 110 may be mounted to and/or electrically connected to the circuit board 125 using another type of connector, such as pins or leads. Similarly, the integrated circuit 105 may include electrical pads (e.g., bond pads) electrically connected to corresponding electrical pads (e.g., bond pads) of the substrate 110 using electrical bonding, such as wire bonding, bump bonding, or the like. The interconnections between the integrated circuit 105, the substrate 110, and the circuit board 125 enable the integrated circuit 105 to receive and transmit signals to other components and/or higher-level systems of the apparatus 100.

As indicated above, fig. 1 is merely exemplary. Other examples may differ from what is described with respect to fig. 1.

FIG. 2 is a diagram of an example memory device 200 that can be fabricated using the techniques described herein. Memory device 200 is an example of apparatus 100 described above in connection with fig. 1. Memory device 200 may be any electronic device configured to store data in memory. In some implementations, the memory device 200 may be an electronic device configured to persist data in the non-volatile memory 205. For example, the memory device 200 may be a hard disk drive, an SSD, a flash memory device (e.g., a NAND flash memory device or a NOR flash memory device), a Universal Serial Bus (USB) thumb drive, a memory card (e.g., a Secure Digital (SD) card), an auxiliary storage device, a non-volatile memory express (NVMe) device, and/or an embedded multimedia card (eMMC) device.

As shown, the memory device 200 may include a non-volatile memory 205, a volatile memory 210, and a controller 215. The components of the memory device 200 may be mounted or otherwise disposed on the substrate 220. In some implementations, the non-volatile memory 205 includes stacked semiconductor die 225, as described above in connection with fig. 1.

The non-volatile memory 205 may be configured to maintain stored data after the memory device 200 is powered down. For example, the non-volatile memory 205 may include NAND memory or NOR memory. The volatile memory 210 requires power to maintain the stored data and may lose the stored data after the memory device 200 is powered down. For example, the volatile memory 210 may include one or more latches and/or RAM, such as DRAM and/or SRAM. As an example, the volatile memory 210 may cache data read from or written to the nonvolatile memory 205 and/or may cache instructions executed by the controller 215.

The controller 215 may be any device configured to communicate with the non-volatile memory 205, the volatile memory 210, and the host device (e.g., via a host interface of the memory device 200). For example, the controller 215 may include a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and/or one or more processing components. In some implementations, the memory device 200 may be included in a system that includes a host device. The host device may include one or more processors configured to execute instructions and store data in the non-volatile memory 205.

The controller 215 may be configured to control the operation of the memory device 200, such as by executing one or more instructions (sometimes referred to as commands). For example, memory device 200 may store one or more instructions as firmware and controller 215 may execute the one or more instructions. Additionally or alternatively, the controller 215 may receive one or more instructions from the host device via the host interface and may execute the one or more instructions. For example, the controller 215 may transmit signals to the non-volatile memory 205 and/or the volatile memory 210 and/or receive signals from the non-volatile memory 205 and/or the volatile memory 210 based on one or more instructions, such as transferring (e.g., writing or programming) data to all or a portion of the non-volatile memory 205 (e.g., one or more memory cells, pages, sub-blocks, or planes of the non-volatile memory 205), transferring (e.g., reading) data from the all or a portion of the non-volatile memory 205, and/or erasing the all or a portion of the non-volatile memory 205.

As indicated above, fig. 2 is merely exemplary. Other examples may differ from what is described with respect to fig. 2. The number and arrangement of components shown in fig. 2 are for illustration only. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in FIG. 2.

Fig. 3A illustrates a side view of an example electronic system assembly 300 in accordance with one or more implementations. Fig. 3B illustrates a top view of an electronic system assembly 300 in accordance with one or more implementations. As shown in fig. 3A and 3B, the electronic system assembly 300 includes a first circuit substrate 302 (e.g., a main circuit substrate), a plurality of second circuit substrates 304 (e.g., auxiliary circuit substrates), a plurality of first semiconductor chip packages 306, a plurality of second semiconductor chip packages 308, and a plurality of conductive interconnect structures 310.

The first circuit substrate 302 may be a multi-layer circuit substrate, such as a PCB or other carrier substrate. In some implementations, the first circuit substrate 302 may be a motherboard or another type of system board to which system components of the electronic system assembly 300 are mounted. In particular, the first circuit substrate 302 has a major surface 312 (e.g., an upper surface) on which system components of the electronic system assembly 300 are mounted and/or electrically coupled thereto. Major surface 312 has a two-dimensional (2D) area defined in a first dimension (e.g., an x-dimension along an x-axis) and a second dimension (e.g., a y-dimension along a y-axis). Major surface 312 may define a first mounting plane on which a first plurality of system components are mounted. In this example, the first mounting plane is an x-y plane defined by an x-axis and a y-axis.

A plurality of second circuit substrates 304, shown as second circuit substrates 304-1 through 304-10, are positioned above the main surface 312, spatially separated from the main surface 312 in a third dimension (e.g., a z-dimension along the z-axis). In other words, the plurality of second circuit substrates 304 are offset from the major surface 312 in the third dimension to define a three-dimensional region between the major surface 312 and the plurality of second circuit substrates 304.

The plurality of second circuit substrates 304 may be multi-layer circuit substrates, such as PCBs or other carrier substrates. In some implementations, the plurality of second circuit substrates 304 may be daughter boards or another type of expansion board to which additional system components of the electronic system assembly 300 are mounted to extend the circuitry of the first circuit substrates 302. The plurality of second circuit substrates 304 may define an additional mounting plane substantially parallel to the first mounting plane on which the additional plurality of system assemblies are mounted. Thus, the plurality of second circuit substrates 304 expands the electronic system assembly 300 into a third dimension and enables vertical space above the major surface 312 for additional system components of the electronic system assembly 300. In particular, the plurality of second circuit substrates 304 provides additional surface area for mounting additional system components of the electronic system assembly 300. Thus, a higher component density may be achieved within the two-dimensional footprint of the major surface 312. In addition, the plurality of second circuit substrates 304 may allow additional system components to be positioned closer to other system components mounted to the major surface 312, thereby enabling shorter signal paths between system components and improving signal integrity.

The plurality of second circuit substrates 304 includes a top surface 314 (shown in fig. 3A as top surfaces 314-1 through 314-4, for example) and a bottom surface 316 (shown in fig. 3A as bottom surfaces 316-1 through 316-4, for example). In particular, each second circuit substrate 304 includes a respective one of the top surfaces 314 and a respective one of the bottom surfaces 316 disposed opposite the respective top surface. Top surface 314 and bottom surface 316 extend substantially parallel to major surface 312. In addition, the distance between the bottom surface 316 and the major surface 312 in the third dimension is less than the distance between the corresponding top surface 314 (e.g., opposite the bottom surface 316 on the same second circuit substrate 304) and the major surface 312 in the third dimension.

In some implementations, the second circuit substrate 304 may have different heights to accommodate, for example, different sized system components underneath. Thus, in some implementations, the distance between the bottom surface 316 and the corresponding top surface 314 in the third dimension may be different than the distance between another bottom surface 316 and another corresponding top surface 314 in the third dimension.

The top surface 314 and the bottom surface 316 provide additional surface area for mounting additional system components. In some implementations, additional system components may be mounted to the top surfaces 314 of the plurality of second circuit substrates 304. In some implementations, additional system components may be mounted to the bottom surface 316 of the plurality of second circuit substrates 304. In some implementations, both the top surface 314 and the bottom surface 316 may be used to house additional system components. In other words, additional system components may be mounted to the top surface 314 and the bottom surface 316 of the plurality of second circuit substrates 304.

A plurality of first semiconductor chip packages 306 are directly mounted to and electrically coupled to a major surface 312 of first circuit substrate 302. Each of the plurality of first semiconductor chip packages 306 is vertically positioned in the third dimension between the main surface 312 and a respective one of the plurality of second circuit substrates 304. In other words, each first semiconductor chip package 306 is arranged in a three-dimensional region vertically defined between the main surface 312 and the plurality of second circuit substrates 304. More particularly, each first semiconductor chip package 306 is arranged between the major surface 312 and one of the plurality of second circuit substrates 304 in a third dimension.

In the example illustrated in fig. 3A, the plurality of first semiconductor chip packages 306 are shown as first semiconductor chip packages 306-1 to 306-4 disposed under second circuit substrates 304-1 to 304-4, respectively. In practice, however, the first semiconductor chip package 306 may include additional semiconductor chip packages provided under the second circuit substrates 304-5 through 304-10 that are blocked from view in fig. 3A and 3B. In some implementations, multiple system components may be placed under a single second substrate 304.

The plurality of first semiconductor chip packages 306 may be electrically coupled to the major surface 312 by any type of electrical interconnect structure (e.g., balls, pins, leads, contact pads, surface mount contacts, or other electrical interconnect structure). Thus, the first circuit substrate 302 may be configured to be connected to any type of semiconductor package.

In some implementations, the first semiconductor chip package 306 may include one or more Integrated Circuits (ICs) including, for example, one or more digital ICs, one or more analog ICs, one or more hybrid analog and digital ICs, one or more logic ICs, one or more memory ICs (e.g., memory ICs), one or more power management ICs, or one or more other general purpose ICs or application specific ICs. In some implementations, the first semiconductor chip package 306 may be a memory device, such as a NAND memory device, a NOR memory device, a RAM device, a ROM device, or a DRAM device. In some implementations, the first semiconductor chip package 306 includes a combination of different types of memory devices or ICs. For example, some of the first semiconductor chip packages 306 may be one type of memory device or IC and some of the first semiconductor chip packages 306 may be another type of memory device or IC.

The electronic system assembly 300 can include a controller 318 mounted to and electrically coupled to the major surface 312. The first semiconductor chip package 306 may be electrically coupled to the controller 318 via the first circuit substrate 302 (e.g., via conductive paths). In some implementations, the controller 318 may be a memory controller and the conductive paths may include memory channels for storing data on the first semiconductor chip package 306 or accessing data stored on the first semiconductor chip package 306 (e.g., to write and read data).

In some implementations, in the top view shown in fig. 3B (e.g., in a plan view), a plurality of second circuit substrates 304 are positioned around the controller 318. For example, one or more second circuit substrates 304 may be positioned in a first direction along a first dimension from the controller 318, one or more second circuit substrates 304 may be positioned in a second direction along the first dimension from the controller 318 (e.g., opposite the first direction), one or more second circuit substrates 304 may be positioned in a third direction along the second dimension from the controller 318, and one or more second circuit substrates 304 may be positioned in a fourth dimension along the second dimension from the controller 318 (e.g., opposite the third direction). This enables some or all of the plurality of second circuit substrates 304 to be positioned in relatively close proximity to the controller 318, which enables a shorter signal path between each of the second circuit substrates 304 and the controller 318, thereby improving signal integrity.

A plurality of second semiconductor chip packages 308 are mounted to and electrically coupled to top surfaces 314 of the plurality of second circuit substrates 304. A plurality of second semiconductor chip packages 308 are shown as second semiconductor chip packages 308-1 through 308-10. Each of the plurality of second semiconductor chip packages 308 may be mounted in a one-to-one correspondence and electrically coupled to a respective one of the plurality of second circuit substrates 304. In some implementations, multiple system components may be mounted to a single second circuit substrate 304.

The plurality of second semiconductor chip packages 308 may be electrically coupled to the top surface 314 by any type of electrical interconnect structure, such as balls, pins, leads, contact pads, surface mount contacts, or other electrical interconnect structures. Thus, the second circuit substrate 304 may be configured to be connected to any type of semiconductor package.

In some implementations, the second semiconductor chip package 308 may include one or more ICs including, for example, one or more digital ICs, one or more analog ICs, one or more hybrid analog and digital ICs, one or more logic ICs, one or more storage ICs (e.g., memory ICs), one or more power management ICs, or one or more other general purpose ICs or application specific ICs. In some implementations, the second semiconductor chip package 308 may be a memory device, such as a NAND memory device, a NOR memory device, a RAM device, a ROM device, or a DRAM device. In some implementations, the second semiconductor chip package 308 includes a combination of different types of memory devices or ICs. For example, some of the second semiconductor chip packages 308 may be one type of memory device or IC and some of the second semiconductor chip packages 308 may be another type of memory device or IC.

The plurality of conductive interconnect structures 310 extend in a third dimension to connect the plurality of second circuit substrates 304, and more particularly, the second semiconductor chip packages 308, to the first circuit substrate 302. A plurality of conductive interconnect structures 310 are provided in a plurality of interconnect groups, including interconnect groups 320-1 through 320-4 shown in fig. 3A. Each of the plurality of interconnect groups 320-1 through 320-4 connects a different one of the plurality of second circuit substrates 304 to the first circuit substrate 302. Each of the plurality of interconnect groups 320-1 through 320-4 may provide one or more power supply paths, one or more ground supply paths, and one or more signal transmission paths (e.g., data signal transmission paths and/or control signal transmission paths). In the illustrated example of fig. 3A and 3B, the interconnect group 320 includes at least two conductive interconnect structures 310 (e.g., positioned on opposite sides of the first semiconductor chip package 306). However, in some implementations, the interconnect group 320 may include a different number of conductive interconnect structures 310 (e.g., three or four).

For example, the interconnect group 320-1 includes conductive interconnect structures 310 that connect the second circuit substrate 304-1 to the first circuit substrate 302 and provide electrical connections (e.g., power supply paths, ground supply paths, and signal transmission paths) to the second semiconductor chip package 308-1. The interconnect group 320-1 not only provides an electrical connection between the second circuit substrate 304-1 and the first circuit substrate 302, the interconnect group 320-1 also provides mechanical (e.g., structural) support to the second circuit substrate 304-1. In addition, the interconnect group 320-1 and the second circuit substrate 304-1 form a bridge structure across the first semiconductor chip package 306-1. For example, one or more conductive interconnect structures 310 of the interconnect group 320-1 may be positioned laterally adjacent or proximate to a first side of the first semiconductor chip package 306-1, and one or more other conductive interconnect structures 310 of the interconnect group 320-1 may be positioned laterally adjacent or proximate to a second side of the first semiconductor chip package 306-1, the second side being opposite the first side. In this manner, the interconnect group 320-1 may be considered to span the first semiconductor chip package 306-1 and the second circuit substrate 304-1 bridges (e.g., extends or spans) the first semiconductor chip package 306-1.

Interconnect groups 320-2, 320-3, and 320-4 provide similar electrical and mechanical connections to respective components and are arranged in a similar manner as described above in connection with interconnect group 320-1.

In some implementations, the conductive interconnect structure 310 can be a pin (e.g., jin Yinjiao) and the first circuit substrate 302 can include a plurality of vias configured to receive the conductive interconnect structure 310. In some implementations, the conductive interconnect structure 310 can be a pin (e.g., jin Yinjiao) surface mounted to the major surface 312 of the first circuit substrate 302. For example, the conductive interconnect structure 310 may be a surface mount pin (e.g., a surface mount technology pin) having a solder tip bonded to the major surface 312. In addition, the conductive interconnect structures 310 may be connected to the corresponding second circuit substrate 304 in a similar manner (e.g., via surface mounting or through-hole insertion).

The second semiconductor chip package 308 may be electrically coupled to the controller 318 via the first circuit substrate 302, the second circuit substrate 304, and the conductive interconnect structure 310 (e.g., via conductive paths). In some implementations, the controller 318 may be a memory controller, and the conductive paths connected to the second semiconductor chip package 308 may include memory channels for storing data on the second semiconductor chip package 308 or accessing data stored on the second semiconductor chip package 308 (e.g., for writing and reading data).

In some implementations, the conductive interconnect structure 310 can include an electrostatic discharge path from the plurality of second circuit substrates 304 to the first circuit substrate 302. For example, the second circuit substrate 304 may provide a connection to a power plane and a ground plane used in conjunction with one or more decoupling capacitors for electrostatic discharge. Thus, the plurality of second circuit substrates 304 may be used to optimize the power and ground planes closer to the system components that are protected from electrostatic discharge.

Although semiconductor chip packages 308 are described herein, in some implementations, electronic system assembly 300 may include a storage capacitor instead of one or more of semiconductor chip packages 308.

In some implementations, stacked module routing and/or connection pins may be used to facilitate immunity from electromagnetic interference, signal crosstalk, and other electrical interference. Furthermore, by increasing the separation of the second circuit substrate 304 from the first circuit substrate 302 in the third dimension, the thermal performance of the individual system components and electronic system assemblies may be improved overall. In some implementations, the heat transfer medium can be provided in a three-dimensional region disposed between the major surface 312 and the plurality of second circuit substrates 304. The heat transfer medium may be configured to transfer heat generated within the three-dimensional region to a periphery of the three-dimensional region. For example, the heat transfer medium may be a thermally conductive layer including a Thermal Interface Material (TIM).

As indicated above, fig. 3A and 3B are merely exemplary. Other examples may differ from what is described with respect to fig. 3A and 3B. The number and arrangement of components shown in fig. 3A and 3B are for illustration only. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in fig. 3A and 3B.

Fig. 4 illustrates a side view of an example electronic system assembly 400 in accordance with one or more implementations. The electronic system assembly 400 is similar to the electronic system assembly 300 shown in fig. 3A, except that a plurality of storage capacitors 402, shown as storage capacitors 402-1, 402-3, and 402-4, are mounted to some of the second circuit substrates 304 (e.g., second circuit substrates 304-1, 304-3, and 304-4). The second semiconductor chip package 308-2 is mounted to the second circuit substrate 304-2. In some implementations, the second semiconductor chip package 308-2 may be a power management device (e.g., including a power management IC or a power management controller) configured to perform power selection, power charging, power discharging, and/or power routing with respect to the storage capacitor 402.

For example, the storage capacitor 402 may be electrically coupled to the first semiconductor chip package 306 for providing backup power thereto. This configuration may be particularly useful when the first semiconductor chip package 306 is a volatile memory device that requires power to maintain stored data. The power management device may be configured to detect a power failure and route stored power from the storage capacitor to the first semiconductor chip package 306 (e.g., for maintaining stored data). Once normal operating power to the first semiconductor chip package 306 is restored, the power management device may be configured to route power to the storage capacitor 402 for recharging. Thus, the second circuit substrate 304 provides additional surface area of the storage capacitor 402 that can be used to house a mobile power supply that forms system components of the electronic system assembly 300.

Although fig. 4 shows a power management device mounted on the second circuit substrate 304-2, in some implementations, the power management device may be mounted to the major surface 312 of the first circuit substrate 302 and the storage capacitor may be mounted on the second circuit substrate 304-2.

As indicated above, fig. 4 is merely exemplary. Other examples may differ from what is described with respect to fig. 4. The number and arrangement of components shown in fig. 4 are for illustration only. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in FIG. 4.

Fig. 5A illustrates a side view of an example electronic system assembly 500A in accordance with one or more implementations. The electronic system assembly 500A is similar to the electronic system assembly 300 shown in fig. 3A, except that a plurality of third semiconductor chip packages 502 are provided. A third semiconductor chip package 502, shown as third semiconductor chip packages 502-1 through 502-4, is mounted to the bottom surface 316 of the second circuit substrate 304. In particular, each third semiconductor chip package of the plurality of third semiconductor chip packages 502 is mounted and electrically coupled to the bottom surface 316 of a respective second circuit substrate of the plurality of second circuit substrates 304. Thus, the plurality of second circuit substrates 304 support a double sided mounting in which the second semiconductor chip package 308 is mounted to the top surface 314 of the second circuit substrate 304 and the third semiconductor chip package 502 is mounted to the bottom surface 316 of the second circuit substrate 304. Thus, the component density of electronic system assembly 500A is further increased within the two-dimensional footprint of major surface 312.

In this example, each interconnect group 320 of the conductive interconnect structures 310 includes additional conductive interconnect structures for electrically connecting the third semiconductor chip package 502 to the first circuit substrate 302. Additional conductive interconnect structures may provide one or more power supply paths, one or more ground supply paths, and one or more signal transmission paths (e.g., data signal transmission paths and/or control signal transmission paths) to each of the third semiconductor chip packages 502. Alternatively, in some implementations, some of the conductive interconnect structures 310 may be shared between the second semiconductor chip package 308 and the third semiconductor chip package 502. For example, the power supply path and the ground supply path provided by the conductive interconnect structure 310 and routed through the second circuit substrate 304 may be shared between the second semiconductor chip package 308 and a third semiconductor chip package 502 mounted to the same second circuit substrate 304. In some implementations, some of the second circuit substrates 304 may be single mount (e.g., top or bottom mount) and some of the second circuit substrates 304 may be dual mount (e.g., top and bottom mount).

In some implementations, the third semiconductor chip package 502 may include one or more ICs including, for example, one or more digital ICs, one or more analog ICs, one or more hybrid analog and digital ICs, one or more logic ICs, one or more memory ICs (e.g., memory ICs), one or more power management ICs, or one or more other general purpose ICs or application specific ICs. In some implementations, the third semiconductor chip package 502 may be a memory device, such as a NAND memory device, a NOR memory device, a RAM device, a ROM device, or a DRAM device. In some implementations, the third semiconductor chip package 502 includes a combination of different types of memory devices or ICs. For example, some of the third semiconductor chip packages 502 may be one type of memory device or IC and some of the third semiconductor chip packages 502 may be another type of memory device or IC.

Although the third semiconductor chip package 502 is described herein, in some implementations, the electronic system assembly 500A may include a storage capacitor instead of one or more of the third semiconductor chip packages 502.

As indicated above, fig. 5A is merely exemplary. Other examples may differ from what is described with respect to fig. 5A. The number and arrangement of components shown in fig. 5A are for illustration only. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in FIG. 5A.

Fig. 5B illustrates a side view of an example electronic system assembly 500B in accordance with one or more implementations. The electronic system assembly 500B is similar to the electronic system assembly 500A shown in fig. 5A, except that a heat transfer medium 504, such as a fluid (e.g., gas) or TIM, is provided in a three-dimensional region disposed between the major surface 312 and the plurality of second circuit substrates 304. The heat transfer medium 504 may be configured to transfer heat generated within the three-dimensional region to the periphery of the three-dimensional region. For example, heat may be generated by one or more of the first semiconductor chip packages 306 and/or one or more of the third semiconductor chip packages 502. The heat transfer medium 504 may be configured to carry heat away from these system components to prevent overheating and ensure that normal operating parameters are met.

As indicated above, fig. 5B is merely exemplary. Other examples may differ from what is described with respect to fig. 5B. The number and arrangement of components shown in fig. 5B are for illustration only. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in FIG. 5B.

Fig. 6A and 6B illustrate example bridge structures 600A and 600B in accordance with one or more implementations. In particular, bridge structures 600A and 600B are possible variations of the bridge structures described above and shown in connection with fig. 3A, 4, 5A, and 5B.

The bridge structure 600A includes a storage capacitor 602 mounted on the top surface 314 of the second circuit substrate 304 and a semiconductor chip package 604 mounted on the bottom surface 316 of the second circuit substrate 304. The storage capacitor 602 may be one of the storage capacitors 402 described above. The semiconductor chip package 604 may be one of the third semiconductor chip packages 502 described above. One or more bridge structures 600A may be coupled to the first circuit substrate 302 via the conductive interconnect structure 310 to extend system components and capabilities of an electronic system assembly (e.g., electronic system assembly 300, 400, 500A, or 500B).

The bridge structure 600B includes a storage capacitor 602 mounted on the bottom surface 316 of the second circuit substrate 304 and a semiconductor chip package 604 mounted on the top surface 314 of the second circuit substrate 304. The storage capacitor 602 may be one of the storage capacitors 402 described above. The semiconductor chip package 604 may be one of the second semiconductor chip packages 308 described above. One or more bridge structures 600B may be coupled to the first circuit substrate 302 via the conductive interconnect structure 310 to extend system components and capabilities of an electronic system assembly (e.g., electronic system assembly 300, 400, 500A, or 500B).

As indicated above, fig. 6A and 6B are merely exemplary. Other examples may differ from what is described with respect to fig. 6A and 6B. The number and arrangement of components shown in fig. 6A and 6B are for illustration only. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in fig. 6A and 6B.

Fig. 7 is a flow chart of an example method 700 of forming an electronic system assembly. In some implementations, one or more of the process blocks of fig. 7 may be performed by various semiconductor manufacturing equipment.

As shown in fig. 7, a method 700 may include mounting a plurality of first semiconductor chip packages onto a surface of a first circuit substrate to be in electrical contact with the first circuit substrate, wherein the surface of the first circuit substrate has a two-dimensional area defined in a first dimension and a second dimension (block 710).

As further shown in fig. 7, the method 700 may include mounting a plurality of second semiconductor chip packages to a plurality of second circuit substrates, wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to a respective second circuit substrate of the plurality of second circuit substrates (block 720).

As further shown in fig. 7, method 700 may include coupling a plurality of conductive interconnect structures to a plurality of second circuit substrates, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups and each interconnect group of the plurality of interconnect groups is coupled to a different second circuit substrate of the plurality of second circuit substrates to form a different bridge structure of the plurality of bridge structures (block 730).

As further shown in fig. 7, the method 700 may include coupling each bridge structure of the plurality of bridge structures to a first circuit substrate, wherein a plurality of second circuit substrates are disposed over a surface of the first circuit substrate, wherein the plurality of conductive interconnect structures extend in a third dimension that is substantially perpendicular to the two-dimensional region, and wherein each first semiconductor chip package of the plurality of first semiconductor chip packages is disposed between the surface of the first circuit substrate and a respective second circuit substrate of the plurality of second circuit substrates in the third dimension (block 740).

Method 700 may include additional aspects, such as any single aspect or any combination of aspects described below and/or in connection with one or more other methods described elsewhere herein.

Although fig. 7 shows example blocks of the method 700, in some implementations, the method 700 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in fig. 7. In some implementations, the method 700 can include forming a structure of an electronic system assembly (e.g., electronic system assembly 300, 400, 500A, or 500B), an integrated assembly including an electronic system assembly (e.g., electronic system assembly 300, 400, 500A, or 500B), any component of an electronic system assembly (e.g., electronic system assembly 300, 400, 500A, or 500B) described herein, and/or any component of an integrated assembly including an electronic system assembly (e.g., electronic system assembly 300, 400, 500A, or 500B) described herein. For example, the method 700 may include forming one or more of the components 302, 304, 306, 308, 310, 318, 402, 502, 504, 602, 604, and/or 606 and combining one or more of the components 302, 304, 306, 308, 310, 318, 402, 502, 504, 602, 604, and/or 606 to form an electronic system assembly (e.g., electronic system assembly 300, 400, 500A, or 500B).

The following provides an overview of some aspects of the disclosure:

Aspect 1: an electronic system assembly, comprising: a first circuit substrate having a first surface, wherein the first surface has a two-dimensional area defined in a first dimension and a second dimension; a plurality of first semiconductor chip packages mounted on and electrically coupled to the first surface; a plurality of second circuit substrates positioned over the first surface, wherein each first semiconductor chip package of the plurality of first semiconductor chip packages is arranged in a third dimension between the first surface and a respective second circuit substrate of the plurality of second circuit substrates; a plurality of conductive interconnect structures extending in the third dimension, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups, and wherein each interconnect group of the plurality of interconnect groups connects a different one of the plurality of second circuit substrates to the first circuit substrate; and a plurality of second semiconductor chip packages, wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to a respective second circuit substrate of the plurality of second circuit substrates.

Aspect 2: the electronic system assembly of aspect 1, wherein each interconnect group of the plurality of interconnect groups spans a respective first semiconductor chip package of the plurality of first semiconductor chip packages.

Aspect 3: the electronic system assembly of any one of aspects 1-2, wherein each interconnect group of the plurality of interconnect groups mechanically supports a different second circuit substrate of the plurality of second circuit substrates to form a corresponding bridge structure that spans a respective first semiconductor chip package of the plurality of first semiconductor chip packages.

Aspect 4: the electronic system assembly of any one of aspects 1-3, wherein the first plurality of semiconductor chip packages are mounted directly on the first surface by electrical interconnects.

Aspect 5: the electronic system assembly of any one of aspects 1-4, wherein the second plurality of circuit substrates are offset from the first surface in the third dimension to define a three-dimensional region in which the plurality of first semiconductor chip packages are arranged.

Aspect 6: the electronic system assembly of aspect 5, further comprising: a heat transfer medium disposed in the three-dimensional region, wherein the heat transfer medium is configured to transfer heat generated within the three-dimensional region to a periphery of the three-dimensional region.

Aspect 7: the electronic system assembly of aspect 6, wherein the heat transfer medium is a thermally conductive layer comprising a thermal interface material.

Aspect 8: the electronic system assembly of any of aspects 1-7, wherein each second circuit substrate of the plurality of second circuit substrates includes a second surface and a third surface arranged opposite the second surface, wherein the second surface and the third surface extend substantially parallel to the first surface, and wherein a distance between the third surface and the first surface is less than a distance between the second surface and the first surface, and wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to the second surface of the respective second circuit substrate of the plurality of second circuit substrates.

Aspect 9: the electronic system assembly of aspect 8, further comprising: at least one storage capacitor, wherein each storage capacitor of the at least one storage capacitor is mounted and electrically coupled to the third surface of a respective second circuit substrate of the plurality of second circuit substrates.

Aspect 10: the electronic system assembly of any of aspects 1-9, wherein each second circuit substrate of the plurality of second circuit substrates includes a second surface and a third surface arranged opposite the second surface, wherein the second surface and the third surface extend substantially parallel to the first surface, and wherein a distance between the third surface and the first surface is less than a distance between the second surface and the first surface, and wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to the third surface of the respective second circuit substrate of the plurality of second circuit substrates.

Aspect 11: the electronic system assembly of aspect 10, further comprising: a plurality of third semiconductor chip packages, wherein each third semiconductor chip package of the plurality of third semiconductor chip packages is mounted and electrically coupled to the second surface of a respective second circuit substrate of the plurality of second circuit substrates.

Aspect 12: the electronic system assembly of aspect 10, further comprising: at least one storage capacitor, wherein each storage capacitor of the at least one storage capacitor is mounted and electrically coupled to the second surface of a respective second circuit substrate of the plurality of second circuit substrates.

Aspect 13: the electronic system assembly of any one of aspects 1-12, further comprising: a controller mounted on the first surface, wherein the controller is electrically coupled to the plurality of first semiconductor chip packages via the first circuit substrate, and wherein the controller is electrically coupled to the plurality of second semiconductor chip packages via the plurality of second circuit substrates, the plurality of conductive interconnect structures, and the first circuit substrate.

Aspect 14: the electronic system assembly of aspect 13, wherein in plan view the plurality of second circuit substrates are positioned around the controller.

Aspect 15: the electronic system assembly of any one of aspects 1-14, wherein the first circuit substrate is a motherboard and the plurality of second circuit substrates are daughter circuit boards.

Aspect 16: the electronic system assembly of any of aspects 1-15, wherein the plurality of first semiconductor chip packages includes a first plurality of memory Integrated Circuits (ICs) and the plurality of second semiconductor chip packages includes a second plurality of memory ICs.

Aspect 17: the electronic system assembly of aspect 16, wherein the first circuit substrate comprises a plurality of memory channels and each second semiconductor chip package of the plurality of second semiconductor chip packages and each interconnect group of the plurality of interconnect groups is coupled to a respective memory channel of the plurality of memory channels.

Aspect 18: the electronic system assembly of aspect 16, further comprising: a memory controller mounted on the first surface, wherein the memory controller is electrically coupled to the plurality of first semiconductor chip packages via the first circuit substrate, and wherein the memory controller is electrically coupled to the plurality of second semiconductor chip packages via the plurality of second circuit substrates, the plurality of conductive interconnect structures, and the first circuit substrate.

Aspect 19: the electronic system assembly of any of aspects 1-18, wherein the plurality of second semiconductor chip packages includes at least one power management Integrated Circuit (IC).

Aspect 20: the electronic system assembly of any of aspects 1-19, wherein the plurality of conductive interconnect structures includes electrostatic discharge paths from the plurality of second circuit substrates to the first circuit substrate.

Aspect 21: an electronic system assembly, comprising: a first circuit substrate having a first surface, wherein the first surface has a two-dimensional area defined in a first dimension and a second dimension; a plurality of semiconductor chip packages mounted on and electrically coupled to the first surface; a plurality of second circuit substrates disposed over the first surface, wherein each semiconductor chip package of the plurality of semiconductor chip packages is disposed between the first surface and a respective second circuit substrate of the plurality of second circuit substrates in a third dimension; a plurality of conductive interconnect structures extending in the third dimension, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups, and wherein each interconnect group of the plurality of interconnect groups connects a different one of the plurality of second circuit substrates to the first circuit substrate; and a plurality of storage capacitors, wherein each storage capacitor of the plurality of storage capacitors is mounted and electrically coupled to a respective second circuit substrate of the plurality of second circuit substrates.

Aspect 22: the electronic system assembly of aspect 21, wherein each interconnect group of the plurality of interconnect groups supports a different second circuit substrate of the plurality of second circuit substrates to form a corresponding bridge structure that spans respective semiconductor chip packages of the plurality of semiconductor chip packages.

Aspect 23: the electronic system assembly of any one of aspects 21-22, further comprising: a controller mounted on the first surface, wherein the controller is configured to distribute power from the plurality of storage capacitors to the plurality of semiconductor chip packages.

Aspect 24: the electronic system assembly of aspect 23, wherein the plurality of semiconductor chip packages includes a plurality of memory Integrated Circuits (ICs).

Aspect 25: a method of manufacturing an electronic system assembly, the method comprising: mounting a plurality of first semiconductor chip packages onto a surface of a first circuit substrate to be in electrical contact with the first circuit substrate, wherein the surface of the first circuit substrate has a two-dimensional area defined in a first dimension and a second dimension; mounting a plurality of second semiconductor chip packages to a plurality of second circuit substrates, wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to a respective second circuit substrate of the plurality of second circuit substrates; coupling a plurality of conductive interconnect structures to the plurality of second circuit substrates, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups and each interconnect group of the plurality of interconnect groups is coupled to a different second circuit substrate of the plurality of second circuit substrates to form a different bridge structure of a plurality of bridge structures; and coupling each bridge structure of the plurality of bridge structures to the first circuit substrate, wherein the plurality of second circuit substrates are arranged over the surface of the first circuit substrate, wherein the plurality of conductive interconnect structures extend in a third dimension that is substantially perpendicular to the two-dimensional region, and wherein each first semiconductor chip package of the plurality of first semiconductor chip packages is arranged between the surface of the first circuit substrate and a respective second circuit substrate of the plurality of second circuit substrates in the third dimension.

The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Modifications and variations are possible in light of the above disclosure or may be acquired from practice of the implementations described herein.

Each of the illustrated x, y, and z axes is substantially perpendicular to the other two axes. In other words, the x-axis is substantially perpendicular to the y-axis and the z-axis, the y-axis is substantially perpendicular to the x-axis and the z-axis, and the z-axis is substantially perpendicular to the x-axis and the y-axis. In some cases, a single reference numeral is shown to refer to a surface, or a non-complete example of a component may be labeled with all surfaces of the component. All examples of a component may include the associated surfaces of the component, although each surface is not labeled.

The orientation of the various elements in the figures is shown as an example, and the illustrated example may be rotated relative to the depicted orientation. The description provided herein and the claims that follow relate to any structure that has a descriptive relationship between various features, whether the structure is in the particular orientation of the drawings or rotated relative to such orientation. Similarly, spatially relative terms such as "below," "lower," "upper," "middle," "left," and "right" are used herein for ease of description to describe one element's relationship to one or more other elements as illustrated in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of the elements, structures, and/or components in use or operation. The structure and/or assembly may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Moreover, unless otherwise indicated, cross-sectional views in the figures show only features in the plane of the cross-section and do not show material behind the plane of the cross-section in order to simplify the drawing.

As used herein, the terms "substantially" and "approximately" mean "within reasonable manufacturing and measurement tolerances.

Even though particular combinations of features are recited in the claims and/or disclosed in the specification, such combinations are not intended to limit the disclosure of embodiments described herein. Many of these features may be combined in ways not specifically recited in the claims and/or disclosed in the specification. For example, the disclosure includes each dependent claim of a claim set in combination with each other individual claim of the claim set and each combination of multiple claims of the claim set. As used herein, a phrase referring to "at least one of a list of items" refers to any combination of the items, including individual members. As an example of this, the process may be performed, "at least one of a, b or c" is intended to encompass a, b, c, a +b, a+c b+c and a+b+c, and any combination with a plurality of the same elements (e.g., a+a, a+a+a b+c and a+b+c, and any combination with a plurality of the same elements (e.g., a+a a+a+a.

No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Moreover, as used herein, the article "a" is intended to include one or more items and may be used interchangeably with "one or more". Furthermore, as used herein, the article "the" is intended to include and be used interchangeably with one or more items referenced in conjunction with the article "the". When only one item is desired, the phrase "only one", "single" or similar language is used. Also, as used herein, the term "having" or the like is intended to be an open term for an element that does not limit its modification (e.g., "an element having" a may also have B). Furthermore, unless expressly stated otherwise, the phrase "based on" is intended to mean "based, at least in part, on". As used herein, the term "multiple" may be replaced with "multiple (a pluralityof)" and vice versa. Also, as used herein, the term "or" when used in a series is intended to be inclusive and interchangeable with "and/or" unless explicitly stated otherwise (e.g., if used in combination with any one of "(either) or" only one of … ").

Claims (20)

1. An electronic system assembly, comprising: A first circuit substrate having a first surface, wherein the first surface has a two-dimensional area defined in a first dimension and a second dimension; a plurality of first semiconductor chip packages mounted on and electrically coupled to the first surface; a plurality of second circuit substrates positioned over the first surface, wherein each first semiconductor chip package of the plurality of first semiconductor chip packages is arranged in a third dimension between the first surface and a corresponding second circuit substrate of the plurality of second circuit substrates; a plurality of conductive interconnect structures extending in the third dimension, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups, and wherein each interconnect group of the plurality of interconnect groups connects a different second circuit substrate of the plurality of second circuit substrates to the first circuit substrate; and A plurality of second semiconductor chip packages, wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to a corresponding second circuit substrate of the plurality of second circuit substrates. 2 . The electronic system assembly of claim 1 , wherein each interconnect group of the plurality of interconnect groups spans across a respective first semiconductor chip package of the plurality of first semiconductor chip packages. 3. The electronic system assembly of claim 1 , wherein each interconnect group of the plurality of interconnect groups mechanically supports a different second circuit substrate of the plurality of second circuit substrates to form a corresponding bridge structure that spans a corresponding first semiconductor chip package of the plurality of first semiconductor chip packages. 4. The electronic system assembly of claim 1, wherein the first plurality of semiconductor chip packages are mounted directly on the first surface via electrical interconnects. 5. The electronic system assembly of claim 1, wherein the second plurality of circuit substrates are offset from the first surface in the third dimension to define a three-dimensional area in which the plurality of first semiconductor chip packages are arranged. 6. The electronic system assembly of claim 5, further comprising: A heat conductive material is arranged in the three-dimensional region, wherein the heat conductive material is configured to transfer heat generated in the three-dimensional region to a periphery of the three-dimensional region. 7. The electronic system assembly of claim 1 , wherein each of the plurality of second circuit substrates comprises a second surface and a third surface arranged opposite to the second surface, wherein the second surface and the third surface extend substantially parallel to the first surface, and wherein a distance between the third surface and the first surface is smaller than a distance between the second surface and the first surface, and Wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to the second surface of the corresponding second circuit substrate of the plurality of second circuit substrates. 8. The electronic system assembly of claim 7, further comprising: At least one storage capacitor, wherein each storage capacitor of the at least one storage capacitor is mounted and electrically coupled to the third surface of a corresponding second circuit substrate of the plurality of second circuit substrates. 9. The electronic system assembly of claim 1 , wherein each of the plurality of second circuit substrates comprises a second surface and a third surface arranged opposite to the second surface, wherein the second surface and the third surface extend substantially parallel to the first surface, and wherein a distance between the third surface and the first surface is smaller than a distance between the second surface and the first surface, and Wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to the third surface of the corresponding second circuit substrate of the plurality of second circuit substrates. 10. The electronic system assembly of claim 9, further comprising: A plurality of third semiconductor chip packages, wherein each third semiconductor chip package of the plurality of third semiconductor chip packages is mounted and electrically coupled to the second surface of a corresponding second circuit substrate of the plurality of second circuit substrates. 11. The electronic system assembly of claim 9, further comprising: At least one storage capacitor, wherein each storage capacitor of the at least one storage capacitor is mounted and electrically coupled to the second surface of a corresponding second circuit substrate of the plurality of second circuit substrates. 12. The electronic system assembly of claim 1, further comprising: a controller mounted on the first surface, wherein the controller is electrically coupled to the plurality of first semiconductor chip packages via the first circuit substrate, and Wherein the controller is electrically coupled to the plurality of second semiconductor chip packages via the plurality of second circuit substrates, the plurality of conductive interconnect structures and the first circuit substrate. 13. The electronic system assembly of claim 1, wherein the plurality of first semiconductor chip packages comprises a first plurality of memory integrated circuits (ICs) and the plurality of second semiconductor chip packages comprises a second plurality of memory ICs. 14. The electronic system assembly of claim 13, wherein the first circuit substrate comprises a plurality of memory channels and each second semiconductor chip package of the plurality of second semiconductor chip packages and each interconnect group of the plurality of interconnect groups are coupled to a respective memory channel of the plurality of memory channels. 15. The electronic system assembly of claim 13, further comprising: a memory controller mounted on the first surface, wherein the memory controller is electrically coupled to the plurality of first semiconductor chip packages via the first circuit substrate, and Wherein the memory controller is electrically coupled to the plurality of second semiconductor chip packages via the plurality of second circuit substrates, the plurality of conductive interconnect structures, and the first circuit substrate. 16. The electronic system assembly of claim 1, wherein the plurality of second semiconductor chip packages include at least one power management integrated circuit (IC). 17. An electronic system assembly, comprising: A first circuit substrate having a first surface, wherein the first surface has a two-dimensional area defined in a first dimension and a second dimension; a plurality of semiconductor chip packages mounted on and electrically coupled to the first surface; a plurality of second circuit substrates arranged on the first surface, wherein each semiconductor chip package of the plurality of semiconductor chip packages is arranged between the first surface and a corresponding second circuit substrate of the plurality of second circuit substrates in a third dimension; a plurality of conductive interconnect structures extending in the third dimension, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups, and wherein each interconnect group of the plurality of interconnect groups connects a different second circuit substrate of the plurality of second circuit substrates to the first circuit substrate; and A plurality of storage capacitors, wherein each storage capacitor of the plurality of storage capacitors is mounted and electrically coupled to a respective second circuit substrate of the plurality of second circuit substrates. 18. The electronic system assembly of claim 17, wherein each interconnect group of the plurality of interconnect groups supports a different second circuit substrate of the plurality of second circuit substrates to form a corresponding bridge structure that spans a respective semiconductor chip package of the plurality of semiconductor chip packages. 19. The electronic system assembly of claim 17, further comprising: A controller is mounted on the first surface, wherein the controller is configured to distribute power from the plurality of storage capacitors to the plurality of semiconductor chip packages. 20. A method of manufacturing an electronic system assembly, the method comprising: Mounting a plurality of first semiconductor chip packages on a surface of a first circuit substrate to be in electrical contact with the first circuit substrate, wherein the surface of the first circuit substrate has a two-dimensional area defined in a first dimension and a second dimension; mounting a plurality of second semiconductor chip packages to a plurality of second circuit substrates, wherein each second semiconductor chip package of the plurality of second semiconductor chip packages is mounted and electrically coupled to a corresponding second circuit substrate of the plurality of second circuit substrates; coupling a plurality of conductive interconnect structures to the plurality of second circuit substrates, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups and each of the plurality of interconnect groups is coupled to a different one of the plurality of second circuit substrates to form a different one of a plurality of bridge structures; and Each bridge structure of the plurality of bridge structures is coupled to the first circuit substrate, wherein the plurality of second circuit substrates are arranged above the surface of the first circuit substrate, wherein the plurality of conductive interconnect structures extend in a third dimension substantially perpendicular to the two-dimensional area, and wherein each first semiconductor chip package of the plurality of first semiconductor chip packages is arranged in the third dimension between the surface of the first circuit substrate and a corresponding second circuit substrate of the plurality of second circuit substrates.