CN118173153B - Bad block management program verification method, product and storage medium - Google Patents
Bad block management program verification method, product and storage medium Download PDFInfo
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- 238000012795 verification Methods 0.000 claims abstract description 44
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
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Abstract
The application relates to the technical field of storage, in particular to a bad block management program verification method, a bad block management program verification product and a bad block management program storage medium, aiming at improving the verification efficiency of the bad block management program. The method comprises the following steps: receiving a bad block simulation configuration command; analyzing the bad block simulation configuration command to obtain a bad block simulation configuration parameter corresponding to the bad block simulation configuration command; generating a corresponding virtual flash memory according to the bad block simulation configuration parameters; designating a plurality of first bad blocks in the virtual flash memory according to preset bad block conditions; performing bad block detection on the virtual flash memory through a bad block scanning program to obtain a plurality of second bad blocks; and verifying the bad block management program by comparing the plurality of first bad blocks with the plurality of second bad blocks.
Description
Technical Field
The embodiment of the application belongs to the technical field of storage, and particularly relates to a bad block management program verification method, a bad block management program verification product and a bad block management program storage medium.
Background
SSD (Solid STATE DRIVE, solid state disk) is a storage device composed of flash memories (flash), each flash memory includes a plurality of storage blocks (blocks), and when in use, the storage blocks may be damaged, in order to determine whether the storage blocks in the flash memory are bad blocks, in the related art, the bad blocks are detected and recorded through a bad block management program, when the compatibility and reliability of the bad block management program are verified, an operation command is directly sent to each storage block at the rear end through a bad block scanning program, whether the storage blocks are bad blocks is determined according to state information returned by the rear end, and then whether the storage blocks are bad blocks is manually verified by a worker.
In the related art, the verification of the bad block management program depends on a hardware structure, each verification needs to interact with the storage device, and then the staff manually verifies, so that the steps of verifying the compatibility and the reliability of the bad block management program in firmware development are complex, the development efficiency is reduced, and the test efficiency is also reduced by a manual verification mode.
Disclosure of Invention
The embodiment of the application provides a bad block management program verification method, a bad block management program verification product and a storage medium, aiming at improving the verification efficiency of a bad block management program.
An embodiment of the present application provides a bad block management program verification method, where the method includes:
receiving a bad block simulation configuration command;
Analyzing the bad block simulation configuration command to obtain a bad block simulation configuration parameter corresponding to the bad block simulation configuration command;
Generating a corresponding virtual flash memory according to the bad block simulation configuration parameters;
Designating a plurality of first bad blocks in the virtual flash memory according to preset bad block conditions;
Performing bad block detection on the virtual flash memory through a bad block scanning program to obtain a plurality of second bad blocks;
And verifying the bad block management program by comparing the plurality of first bad blocks with the plurality of second bad blocks.
Optionally, the analyzing the bad block simulation configuration command to obtain a bad block simulation configuration parameter corresponding to the bad block simulation configuration command includes:
reading each field of the bad block emulation configuration command in sequence;
And determining the number of channels, the number of chip enabling units, the number of functional units, the number of storage matrixes, the number of storage blocks and the bad block rate designated by the bad block simulation configuration parameters according to the fields.
Optionally, the method further comprises:
Verifying the bad block simulation configuration command;
under the condition that the bad block simulation configuration command is a legal command, loading the bad block simulation configuration parameters into the bad block scanning program;
and returning a command error message in the case that the bad block emulation configuration command is not a legal command.
Optionally, the generating the corresponding virtual flash according to the bad block emulation configuration parameters includes:
Determining a flash memory structure of the virtual flash memory to be generated according to the bad block simulation configuration parameters;
and generating the corresponding virtual flash memory according to the flash memory structure.
Optionally, the designating a plurality of first bad blocks in the virtual flash memory according to a preset bad block condition includes:
traversing each storage block in the virtual flash memory according to the address increasing sequence;
determining, for each of the memory blocks, whether the memory block satisfies the bad block condition;
And designating the storage block as the first bad block in the case that the storage block satisfies the bad block condition.
Optionally, the expression corresponding to the preset bad block condition is:
rand ()% (1/bad block rate) = 0
Wherein a 1/bad block rate represents the number of said memory blocks required for the presence of at least one said bad block, and rand () represents a random number.
Optionally, the designating the storage block as the first bad block includes:
Running a bad block setting program;
And setting the storage block as the first bad block in a bitmap through the bad block setting program.
Optionally, the method further comprises:
recording a storage block number, a functional unit number, a chip enabling unit number and a channel number corresponding to the first bad block in the virtual flash memory;
And recording the bit number, the byte number and the byte position corresponding to the first bad block in the bitmap.
Optionally, the detecting bad blocks of the virtual flash memory by the bad block scanning program to obtain a plurality of second bad blocks includes:
Running the bad block scanning program;
And scanning each storage block in the virtual flash memory through the bad block scanning program to obtain a plurality of second bad blocks.
Optionally, the scanning, by the bad block scanning program, each storage block in the virtual flash memory to obtain a plurality of second bad blocks includes:
transmitting a corresponding instruction to each storage block in the virtual flash memory through the bad block scanning program;
And when the response message returned by the storage block is an abnormal message, determining that the storage block is the second bad block.
Optionally, the method further comprises:
recording a storage block number, a functional unit number, a chip enabling unit number and a channel number corresponding to the second bad block in the virtual flash memory;
And recording the bit number, the byte number and the byte position corresponding to the second bad block in the bitmap.
Optionally, the verifying the bad block management program by comparing a plurality of the first bad blocks with a plurality of the second bad blocks includes:
Reading record information corresponding to each first bad block and each second bad block according to each first bad block and each second bad block;
when the record information corresponding to the first bad block and the second bad block are matched, determining that the second bad block is correctly identified;
passing verification of the bad block manager if each of the second bad blocks is identified as correct;
In the case that there is a bad block that does not match the plurality of the first bad blocks among the plurality of the second bad blocks, the bad block manager fails the verification.
A second aspect of an embodiment of the present application provides a bad block management program verification apparatus, the apparatus including:
the command receiving module is used for receiving a bad block simulation configuration command;
The simulation configuration parameter acquisition module is used for analyzing the bad block simulation configuration command to obtain a bad block simulation configuration parameter corresponding to the bad block simulation configuration command;
the virtual flash memory generation module is used for generating a corresponding virtual flash memory according to the bad block simulation configuration parameters;
The first bad block determining module is used for designating a plurality of first bad blocks in the virtual flash memory according to preset bad block conditions;
the second bad block determining module is used for carrying out bad block detection on the virtual flash memory through a bad block scanning program to obtain a plurality of second bad blocks;
And the program verification module is used for verifying the bad block management program by comparing the plurality of first bad blocks with the plurality of second bad blocks.
Optionally, the simulation configuration parameter obtaining module includes:
the field reading sub-module is used for sequentially reading each field of the bad block simulation configuration command;
and the parameter determination submodule is used for determining the channel number, the chip enabling unit number, the functional unit number, the storage matrix number, the storage block number and the bad block rate designated by the bad block simulation configuration parameter according to the field.
Optionally, the apparatus further comprises:
The command verification module is used for verifying the bad block simulation configuration command;
the parameter loading module is used for loading the bad block simulation configuration parameters into the bad block scanning program under the condition that the bad block simulation configuration command is a legal command;
and the error message return module is used for returning a command error message when the bad block simulation configuration command is not a legal command.
Optionally, the virtual flash generating module includes:
The flash memory structure determining submodule is used for determining the flash memory structure of the virtual flash memory to be generated according to the bad block simulation configuration parameters;
and the virtual flash memory generation sub-module is used for generating the corresponding virtual flash memory according to the flash memory structure.
Optionally, the first bad block determining module includes:
the storage block detection sub-module is used for traversing each storage block in the virtual flash memory according to the address growth sequence;
a condition judgment sub-module, configured to determine, for each of the storage blocks, whether the storage block satisfies the bad block condition;
And the first bad block designating submodule is used for designating the storage block as the first bad block under the condition that the storage block meets the bad block condition.
Optionally, the expression corresponding to the preset bad block condition is:
rand ()% (1/bad block rate) = 0
Wherein a 1/bad block rate represents the number of said memory blocks required for the presence of at least one said bad block, and rand () represents a random number.
Optionally, the first bad block designating submodule includes:
The setting program running sub-module is used for running a bad block setting program;
and the bad block setting sub-module is used for setting the storage block into the first bad block in the bitmap through the bad block setting program.
Optionally, the apparatus further comprises:
The first information recording sub-module is used for recording the storage block number, the functional unit number, the chip enabling unit number and the channel number corresponding to the first bad block in the virtual flash memory;
and the second information recording sub-module is used for recording the bit number, the byte number and the byte position corresponding to the first bad block in the bitmap.
Optionally, the second bad block determining module includes:
the scanning program running sub-module is used for running the bad block scanning program;
and the storage block scanning sub-module is used for scanning each storage block in the virtual flash memory through the bad block scanning program to obtain a plurality of second bad blocks.
Optionally, the storage block scanning submodule includes:
The instruction sending sub-module is used for sending corresponding instructions to each storage block in the virtual flash memory through the bad block scanning program;
And the second bad block determining submodule is used for determining that the storage block is the second bad block when the response message returned by the storage block is an abnormal message.
Optionally, the apparatus further comprises:
the third information recording sub-module is used for recording the corresponding storage block number, the functional unit number, the chip enabling unit number and the channel number of the second bad block in the virtual flash memory;
And the fourth information recording sub-module is used for recording the bit number, the byte number and the byte position corresponding to the second bad block in the bitmap.
Optionally, the program verification module includes:
the recording information reading sub-module is used for reading the recording information corresponding to each first bad block and each second bad block according to each first bad block and each second bad block;
The identification determination submodule is used for determining that the second bad block is correctly identified when the record information corresponding to the first bad block is matched with the record information corresponding to the second bad block;
the verification passing sub-module is used for passing the verification of the bad block management program under the condition that each second bad block is identified to be correct;
and the verification lost prodigal module is used for failing the verification of the bad block management program under the condition that a bad block which is not matched with the first bad blocks exists in the second bad blocks.
A third aspect of an embodiment of the application provides a computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method according to the first aspect of the application.
A fourth aspect of the embodiments of the present application provides a readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method according to the first aspect of the present application.
A fifth aspect of the embodiments of the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method according to the first aspect of the present application when the computer program is executed by the processor.
By adopting the bad block management program verification method provided by the application, a bad block simulation configuration command is received; analyzing the bad block simulation configuration command to obtain a bad block simulation configuration parameter corresponding to the bad block simulation configuration command; generating a corresponding virtual flash memory according to the bad block simulation configuration parameters; designating a plurality of first bad blocks in the virtual flash memory according to preset bad block conditions; performing bad block detection on the virtual flash memory through a bad block scanning program to obtain a plurality of second bad blocks; and verifying the bad block management program by comparing the plurality of first bad blocks with the plurality of second bad blocks.
According to the application, a bad block simulation configuration command is received through a simulation system, further a bad block simulation configuration parameter is obtained, a corresponding virtual flash memory is generated, the virtual flash memory is a flash memory simulated by a simulation program and is independent of hardware, the structure of the flash memory can be flexibly adjusted, a plurality of first bad blocks are appointed in the virtual flash memory according to preset bad block conditions, the virtual flash memory is scanned through a bad block management program to obtain a plurality of second bad blocks, verification of the bad block management program is completed by comparing the first bad blocks with the second bad blocks, and verification of compatibility and reliability of the bad block management program on flash memories with various structures can be realized by the verification mode, and a staff is not required to manually verify the scanning result of the bad block management program, so that verification efficiency and test efficiency of the bad block management program in firmware development are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a bad block manager verification method according to an embodiment of the present application;
FIG. 2 is a block diagram illustrating a bad block simulation flow according to an embodiment of the present application;
FIG. 3 is a bitmap storage structure in single block format according to an embodiment of the present application;
FIG. 4 is a diagram illustrating a ulti block format bitmap storage structure according to one embodiment of the present application;
FIG. 5 is a schematic diagram of a bad block manager verification device according to an embodiment of the present application;
fig. 6 is a schematic diagram of an electronic device according to an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
For convenience of understanding, first, terms appearing in the embodiments of the present application will be explained in detail:
SSD (Solid STATE DRIVE): solid state disk
Flash (Flash Memory) flash memory, a type of non-volatile memory
NOR Flash (NOT OR Flash): nonvolatile memory
NAND FLASH (NOT AND Flash) nonvolatile memory
Channel: SSD master and nand communication channel with independent buses
CE (Chip enable) chip enable, which means that the master control selects a certain NAND flash memory to perform read-write operation
LUN (Logical Unit Number): functional unit
Plane: each NAND flash memory chip is composed of several planes, each Plane is composed of a plurality of blocks
Block, each NAND flash memory chip is composed of thousands of blocks
PBA (Physics Block Address): physical address, i.e. physical address stored in NAND
Bad Block, which is called Bad Block, in which 1 or more bits contained in one Block are Bad
Bad block rate: the proportion of bad blocks to all blocks is bad block rate
Bitmap: bitmap, data structure
The rear end: module for communicating with flash memory
Single Block: all blocks with the same Block number in a solid state disk are collectively called Single Block
MultiBlock-on the basis of Single Block, several blocks of one Multiplane operation (a command sent to several planes in one LUN) are called MultiBlock
Referring to fig. 1, fig. 1 is a flowchart of a bad block manager verification method according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
S11: and receiving a bad block simulation configuration command.
In this embodiment, the bad block emulation configuration command is used to instruct the main control test program to start emulation test, where the bad block emulation configuration command includes various parameters in the virtual flash memory, and according to the parameters included in the command, the corresponding virtual flash memory can be emulated, so as to start to detect compatibility and reliability of the bad block management program, and the bad block refers to a storage area or sector in the data storage device (such as a hard disk drive, a flash memory drive, an optical disk, etc.), which cannot be used for storing and retrieving data due to physical damage or logic error. Bad blocks may be caused by a variety of reasons including, but not limited to, hardware failures, memory problems, operating system problems, input output subsystem problems, or defects in the storage medium itself. In hard disk drives, bad blocks may appear as physical bad blocks due to physical damage (e.g., media damage) or logical bad blocks due to logical errors (e.g., index errors). Bad blocks may also exist in NAND flash because the flash area cannot be erased. In NAND flash memory, it is bad that 1 or more bits contained in one block are bad, which is called a bad block. These bad blocks may exist at the factory or may be worn out during use due to prolonged use and erase operations.
In this embodiment, referring to fig. 2, fig. 2 is a block simulation flow chart according to an embodiment of the present application, and as shown in fig. 2, when a worker needs to test a block management program, a block simulation configuration command is sent to an SSD main control test program, and the SSD main control test program receives the block simulation configuration command.
In this embodiment, the SSD master control test program may simulate a virtual flash memory by using parameters included in the bad block emulation configuration command, the flash memory structure of the simulated flash memory is the same as the structure specified in the bad block emulation configuration command, and the SSD master control test program may call the bad block management program to scan the virtual flash memory.
S12: and analyzing the bad block simulation configuration command to obtain a bad block simulation configuration parameter corresponding to the bad block simulation configuration command.
In this embodiment, the simulation configuration parameters include the channel number, lun number, plane number, block number and bad block rate of the virtual flash memory. The channel number is the number of channels contained in the virtual flash memory, the lun number is the number of functional units contained in the virtual flash memory, the plane number is the number of storage matrixes contained in the virtual flash memory, the block number is the number of storage blocks contained in the virtual flash memory, and the bad block rate is the probability of bad blocks in the virtual flash memory.
In this embodiment, the SSD master control test program analyzes fields in the bad block simulation configuration command one by one through a serial port command analysis module, so as to obtain simulation configuration parameters corresponding to the bad block simulation configuration command, where the serial port command analysis module is a module dedicated to analyzing commands sent externally, and can analyze command language into parameters that can be read by the SSD master control test program.
In this embodiment, the specific step of analyzing the bad block simulation configuration command to obtain the bad block simulation configuration parameter corresponding to the bad block simulation configuration command includes:
s12-1: and reading each field of the bad block emulation configuration command in turn.
In this embodiment, when the bad block emulation configuration command is parsed, each field of the bad block emulation configuration command is read in sequence, and each field in the bad block emulation configuration command has a corresponding meaning, and each parameter of the flash memory to be emulated is identified.
S12-2: and determining the number of channels, the number of chip enabling units, the number of functional units, the number of storage matrixes, the number of storage blocks and the bad block rate designated by the bad block simulation configuration parameters according to the fields.
In this embodiment, the number of channels, the number of chip enable units, the number of functional units, the number of memory matrices, the number of memory blocks, and the bad block rate specified in the bad block emulation configuration parameters are determined according to the fields in the bad block emulation configuration command.
In this embodiment, the method further includes:
S12-3: and verifying the bad block simulation configuration command.
In this embodiment, after the SSD master control test program receives the bad block emulation configuration command, the bad block emulation configuration command is verified.
In this embodiment, an identifier for verification is added to the command, which is generally included in the beginning field of the command, and the field including the verification identifier is parsed to obtain the corresponding verification identifier. Before the command is transmitted, the transmitting command and the receiving command party negotiate the verification identification in advance. When the analyzed verification mark is the pre-negotiated verification mark, determining that the bad block simulation configuration command is a legal command, and when the analyzed verification mark is not the pre-negotiated verification mark, determining that the bad block simulation configuration command is not the legal command.
S12-4: and under the condition that the bad block simulation configuration command is a legal command, loading the bad block simulation configuration parameter into the bad block scanning program.
In this embodiment, the bad block scanning program is a part of a bad block management program, and is configured to scan the storage blocks of the storage device, so as to determine which storage blocks in the storage device are bad blocks.
In this embodiment, when it is detected that the bad block emulation command is a legal command, the bad block emulation configuration parameters are loaded into the bad block scanning program.
S12-5: and returning a command error message in the case that the bad block emulation configuration command is not a legal command.
In this embodiment, the command error message is used to alert the command sender that the previously issued command is erroneous and cannot be resolved.
In this embodiment, when the bad block emulation configuration command is not a legal command, the SSD master control test program generates a command error message, sends the command error message to the sender of the command, prompts the command that the command is wrong, and needs to resend the command.
S13: and generating a corresponding virtual flash memory according to the bad block simulation configuration parameters.
In this embodiment, the virtual flash memory is a virtual storage device generated by the SSD master control test program according to the bad block emulation configuration parameters, and the structure thereof follows the structure specified in the bad block emulation configuration parameters.
In this embodiment, after the bad block simulation configuration parameters are determined, a corresponding virtual flash memory is generated according to the bad block simulation configuration parameters.
In this embodiment, the generating the corresponding virtual flash according to the bad block emulation configuration parameter includes:
S13-1: and determining the flash memory structure of the virtual flash memory to be generated according to the bad block simulation configuration parameters.
In this embodiment, the flash memory structure is a structure inside the flash memory.
In this embodiment, according to the bad block emulation configuration parameters, the flash memory structure of the virtual flash memory to be generated is determined.
S13-2: and generating the corresponding virtual flash memory according to the flash memory structure.
In this embodiment, after determining the corresponding flash memory structure, a corresponding virtual flash memory is generated, when generating the virtual flash memory, a corresponding storage space is applied in a computer running the SSD master control test program, addresses corresponding to each region are specified in the storage space according to the flash memory structure of the virtual flash memory, and then the internal structure of the whole flash memory is simulated, so as to generate the corresponding virtual flash memory.
The bad block management mode designed by the SSD main control manufacturer needs to be compatible with different hard disk sizes (namely needs to be compatible with different channel numbers and chip enabling unit numbers), meanwhile needs to be compatible with different flash memory models (namely needs to be compatible with different functional unit numbers, storage matrix numbers and storage block numbers), so that the structures of corresponding bad block tables are different, and meanwhile, when a storage structure needing to adjust a bad block table map (bitmap) is met, for example, the storage structure of single block is required to be changed into a storage structure of multi-block, the storage matrix is added to the next layer of the channel due to the storage structure type of the multi-block, so that the bad block management program is adjusted to be larger.
Referring to fig. 3, fig. 3 is a bitmap memory structure in single block format according to an embodiment of the present application, as shown in fig. 3, a memory block in the figure sequentially includes two functional units (lun 0, lun 1), 8 functional units (ce 0-ce 7), and 1 channel (ch 0).
Referring to fig. 4, fig. 4 is a bitmap memory structure in ulti block format according to an embodiment of the present application, as shown in fig. 4, a memory block in the figure includes 1 channel (ch 0), 8 chip enable units (ce 0-ce 7), two functional units (lun 0, lun 1), each channel includes 8 memory matrices (pl), LSB is a start address, and MSB is a stop address.
As can be seen from fig. 3 and 4, the memory structures according to both are greatly different, and since the NAND type is stored in the 6-plane type, but 8-bit alignment is required when designing the memory structure, two-bit default complement 0 is required, and in the case of 4-plane, only tight alignment is required, the structures are also greatly different due to the different types. Because the SSD needs to be compatible with various storage structure types, the compatibility of the bad block management program also needs to be satisfied, and various different conditions are covered when the bad block management program is tested, the virtual flash memory is simulated through the SSD main control test program, so that the test coverage of the bad block management program to various flash memory structures can be ensured.
S14: and designating a plurality of first bad blocks in the virtual flash memory according to preset bad block conditions.
In this embodiment, the preset bad block condition is a condition that a certain memory block is specified in the virtual flash memory to be a bad block to be satisfied. The first bad block is a bad block specified in the virtual flash by the SSD master test program.
In this embodiment, a bad block condition is preset, the SSD master control test program scans the entire virtual flash memory, performs condition judgment on each storage block, and designates a storage block satisfying the preset bad block condition as a first bad block.
In this embodiment, the specific steps of designating the plurality of first bad blocks in the virtual flash memory according to the preset bad block condition include:
s14-1: traversing each storage block in the virtual flash memory according to the address growth sequence.
In this embodiment, the address (PBA) growth order is an order of addresses of each memory block in the virtual flash memory from small to large.
In this embodiment, when a bad block in the virtual flash memory is specified, each memory block in the virtual flash memory is traversed according to an address growth order, wherein the traversing order is a memory block, a functional unit, a chip enabling unit, and a memory matrix, and the traversing range is 0-maximum.
S14-2: for each of the memory blocks, determining whether the memory block satisfies the bad block condition.
In this embodiment, for each memory block, it is determined whether the memory block satisfies a preset bad block condition.
In this embodiment, the expression corresponding to the preset bad block condition is:
rand ()% (1/bad block rate) = 0 (1)
Wherein a 1/bad block rate represents the number of said memory blocks required for the presence of at least one said bad block, and rand () represents a random number.
In this embodiment, when one memory block is scanned each time, a determination is made as to whether the memory block satisfies the bad block condition in equation 1. The random probability that a memory block is a bad block is also substantially the same as the bad block rate in the formula.
S14-3: and designating the storage block as the first bad block in the case that the storage block satisfies the bad block condition.
In the present embodiment, in the case where a memory block satisfies the above-described bad block condition, the memory block is designated as the first bad block.
In this embodiment, the specific step of designating the storage block as the first bad block includes:
s14-3-1: and running a bad block setting program.
In this embodiment, the bad block setting program is used to set the memory block as a bad block in the bitmap.
In this embodiment, when it is determined that a certain memory block satisfies a bad block condition, the SSD master control test program calls a bad block setting program to set the memory block as a first bad block.
S14-3-2: and setting the storage block as the first bad block in a bitmap through the bad block setting program.
In this embodiment, a bitmap (bitmap) is a storage structure, which is a data structure and is mainly used for storing boolean information. The Bitmap data structure realizes various functions such as collection operation, counting statistics and the like through the operation of the bit. Each bit (bit) of the Bitmap is treated as an independent switch, which can represent either a 0 or a 1. In a computer system, 8 bits constitute one Byte, and the value of one bit can only be 0 or 1. Additionally, bitmaps are also commonly used to represent images, particularly bitmaps (RASTER GRAPHICS) or Bitmap images, which are represented using pixel arrays. In image processing, bitmap is used to acquire image file information, perform operations such as image cutting, rotation, scaling, and the like, and can store an image file in a specified format.
In this embodiment, after the bad block setting program is run, the storage block is set as the first bad block in the bitmap by the bad block setting program, and when setting, a bad block mark is added at the position where the bad block is located, and the specific address of the bad block in the bitmap is recorded.
In this embodiment, when none of the scanned memory blocks satisfies the preset bad block condition, a random number is regenerated and the next cycle is entered to continue scanning each memory block.
In this embodiment, the method further includes:
S14-4: and recording the corresponding storage block number, function unit number, chip enabling unit number and channel number of the first bad block in the virtual flash memory.
In this embodiment, the memory block number is the number of the memory block corresponding to the first bad block, the functional unit number is the number of the functional unit corresponding to the first bad block, the chip enable unit number is the number of the chip enable unit corresponding to the first bad block, and the channel number is the number of the channel corresponding to the first bad block.
In this embodiment, after one memory block is designated as the first bad block, the memory block number, the functional unit number, the chip enable unit number, and the channel number corresponding to the first bad block in the virtual flash memory are recorded.
S14-5: and recording the bit number, the byte number and the byte position corresponding to the first bad block in the bitmap.
In this embodiment, a bit (bit) is the smallest unit of data in a computer, a byte (byte) is a unit of storage in a computer, one byte contains a plurality of bits, and a byte position is a position of the byte in a bitmap.
In this embodiment, the number of bits, the number of bytes, and the byte position (i.e., the number of bits of the bad block in the byte) corresponding to the first bad block in the bitmap are recorded, and the hexadecimal number of the corresponding byte is recorded.
In this embodiment, after the information is recorded, the information may be output to the window through the serial port for printing.
S15: and detecting bad blocks of the virtual flash memory through a bad block scanning program to obtain a plurality of second bad blocks.
In this embodiment, the second bad block is a bad block determined by scanning the virtual flash memory by the bad block scanning program.
In this embodiment, a bad block scanning program is run to detect bad blocks of the created virtual flash memory, the bad block scanning program scans the virtual flash memory according to a preset scanning logic, each storage block is judged, the bad blocks in the storage blocks are determined, and the obtained bad blocks are designated as second bad blocks.
In this embodiment, the specific step of performing bad block detection on the virtual flash memory by using a bad block scanning program to obtain a plurality of second bad blocks includes:
S15-1: and running the bad block scanning program.
In this embodiment, when verifying the bad block management program, a bad block scanning program is run to scan the virtual flash memory. When the virtual flash memory is scanned, each flash memory block is scanned one by one according to the address increasing sequence of each storage block in the virtual flash memory.
S15-2: and scanning each storage block in the virtual flash memory through the bad block scanning program to obtain a plurality of second bad blocks.
In this embodiment, each storage block in the virtual flash memory is scanned by the bad block scanning program, so as to obtain a plurality of second bad blocks.
In this embodiment, after obtaining the plurality of second bad blocks, the number of bits, the number of bytes, and the byte positions of the plurality of second bad blocks are recorded, and the recorded result can be printed out as well.
In this embodiment, the specific step of scanning each storage block in the virtual flash memory by the bad block scanning program to obtain a plurality of second bad blocks includes:
s15-2-1: and sending a corresponding instruction to each storage block in the virtual flash memory through the bad block scanning program.
In this embodiment, when detecting bad blocks in the virtual flash memory, the bad block scanning program sends corresponding instructions to each memory in the virtual flash memory, and the sent instructions are generally read, write, erase and other instructions.
S15-2-2: and when the response message returned by the storage block is an abnormal message, determining that the storage block is the second bad block.
In this embodiment, the response message is a response message returned by the storage block to the sender of the instruction according to the received instruction, for example, a message that the erasure is completed, the writing is successful, etc. The abnormal message is a response message other than the normal response message, such as a write failure, an erase failure, or the like.
In this embodiment, when the response message returned by the storage block is an abnormal message, it is determined that the storage block is a second bad block.
S16: and verifying the bad block management program by comparing the plurality of first bad blocks with the plurality of second bad blocks.
In this embodiment, after obtaining the plurality of first bad blocks and the plurality of second bad blocks, the bad block management program is verified according to the comparison result between the first bad blocks and the second bad blocks, and if the bad block numbers recorded by the plurality of first bad blocks and the position information of the bad blocks in the bitmap are the same as the bad block numbers recorded by the plurality of second bad blocks and the position information of the bad blocks in the bitmap, it is determined that the bad block management program passes the verification, and the compatibility and the reliability of the bad block management program pass the verification. If the corresponding data of the first bad block record is different from the corresponding data of the second bad block record, determining that the bad block management program is not verified.
In this embodiment, the specific step of verifying the bad block management program by comparing a plurality of the first bad blocks with a plurality of the second bad blocks includes:
S16-1: and reading record information corresponding to the first bad blocks and the second bad blocks according to each first bad block and each second bad block.
In this embodiment, the recording information is related information of a bad block recorded when the first bad block and the second bad block are specified.
In this embodiment, when verifying the result, the record information of the first bad block and the second bad block is read for each first bad block and each second bad block.
In this embodiment, the related information of the first bad block and the second bad block is recorded when the first bad block and the second bad block are identified before, at this time, the previous record is read, the storage block number of the first bad block specified by the SSD master control test program is determined, the corresponding position of the first bad block in the bitmap, the storage block number of the second bad block record is determined, and the corresponding position of the second bad block in the bitmap.
S16-2: and when the record information corresponding to the first bad block and the second bad block are matched, determining that the second bad block is correctly identified.
In this embodiment, when the record information corresponding to the first bad block and the second bad block are matched, it is determined that the second bad block is correctly identified, and the bad block management program correctly records the information of the second bad block.
S16-3: and in the case that each second bad block is identified correctly, passing the verification of the bad block management program.
In this embodiment, when all the second bad blocks are identified correctly, it is described that the bad block management program correctly identifies and records each bad block in the virtual flash memory, and at this time, the verification of the bad block management program is passed.
S16-4: in the case that there is a bad block that does not match the plurality of the first bad blocks among the plurality of the second bad blocks, the bad block manager fails the verification.
In this embodiment, in the case that a plurality of bad blocks exist in a plurality of second bad blocks, which are not matched with a plurality of first bad blocks, it is indicated that an error occurs in the bad block management program during the scanning or recording process, and each bad block in the virtual flash memory is not accurately identified or recorded, and at this time, it is determined that verification of the bad block management program fails.
In this embodiment, parameters such as a channel, an enabling chip unit, a functional unit, a storage block, and a storage matrix number may be flexibly modified by inputting a serial port to flexibly modify a structure of the virtual flash memory, and a bad block rate of the virtual flash memory may be flexibly specified, so as to simulate bad blocks of different types of flash memories by software, thereby facilitating verification of compatibility and reliability of a bad block management program in firmware development.
In another embodiment of the present application, multiple groups of bad block simulation configuration parameters may be set at one time, and the multiple groups of bad block simulation configuration parameters may be input into an SSD master control test program at one time, corresponding virtual flash memories are sequentially generated by the master control test program, and verification is performed on the multiple virtual flash memories by a bad block management program, so as to obtain verification results of the bad block management program on the multiple virtual flash memories, statistics is performed on the verification results, so that accuracy of identifying and recording bad blocks by the bad block management program is obtained, and corresponding print files are generated for viewing by staff.
In this embodiment, by setting multiple groups of simulation configuration parameters at one time, the bad block management program is enabled to verify on multiple virtual flash memories, and the accuracy of identifying and recording bad blocks by the bad block management program is counted, so that development and testing personnel can conveniently grasp the compatibility and reliability of the bad block management program on the whole, and timely modifying the bad block management program improves the testing efficiency of the firmware-initiated bad block management program.
Based on the same inventive concept, an embodiment of the present application provides a bad block management program verification device. Referring to fig. 5, fig. 5 is a schematic diagram of a bad block management program verification device 500 according to an embodiment of the application. As shown in fig. 5, the apparatus includes:
A command receiving module 501, configured to receive a bad block emulation configuration command;
the simulation configuration parameter obtaining module 502 is configured to parse the bad block simulation configuration command to obtain a bad block simulation configuration parameter corresponding to the bad block simulation configuration command;
A virtual flash generating module 503, configured to generate a corresponding virtual flash according to the bad block emulation configuration parameter;
a first bad block determining module 504, configured to designate a plurality of first bad blocks in the virtual flash memory according to a preset bad block condition;
The second bad block determining module 505 is configured to perform bad block detection on the virtual flash memory through a bad block scanning program, so as to obtain a plurality of second bad blocks;
program verification module 506 is configured to verify the bad block management program by comparing the plurality of first bad blocks with the plurality of second bad blocks.
Optionally, the simulation configuration parameter obtaining module includes:
the field reading sub-module is used for sequentially reading each field of the bad block simulation configuration command;
and the parameter determination submodule is used for determining the channel number, the chip enabling unit number, the functional unit number, the storage matrix number, the storage block number and the bad block rate designated by the bad block simulation configuration parameter according to the field.
Optionally, the apparatus further comprises:
The command verification module is used for verifying the bad block simulation configuration command;
the parameter loading module is used for loading the bad block simulation configuration parameters into the bad block scanning program under the condition that the bad block simulation configuration command is a legal command;
and the error message return module is used for returning a command error message when the bad block simulation configuration command is not a legal command.
Optionally, the virtual flash generating module includes:
The flash memory structure determining submodule is used for determining the flash memory structure of the virtual flash memory to be generated according to the bad block simulation configuration parameters;
and the virtual flash memory generation sub-module is used for generating the corresponding virtual flash memory according to the flash memory structure.
Optionally, the first bad block determining module includes:
the storage block detection sub-module is used for traversing each storage block in the virtual flash memory according to the address growth sequence;
a condition judgment sub-module, configured to determine, for each of the storage blocks, whether the storage block satisfies the bad block condition;
And the first bad block designating submodule is used for designating the storage block as the first bad block under the condition that the storage block meets the bad block condition.
Optionally, the expression corresponding to the preset bad block condition is:
rand ()% (1/bad block rate) = 0
Wherein a 1/bad block rate represents the number of said memory blocks required for the presence of at least one said bad block, and rand () represents a random number.
Optionally, the first bad block designating submodule includes:
The setting program running sub-module is used for running a bad block setting program;
and the bad block setting sub-module is used for setting the storage block into the first bad block in the bitmap through the bad block setting program.
Optionally, the apparatus further comprises:
The first information recording sub-module is used for recording the storage block number, the functional unit number, the chip enabling unit number and the channel number corresponding to the first bad block in the virtual flash memory;
and the second information recording sub-module is used for recording the bit number, the byte number and the byte position corresponding to the first bad block in the bitmap.
Optionally, the second bad block determining module includes:
the scanning program running sub-module is used for running the bad block scanning program;
and the storage block scanning sub-module is used for scanning each storage block in the virtual flash memory through the bad block scanning program to obtain a plurality of second bad blocks.
Optionally, the storage block scanning submodule includes:
The instruction sending sub-module is used for sending corresponding instructions to each storage block in the virtual flash memory through the bad block scanning program;
And the second bad block determining submodule is used for determining that the storage block is the second bad block when the response message returned by the storage block is an abnormal message.
Optionally, the apparatus further comprises:
the third information recording sub-module is used for recording the corresponding storage block number, the functional unit number, the chip enabling unit number and the channel number of the second bad block in the virtual flash memory;
And the fourth information recording sub-module is used for recording the bit number, the byte number and the byte position corresponding to the second bad block in the bitmap.
Optionally, the program verification module includes:
the recording information reading sub-module is used for reading the recording information corresponding to each first bad block and each second bad block according to each first bad block and each second bad block;
The identification determination submodule is used for determining that the second bad block is correctly identified when the record information corresponding to the first bad block is matched with the record information corresponding to the second bad block;
the verification passing sub-module is used for passing the verification of the bad block management program under the condition that each second bad block is identified to be correct;
and the verification lost prodigal module is used for failing the verification of the bad block management program under the condition that a bad block which is not matched with the first bad blocks exists in the second bad blocks.
Based on the same inventive concept, another embodiment of the present application provides a readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the bad block management program verification method according to any of the above embodiments of the present application.
Based on the same inventive concept, another embodiment of the present application provides an electronic device, and referring to fig. 6, fig. 6 is a schematic diagram of an electronic device according to an embodiment of the present application, including a memory 602, a processor 601, and a computer program stored in the memory and capable of running on the processor, where the processor executes the steps in the bad block management program verification method according to any one of the foregoing embodiments of the present application.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the application may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.
The bad block management program verification method, product and storage medium provided by the application are described in detail, and specific examples are applied to illustrate the principle and implementation of the application, and the description of the above examples is only used for helping to understand the method and core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (14)
1. A bad block management program verification method, the method comprising:
receiving a bad block simulation configuration command;
Analyzing the bad block simulation configuration command to obtain a bad block simulation configuration parameter corresponding to the bad block simulation configuration command;
Generating a corresponding virtual flash memory according to the bad block simulation configuration parameters;
Designating a plurality of first bad blocks in the virtual flash memory according to preset bad block conditions;
Performing bad block detection on the virtual flash memory through a bad block scanning program to obtain a plurality of second bad blocks;
And verifying the bad block management program by comparing the plurality of first bad blocks with the plurality of second bad blocks.
2. The method according to claim 1, wherein the parsing the bad block emulation configuration command to obtain bad block emulation configuration parameters corresponding to the bad block emulation configuration command comprises:
reading each field of the bad block emulation configuration command in sequence;
And determining the number of channels, the number of chip enabling units, the number of functional units, the number of storage matrixes, the number of storage blocks and the bad block rate designated by the bad block simulation configuration parameters according to the fields.
3. The method according to claim 2, wherein the method further comprises:
Verifying the bad block simulation configuration command;
under the condition that the bad block simulation configuration command is a legal command, loading the bad block simulation configuration parameters into the bad block scanning program;
and returning a command error message in the case that the bad block emulation configuration command is not a legal command.
4. The method of claim 1, wherein generating the corresponding virtual flash memory according to the bad block emulation configuration parameters comprises:
Determining a flash memory structure of the virtual flash memory to be generated according to the bad block simulation configuration parameters;
and generating the corresponding virtual flash memory according to the flash memory structure.
5. The method of claim 1, wherein the designating the first bad blocks in the virtual flash memory according to the preset bad block condition comprises:
traversing each storage block in the virtual flash memory according to the address increasing sequence;
determining, for each of the memory blocks, whether the memory block satisfies the bad block condition;
And designating the storage block as the first bad block in the case that the storage block satisfies the bad block condition.
6. The method of claim 5, wherein the preset bad block condition corresponds to an expression:
rand ()% (1/bad block rate) = 0
Wherein a 1/bad block rate represents the number of said memory blocks required for the presence of at least one said bad block, and rand () represents a random number.
7. The method of claim 5, wherein the designating the memory block as the first bad block comprises:
Running a bad block setting program;
And setting the storage block as the first bad block in a bitmap through the bad block setting program.
8. The method of claim 7, wherein the method further comprises:
recording a storage block number, a functional unit number, a chip enabling unit number and a channel number corresponding to the first bad block in the virtual flash memory;
And recording the bit number, the byte number and the byte position corresponding to the first bad block in the bitmap.
9. The method of claim 1, wherein performing bad block detection on the virtual flash memory by a bad block scanning procedure to obtain a plurality of second bad blocks comprises:
Running the bad block scanning program;
And scanning each storage block in the virtual flash memory through the bad block scanning program to obtain a plurality of second bad blocks.
10. The method of claim 9, wherein scanning each memory block in the virtual flash memory by the bad block scanning program to obtain a plurality of the second bad blocks, comprises:
transmitting a corresponding instruction to each storage block in the virtual flash memory through the bad block scanning program;
And when the response message returned by the storage block is an abnormal message, determining that the storage block is the second bad block.
11. The method according to claim 9, wherein the method further comprises:
recording a storage block number, a functional unit number, a chip enabling unit number and a channel number corresponding to the second bad block in the virtual flash memory;
and recording the bit number, the byte number and the byte position corresponding to the second bad block in the bitmap.
12. The method of claim 1, wherein validating the bad block manager by comparing a plurality of the first bad blocks with a plurality of the second bad blocks comprises:
Reading record information corresponding to each first bad block and each second bad block according to each first bad block and each second bad block;
when the record information corresponding to the first bad block and the second bad block are matched, determining that the second bad block is correctly identified;
passing verification of the bad block manager if each of the second bad blocks is identified as correct;
In the case that there is a bad block that does not match the plurality of the first bad blocks among the plurality of the second bad blocks, the bad block manager fails the verification.
13. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method as claimed in any one of claims 1 to 12.
14. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method according to any of claims 1 to 12.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107679266A (en) * | 2017-08-22 | 2018-02-09 | 珠海泓芯科技有限公司 | The emulation mode and simulator of flash memory circuit |
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| CN112083873B (en) * | 2019-06-14 | 2023-06-20 | 北京忆芯科技有限公司 | Method and device for intelligently identifying unreliable blocks of non-volatile storage media |
| CN117493070A (en) * | 2023-10-10 | 2024-02-02 | 苏州元脑智能科技有限公司 | Method and system for processing storage bad blocks |
| CN117577163A (en) * | 2023-11-20 | 2024-02-20 | 成都芯忆联信息技术有限公司 | SSD bad block detection method, SSD bad block detection device, computer equipment and storage medium |
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| CN112395146A (en) * | 2020-11-27 | 2021-02-23 | 深圳忆联信息系统有限公司 | SSD firmware simulation verification method, system, computer equipment and storage medium |
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