CN1181703C - Switching device and method thereof - Google Patents

Abstract

The present invention relates to an exchanging device which transmits data packets from an input port to a specified output port. The effective load of the data packets is stored in a storage device; the exchanging device is provided with exchanging equipment which has more switch output than switch input, and the exchanging equipment is sequentially switched between one piece of switch input and a plurality of pieces of switch output; the effective load is stored in the exchanging equipment. Besides, the present invention also relates to a storage method which uses the exchanging equipment to store continuously and sequentially store the effective load, exchanging equipment which comprises a plurality of exchanging devices and a modular system which uses the exchanging devices as scalable proportion.

Description

Switching device and method thereof

technical field

The invention relates to a switching arrangement for fixed length data packets, especially ATM packets. More specifically, it concerns a switching device with several input ports and several output ports, determined to transfer incoming packets to one or more designated output ports according to their headers. Further, the invention relates to a method for transferring fixed length packets from several input ports to several output ports, especially for ATM packets. The invention also relates to a switching arrangement comprising several switching devices.

Background technique

The rapid exchange of information, i.e. samples of analogue signals or mixed alphanumeric data, is an important task of communication networks. Network nodes are often responsible for delays in transmission, where lines or transmission links from different directions are interconnected to exchange information between each other. Increased delays or even loss of information are often encountered if a lot of traffic is concentrated in one node, especially if most of the traffic goes through only some of the links. It is therefore ideal to have nodes that allow fast route finding and are at least partially non-blocking.

In EP312628 a switching device is described for interconnecting a plurality of incoming and outgoing transmission links of a communication network, or for exchanging data between incoming and outgoing computer and workstation connection links. Known packet formats are further described.

An overview of current switching technology is given at the Internet page WWW.Zurich.ibm.com/Technology/ATM/.SWOCPWP, where the introduction to the PRIIMA chip is set forth. Another source of information on this topic is the article "A Flexible Buffer Shared Switch for ATM at Gbit/s Rates" by W.E.Denzel, A.P.J.Engbersen, I.Iliadis on Computer Networks and ISDN Systems (0169-7552194) ", Elsevier Science B.V., Vol. 27, No. 4, pp. 611-624.

The PRIZMA chip has 16 input ports and 16 output ports providing a port rate of 300-400Mbit/s. The switching principle is to first send the input packets through a completely parallel input/output routing tree, and then queue the outgoing packets in an output buffer. Otherwise the chip applies a separation of data (payload) and control (header) streams. Only the payload is stored in the dynamically shared output buffer memory. Head-of-line queuing is avoided with this structure. The PRIZMA chip has a scalable structure, thus providing various expansion capabilities, whereby the port rate, the number of ports and the data throughput can be increased. These extensions can be realized based on the modular application PRIZMA. Likewise single-level or multi-level switching fabrics can be constructed in a modular manner.

The PRIZMA chip is particularly suitable for broadband telecommunications based on ATM, or Asynchronous Transfer Mode. However, this concept is not limited to ATM-oriented fabric environments. ATM is based on short, fixed-length packets, often called cells, which are assumed to be used as the integrated switching and delivery standard in the future public Broadband Integrated Services Digital Network (BISON). PRIZMA applies high-level parallel theory to the topology and queuing configurations used to resolve contention. The routing function is done in a distributed manner at the hardware level and is known as self-discovery routing. ATM packets are divided into several packet types, in particular those with different payload lengths, while the PRIZMA chip is dedicated to handling packets with payloads of up to 64 bytes. However, packets with payloads of 12, 16, 32 or 48 bytes are usually also transmitted.

The typical size of the shared storage part in PRIZMA includes 128 storage units, and the unit length is 64 bytes, which is used to store up to 128 packets, and has nothing to do with the length of the packets. When the PRIZMA chips are applied in rate-extended mode, where 4 chips operate in parallel and each chip receives a quarter of the payload, smaller payloads are automatically generated, which means that a considerable amount of memory is not used .

Furthermore, the writing and reading process of payloads in the memory area is synchronous, which means that packets arriving asynchronously must wait until the write pointer common to all memory cells delivers the first byte for all memory cells. This results in an additional delay of up to 63 clock cycles.

Contents of the invention

It is therefore an object of the present invention to provide a switching arrangement for transferring incoming fixed length data packets from a plurality of input ports to a plurality of output ports which provides a very high packet throughput.

The arrangement according to independent claim 1 shows the advantage that the switch provides a relatively high performance and at the same time employs a structural composition of only relatively small dimensions, in particular input devices with a reduced number of outputs, more particularly with a ratio Storage devices have fewer outputs than storage cells.

The dependent claims of claim 1 present different measures which indicate more advantageous enhancements and improvements to the invention claimed in claim 1 .

The arrangement according to claim 2 demonstrates the advantage that, in the case of packet types with the smallest possible size, a minimum of storage space is wasted, while still retaining the possibility of storing very large packet types. The switching device can thus be programmed which packet type to handle, thereby providing optimal storage usage for the different packet types through this.

When the number of storage units connected to a switching device is selected so that the sum of the sizes of their storage units is sufficient to store the entire payload of a packet of a predetermined maximum size packet type to be processed by the switching means, at any In the case of the packet type, the storage unit connected to the above-mentioned switching device is sufficient to completely store a packet payload. Therefore only one switching device with a dedicated memory location needs to be addressed for storing a packet payload. This sizing rule is also beneficial because when a memory device is divided into groups of memory cells, each group can be written to independently of the other.

The fact that only one set of output control devices is assigned to a single memory bank containing multiple memory cells is advantageous because it can be kept very small by taking advantage of the fact that several output ports want to access the same memory bank at the same time. Small amount of hardware and software. The probability of simultaneous access to the same memory bank is low because packet bursts, ie consecutive packets arriving at the same output port, usually occur during average traffic. Due to bursting, usually the entire bank contains data arriving at the same output port. The second reason why performance degradation is less likely is the fact that not all output ports are busy at a point in time and the banks are usually not all filled, and in the end there are far more memory banks than output ports.

Providing a separate output queue for each output port simplifies the method of routing stored payloads to their destinations. Also this is a very simple way of handling multicast packets.

A switch control device provides convenience, because with such a device the information in which memory location the payload is stored can be easily retrieved, and further this device can be programmed for different packet types, corresponding packet factors.

A translation device for generating data patterns, in particular bitmaps for each packet, represents a facility for easily extracting routing information from packet headers. Additionally, this is noted as valid for multicast packets.

The routing information in the packet header is best utilized by receiving the specified data pattern from the queue control device and using it as an enable function to store the individual payload addresses in the output queue. The payload address is defined here as a combination of the bank address belonging to the bank receiving the respective payload and the memory unit number in which the payload is stored. In the case where the payload occupies several consecutive memory locations, the memory location number may be selected as, for example, the memory location containing the first byte of the payload. This in turn provides an efficient means for quickly and easily delivering payloads to their destination.

Since the storage process of payloads, especially with small numbers of bytes, is very fast, backpressure can be better optimized when the information about which memory cell stores which payload is processed in parallel for several input ports. avoid. Backpressure can arise, for example, when the write processing of the payload is faster than the management of the piece of information about which storage unit stores which payload, because the storage device will be completely filled and no more input can be stored Packet payload.

When the counting device counts the number of read transactions per multicast packet for each memory group, the payload need only be stored once and the risk of losing packets or not providing all output ports with their copies of multicast packets is reduced. Small. Furthermore, if only one counting device is provided for each memory group, this is still sufficient to maintain the above-mentioned low risk for multicast packets and at the same time reduce the necessary number of counters for the entire switching arrangement.

In addition to its enabling function, the use of data patterns for counting purposes is a very efficient application of information, which reduces the use of hardware and software.

When the counting device is split into two counters, the implemented counter only needs to count in one direction, which is less complicated. In addition, the two counters can operate simultaneously and independently of each other, which reduces hardware complexity.

Bookkeeping of free storage group addresses provides very fast access to non-occupied storage group addresses and reduces the likelihood that storage group addresses will be reused before their entire contents have been read.

Another object of the present invention is to provide a method for transferring an input fixed-length data packet from a plurality of input ports to a plurality of output ports by storing the packet payload in a storage device, using a switching device in consecutive storage units exchange between.

A further object of the present invention is to provide a switching arrangement comprising several switching means as described above. Such a device provides better performance, such as higher port speed, higher throughput or more input and output ports.

Switching devices may be built from identical switching devices, more specifically by The same printed circuit boards (PCB's) build.

When each switching device is combined with an arbitration device and one of the above selection devices as a scalable module, product cost can be reduced because the same module can be used as a single switching device or in In a switching device with several switching devices.

A master/slave configuration as claimed in claim 32 is advantageous because with it a higher throughput can be achieved.

In the inventive switching arrangement, the storage units are grouped together by means of a switching device. By doing so, the storage unit can be sized such that a packet payload of a small length fits in one storage unit while a packet with a larger payload length uses several consecutive storage units.

According to one aspect of the present invention, a switching device for transferring incoming fixed-length data packets comprising a destination header and information in the form of payload from a plurality of input ports (101-108) to a plurality of output ports (501-508), comprising an input device (86) for sending said payload of said incoming packet to a storage device (87) comprising a plurality of storage units (6001-6128), and comprising a device for reading said stored payload and sending They are sent to an output device selected from the above-mentioned output ports (501-508), the option is predetermined by the above-mentioned destination header, characterized in that at least one switching device (3401-3432) is provided, and each A switch output (291-294) connected to one of said storage units (6001-6128) is more than said payload from said input device (121-128, 4001-4256, 1301-1332) to a switch input thereto (85), and at least two of said switching outputs (291-294) are dedicated to the same said switching input (85), and said switching devices (3401-3432) are able to switch between said dedicated switching outputs in a predetermined order While switching between (291-294), the above-mentioned useful load is directed to its dedicated switch output (291-294) from the above-mentioned switch input (85).

An embodiment of the invention provides a translation device for translating said header into a data schema containing information about to which said output port (501-508) said incoming packet is to be sent.

According to another aspect of the present invention, a method of sending incoming fixed-length data packets comprising a destination header and information in the form of a payload from a plurality of input ports (101-108) to a plurality of output ports (501-508), including a step of sending said payload of said incoming packet to a storage device (1401-1432) comprising a plurality of storage units (6001-6128), and reading said stored payload and sending them to said The step of selecting one of the output ports (501-508), the selection is predetermined by the above-mentioned destination header, characterized in that the above-mentioned payload is sent from the above-mentioned switch input (85) to the above-mentioned dedicated switch outputs (291-294), while switching in a predetermined sequence between said dedicated switch outputs (291-294), each of which is connected to one of said storage units (6001-6128) included in the switching facility The switch outputs (291-294) are more than the switch inputs (85) where the above-mentioned effective loads arrive there from the above-mentioned input devices (121-128, 4001-4256, 1301-1332), and at least two of the above-mentioned switch outputs (291-294) one dedicated to the same switch input (85).

Description of drawings

Examples of the invention are illustrated in the drawings and the detailed description given below, by way of illustration. It is given below:

Figure 1a: the first part of the functional block diagram of a switch embodiment,

Fig. 1b: the second part of the functional block diagram of a switch embodiment,

Figure 2: An example of a storage group with 4 small size length packet payloads,

Figure 3a: An example of a storage group with two medium-length packet payloads,

Figure 3b: An example of a storage group with a large length packet payload,

Figure 4: A port expansion unit with 4 switching units,

Figure 5: A port expansion unit with 4 printed circuit boards,

Figure 6: A port expansion device with a port-mapping switch device,

Figure 7: A rate extension device.

Detailed description of specific embodiments

The invention is illustrated in the following various examples. The number of devices and ports chosen is for illustrative example only and can be changed without departing from the scope of the invention. For clarity in Figures 1 to 3b many identical parts are arranged side by side, only the first and last representations of these parts are drawn, but all parts are referred to in the description.

The device shown in Figures 1a, b and 2 comprises 8 input ports 101-108 which are connected to 8 input controllers 111-118 which function as translation devices. Each of the aforementioned input controllers 111-118 is connected to a corresponding one of eight subsequent input routers 121-128. Each input router 121-128 is connected to each of the 32 input selectors 1301-1332 via one of the 256 routing connection lines 4001-4256. Input routers 121-128, router connection lines 4001-4256 and input selectors 1301-1332 together form an input device 86. Each of the 32 input selectors is connected via one of the 32 unit selector switches 3401-3432 to a corresponding one of the 32 storage groups 1401-1432. Unit selector switches 3401-3432 function as switching devices. Each of the memory banks 1401-1432 has its assigned bank input controller 1501-1532 as a switch control device and its assigned bank output controller 1601-1632 as a bank output control device. Each group input controller 1501-1532 is connected to each input controller 111-118 via one of eight bidirectional lines 521-528. Each memory bank 1401-1432 includes such a bank of four memory cells 6001-6128 and has four corresponding memory outputs. There are thus 128 memory cells 6001-6128, divided into four groups. Each cell selector switch 3401-3432 has a switch input 85 connected to an input device 86 and has four switch outputs 291,292,293,294, each of which is connected to one of the memory banks 1401-1432 One of the storage units 6001-6128. Storage groups 1401-1432 together form a storage device 87. Each output of each storage group 1401-1432 is connected to each of eight output routers 171-178 which together are defined as output devices. Each of the eight output routers 171-178 is properly connected to one of the eight output controllers 201-208.

Bookkeeping equipment in the form of an address manager 71 includes an address look-up table 72 comprising a memory matrix of 32 rows and 3 columns 78,79,80. The first column 78 contains comparators dedicated to the bank addresses of memory banks 1401-1432. The second column 79 contains a first counter and the third column 80 contains a second counter. The address manager 71 further includes an incrementing section 74 and a decrementing section 73 . The address look-up table 72, incrementing section 74 and decrementing section 73 together form a counting device. Incremental section 74 is connected to all eight input controllers 111-118 and to all eight input routers 121-128. Decrement section 73 also has eight inputs, which are connected to eight output controllers 201-208 and eight output routers 171-178 via eight decrementer input lines 541-548. In the decrement section and output routers 171-178, the eight decrementer input lines 541-548 between the output controllers 201-208 are also connected to each of the 32 group output controllers 1601-1632. The decrementing section 73 and incrementing section 74 are connected to an address look-up table 72 which itself is connected to an address queue 75 having 32 queue positions. Address queue 75 has an output connected to each input controller 111-118. A queue control device in the form of an output queue access manager 18 has eight inputs which are respectively connected to eight input controllers 121-128. The eight inputs are divided into two input groups 281, 282 of four inputs each. Each input group 281, 282 is connected to a group selection switch 19 which has four output lines grouped together as an output group 30. The output queue access manager 18 further includes a switch controller 77 which controls the bank select switch 19 and has eight inputs from the input controllers 111-118. Each of the eight output queues 261-268 has four inputs connected in parallel to four output lines. Each output queue 261-268 is dedicated, linked to one of the output controllers 201-208 via one of eight queue output lines 531-538. The data output of each output controller 201-208 is directly connected to one of the eight output ports 501-508. Each bank output controller 1601-1632 provides a read pointer dedicated to all four memory cells 600-628 in the corresponding memory bank 1401-1432. The storage units 6001-6128 all have the same size, that is, the length is 16 bytes. Packets handled by the device can be of several sizes, known as packet types, i.e. a small packet has a payload length of 12 bytes, a medium packet has a payload length of 32 bytes and a large packet has a payload length of 64 bytes .

As explained in detail below, in applications the device is determined to receive only one type of packet by programming the cell selection switches 3401-3432 to act accordingly. However, the programming can be changed for different applications.

For example, an incoming fixed-length packet, such as an ATM packet, arrives at an input port 111 and is entering a corresponding input controller 121 . A packet contains information consisting of a header and a payload. The header contains destination information as to which output port 501-508 the packet is to be sent to. The destination information is encrypted as a number in the packet header. The corresponding input controller 121 acts as a translation device and thus contains a list of digits and a corresponding list of data patterns, ie bitmaps. The code of the input destination information is compared with the stored code list until a matching code is found. The corresponding bitmap is read from the list and assigned to the received packet. The purpose information is then translated into a dedicated bitmap through this process. The bitmap has 8 bits, one for each output port 501-508. The bits included indicate in binary form whether the respective output port 501-508 should receive the packet. Each logical 1 in the bitmap means that the corresponding output port 501-508 should receive a copy of the packet. The selection of output ports 501-508 is thus determined by this bitmap. As will be explained below, this is a complex method of handling multimodal packets. The specified bitmap is sent to the switch controller 77 of the output queue access manager 18. The payload of the incoming packet is sent to the corresponding incoming router 121 .

The address queue 75 of the address manager assigns each input controller 111-118 the number of a free bank address, ie, the address of a bank 1041-1432 not occupied by undelivered packet payloads. A free bank address is given to each input controller 111-118 by the address queue 75 and simultaneously removed from the queue. In order to achieve high performance, each input controller 111-118 has been given a bank address before the packet arrives.

The receive input controller 111 sends the received storage group address to the corresponding input router 121 and also to the corresponding input group 282 in the output queue access manager 18 .

The reception input controller 111 further sends the designated bitmap to the incrementing section 74 . In the incrementing section 74, the sum of the logic 1s in the received bitmap is calculated and sent to the address look-up table 72. There, the first counter 79 of the corresponding bank address is set to the received value.

When the storage group address has been assigned to the input controller 111-118 before the packet arrives, it is possible to set the corresponding counter to the value of the storage location 6001-6128 already in the storage group 1401-1432, such as 4, An additional step of adding section 74 is therefore required only in the case of multicast packets. This has the advantage that without adding hardware complexity to this waiting bank 1401-1432, the comparison of the counter positions yields an unequal result which prevents bank addresses from being incorrectly reused.

The receiving input router 121 has established a connection to the corresponding input selector 1332 of the storage group 1432 for which it has received the storage group address. The input selector 1332 has automatically switched the input connection to the corresponding memory bank 1432 . For high performance, connections to input selectors 1301-1332 are all established when a packet arrives.

The corresponding bank input controller 1532 controlling the corresponding bank 1432 with the bank address received by the receive input controller 111 receives a signal from the receive input controller 111 indicating that the bank 1432 is to be written.

The bank input controller receiving the memory bank 1432 controls the corresponding cell selector switch 3432 and additionally serves as a write pointer. Since the addressed memory bank 1432 contains four memory locations 6125, 6126, 6127, 6128, it is possible to store four packet payloads of the small length packet type. For the first packet payload to be written, the addressed cell selector switch 3432 is pointed to the first memory cell 6125 and the write pointer is pointed to the first byte. The packet payload is inserted into the first memory location 6125 of the addressed memory bank 1432 while the write pointer is incremented byte by byte. After this process, the cell selector switch 3432 is incremented to the next memory cell 6126 and the write pointer is reset to the first byte to receive the next payload of the next incoming packet. When a payload is written to an addressed memory location 6125, the corresponding bank input controller 1532 sends to the receive input controller 111 the number of the actual memory location 6125 determined by the cell selector switch 3432, where the memory location number is It is further sent to the input group 282 of the output queue access manager 18, from there to the output group 30, and from there to the designated output queues 261-268.

The output queue access manager 18 connects the input groups 281, 282 to the output group 30 one after the other to all the output queues 261-268. This is done by the switch controller 77 which controls the switching process of the group selector switch 19 . The payload address consisting of the received bank number and the received bank address is then written to the output queues 261-268 along with the bitmap received by the switch controller 77. Only certain ones of the output queues 261-268, ie, those with logic 1's in the bitmap, receive payload addresses. The payload address is stored in the output queue 261-268 corresponding to each output port 501-508 that must receive a copy of the incoming packet.

Then using the above-mentioned means, various methods, the payload of a packet is stored in the storage unit 6125, and its destination is determined as follows, that is, the output queue 261-268 assigned to a particular output port 501-508 is in the corresponding output port 501-508 Queues 261-268 contain records for payload addresses.

Addressed bank 1432 remains active until all four memory cells 6125, 6126, 6127, 6128 have been used. This means that the next incoming payload is automatically stored in storage unit 6126, the next in storage unit 6127 and so on. Thus stored payloads do not necessarily have to go to the same output port 501-508. When the cell selector switch 3432 has finished selecting each of the four memory cells 6125, 6126, 6127, 6128 in a memory bank 1432, a new memory bank 1401-1431 is selected from the address queue 75 for to store the following four packet payloads. Stored procedures within a storegroup 1432 are typically completed sequentially. Cell selector switch 3432 is programmed to switch between memory cells 6125, 6126, 6127, 6128 in a predetermined order.

To read a packet payload from a storage unit 6001-6128 and send it to one of the designated output ports 501-508, each output controller 201-208 receives from its corresponding output queue 261-268 The next payload address, which includes the address in the corresponding memory bank 1432 and the number of the corresponding memory location 6125 that stores the next payload for the output port 508. The receive output controller 508 uses the received memory group address to notify the group output controller 1632 of the memory group 1432 containing the memory unit 6125 that it must be ready to send the stored packet payload. The output controller 208 receives the payload address from the output queue 268 in the form of a storage group 1432 and a storage location 6125 within the storage group 1432 . The corresponding output router 178 also receives the payload address from the output controller 208 and establishes a connection between the storage unit 6125 with the corresponding storage unit number and the output controller 208 . The bank output controller 1632 then also provides a read pointer, resets the read pointer to the first byte and simultaneously sends all packets in the store bank 1432 to its store output. As an example in this example, for reading from the storage group 1432, when only one storage unit 6125 is connected to one output controller 208, only the content of the storage unit 6125 is read. However, since only copying is done during the read process, which is called non-destructive read, other packet payloads in the same storage group 1432 are not lost, but are read during the subsequent read process. The output controller 208 sends a signal to the decrement section 73 when the packet payload is received. The second counter 80 is then decremented by one.

When both the first counter 79 and the second counter 80 have equal values, the comparator 78 realizes that the bank address of the corresponding bank 1432 is put into the address queue 75 again.

All storage groups 1401-1432 are independent and can receive packet payloads independently and thus asynchronously. However, only one payload can be written to a memory bank 1401-1432 at a time.

The input device 86 could also be replaced by a 32 by 8-to-1 router, each an 8-to-1 multiplexer arrangement.

The above-mentioned device can realize synchronous reading of the included memory cells 6001-6128 within each memory group 1401-1432. This means that a second output controller 201-207 that wants to read a packet payload from the same memory bank 1401-1432 must wait until the packet payload currently being read is completely read, i.e. the read pointer reaches First byte of memory locations 6001-6128. This situation can be used as a standard for determining the size of the storage groups 1401-1432. Combining a small number of memory cells 6001-6128 in one memory bank 1402-1432 means that the likelihood of several output ports 501-508 simultaneously requesting to receive packet payloads from the same memory bank 1401-1432 is low. On the other hand, it is a fact that a large number of storage units 6001-6128 in a storage group 1401-1432 means that the expenditure on hardware is reduced, namely the input routers 121-128 and input selectors 1301-1332, because a Banks 1401-1432 have only one switch input 85 .

To keep the latency of blocked output ports 501-508 low, the memory cells 6001-6128 within a memory bank 1401-1432 should all be equally filled. Thus, during the read process, the read pointers of the group output controllers 1601-1632 are reset to the first byte of memory cells 6001-6128 immediately after having reached the last occupied byte of all memory cells 6001-6128, which Much faster than waiting for the read pointer to reach the last byte of memory location 6001-6128. Generally, the read process and the store process are independent of each other. Thus, the readout process of a particular packet payload can already be initiated when its first byte has been stored.

The above configuration has been exemplarily described for four small-sized groups, where the relationship between group size and storage group size is referred to herein as a combination factor of 4 (group per group). But this arrangement is also suitable for handling medium-sized packet types, ie packet types whose size exceeds the length of a single memory location 6001-6128 but is smaller than two memory locations 6001-6128. The switch can be programmed in such a way that the payload of such a packet is divided into two payload segments, each segment being stored in a separate, contiguous memory location 6001-6128.

This solution is drawn in Figure 3a. The first packet is divided into the first payload segment P1aPD501 (ie the first packet, segment a, packet destination output port 501) and two payload segments P1bpp501 (ie the first packet, segment b, packet destination output port 501). The first payload segment is stored in storage unit 6001 and the second payload segment is stored in subsequent storage unit 6002 . The same is done for the second packet divided into first payload segment P2apo503 and second payload segment P2bpo503. In storage group 1401, then, two medium-sized packets are stored. This relationship between packet size and storage group size is referred to herein as a combination factor of 2 (group per group). As far as the overall hardware configuration of the switching device with settings is concerned, the only difference from the combination factor 4 is the different programming of the switching actions of the unit selector switches 3401-3432, and thus the group input controllers 1501-1532 programming, and reading procedures for the various groups of output controllers 1601-1632.

In all cases, cell selector switches 3401-3432 enable precise switching between consecutive memory cells 6001-6128. Each memory bank 1401-1432 is connected to input device 86 by only one input line, namely at switch input 85 . This places a limit on the required size of the input device 86 . In the above case the output number of the input device 86 is divided by four compared to a known switching arrangement. Address queue 75 includes a pool of all free bank addresses, where each bank address includes four physical addresses (memory unit numbers). Each access to a bank address means an access to the entire bank 1401-1432, and only when all four memory cells 6001-6128 in this particular bank 1401-1432 have been read, a Only storage groups 1401-1432 can be appended to the pool of free storage group addresses.

Multicast packets are implemented by storing their payloads only once and putting the corresponding payload addresses into several output queues 261-268. The selection of output queues 261-268 is determined by the bitmap. The counting devices 72, 73, 74 provide control that the respective storage unit 6001-6128 and the respective storage bank 1401-1432 are not reused until the last copy of the multicast module packet stored therein has been read out.

In this arrangement, memory banks 1401-1432 have the smallest memory bank entity with a write pointer and four switch outputs 291-294. The four switch outputs 291-294 are grouped together by cell selector switches 3401-3432. Thus a bank 1401-1432 has a common input, switch input 85, and a write pointer. Since only one packet payload can be written to a memory bank 1401-1432 at a particular point in time, and all packet payloads arriving at a memory bank 1401-1432 come from the same input port 101-108, there will be no packet payloads The load must wait to be stored. All storage groups 1401-1432 are thus independent of each other, which means that each of them can start receiving a packet payload independently of the other storage groups 1401-1432. Therefore, input ports 101-108 can receive incoming packets independently of each other. There is thus no need for elastic buffers or delay removal logic to synchronize the input ports 101-108.

With respect to synchronous readout of packet payloads within a storage group, it is conceivable that small differences in packet arrival times lead to large delays in the synchronous readout process. However, since for asynchronously arriving packets that are being queued in different output queues 261-268, automatic synchronization has occurred when the first packet of such a queue has been queued for a period of time while being blocked, this problem is addressed. minimized.

A third relationship between packet size and storage group size called combination factor 1 is drawn in Fig. 3b, i.e. the storage of one packet of the large size packet type, which is thus divided into four payload segments P1aPD505 , P1bPD505, P1cPD505, P1dPD505, which are stored in four storage units 6001-6128 of one storage group 1401-1432. As shown in the figure, packet payload segments P1aPD505, P1bPD505, P1cPD505, P1dPD505 are all shorter than the length of one memory location 6001-6004, but therefore all segments are of equal length. As explained above, this proves to be better for a faster readout process. During the readout of such a large-sized packet, the output routers 171-178 are sequentially connected to each of the four storage units 6001-6004.

The possibility of combining factor definitions makes the switching device a universal device for different applications. Regardless of the size of the packet type, on-chip memory is usually maximized.

The output queues 261-268 can be split into regions with different priorities, which allows higher priority payload addresses to bypass those of lower priority, which ultimately means that these payloads are easier to read.

Reading payloads from the various memory banks 1401-1432 can be performed asynchronously or synchronously. In synchronous send mode, all memory banks 1401-1432 are synchronized for read operations. This means that there is an additional delay in synchronous send mode due to waiting for the synchronization point, here the synchronization point is defined as when the write pointer points to the first byte of all corresponding memory cells 6001-6128 in its corresponding memory group 1402-1432 that moment. However, depending on the combination factor, there are multiple synchronization points defined. For a combination factor of 1, there are four synchronization points within the read time of a packet. For combination factor 2, since a packet is longer than a storage unit, there are two synchronization points. For combination factor 4, there is only one synchronization point. In terms of absolute time length, the maximum delay is usually the same, that is, the length of the storage unit, eg 16 bytes here. This time will of course be reduced if the bytes of storage locations 6001-6128 are not all filled with the data of the stored payload. Subsequently, the read pointer is reset to the first byte immediately after the last payload byte, eg 12 bytes later.

Output routers 171-178 may be implemented as a blocking output router. This means that output routers 171-178, while reading payloads from a selected storage group 1401-1432, block any access to the same storage group 1401-1432 by other output routers 171-178. The output routers 171-178 can then be reduced in size by placing a multiplexer with one output and four inputs after each storage group 1401-1432, the output being connected to each output router 171-178, The inputs are connected to the outputs of the corresponding memory banks 1401-1432. The multiplexing means then acts like the inverse of the cell selector switches 3401-3432, allowing access to only one memory cell 6001-6128 of a memory bank 1401-1432 at a time. Thus longer accesses to blocked output ports 501-508 appear more likely. However, as already explained, the low probability of occasional simultaneous access to several output ports 501-508 of the same bank 1401-1432 is a fact that will keep the latency acceptably small.

In the output queue access manager 18, several data patterns, corresponding bitmaps can be processed in parallel, and corresponding received payload addresses can also be processed in parallel. The figures below illustrate the background. When assuming a clock cycle of 8 ns and a processing speed of one byte per clock cycle, the store procedure with a packet payload of size 12 bytes takes a total of 96 ns. This is the maximum acceptable time during which the storage group address queuing process must be completed for all input ports 101-108. When there are 32 input ports 101-108 and an equal number of output ports 501-508 and output queues 261-268, the input ports 101-108 are divided into groups of four and each group is processed within one clock cycle, the Sending the payload address into the output queues 261-268 takes 8 clock cycles, so 64ns is significantly less than 96ns. So, here, the parallelism of four simultaneously processed payload addresses is the minimum required to satisfy the necessary timely payload address queuing.

The structural principle of the switching device is suitable for any choice of size, which is also called scalability. This means that by varying the dimensions, some or all parts of the switching device can be selected, a desired number of input ports 101-108 output ports 501-508 and/or storage units 6001-6128, corresponding to storage banks 1401-1432.

The hardware devices described above can be altered while still retaining the basic principles of the invention. For example, increment section 74 need not be connected to input controllers 111-118. They can also be connected to the outputs of the output group 30 and then only receive the added values taken from the bitmap at the input ports 101-108 which are processed locally at that time. In addition, the bitmap does not have to be received by the switch controller 77, but can also be received by the input groups 281,282. The translation of the content of the bitmap can then take place in the output group 30 . In general, an interconnection with several components drawn as being connected by the same line may also be implemented as a bus connection or as separate lines.

In the following sections, a device comprising several of the switching devices described above will be described. For clarity, all switches are drawn with only two input ports and two output ports, but of course examples with a greater number of input and output ports work equally well.

The switching device is preferably adapted to be scaled up to enhance its performance. So as a scalable module it is available for a scalable system. There are different modes of expansion: size expansion, that is, an increase in the number of ports, storage area expansion for higher data throughput and rate expansion for higher port rates.

For size expansion, single-stage and multi-stage configurations are possible. The single-stage version is drawn in Figure 4. This design has less delay than a multi-stage network, and the number of switching devices grows by n2, where n is the multiplexing factor for the expansion of the input ports.

In FIG. 4, four switching devices 11, 12, 13, 14 are combined. The first switching device 11 has two input ports 21 , 22 and two output ports 31 , 32 . The second switching device 12 has two input ports 23 , 24 and two output ports 33 , 34 . The third switching device 13 has two input ports 25 , 26 and two output ports 35 , 36 . The fourth switching device 14 has two input ports 27 , 28 and two output ports 37 , 38 . A first system input 51 is connected to a first selector device 41 with two outputs, one output connected to input port 21 and one output connected to input port 23 . A second system input 52 is connected to a second selector device 42 with two outputs, one connected to input port 22 and one connected to input port 24 . A third system input 53 is connected to a third selector device 43 with two outputs, one connected to input port 25 and one connected to input port 27 . A fourth system input 54 is connected to a fourth selector device 44 with two outputs, one connected to input port 26 and one connected to input port 28 . The first arbiter 45 has an output port 31 as a first input and an output port 35 as a second input. Its output is defined as the first system output 55. The second arbiter 46 has an output port 32 as a first input and an output port 36 as a second input. Its output is defined as the second system output 56 . The third arbiter 47 has an output port 33 as a first input and an output port 37 as a second input. Its output is defined as the third system output 57 . The fourth arbiter 48 has an output port 34 as a first input and an output port 38 as a second input. Its output is defined as the fourth system output 58 .

The entire arrangement now has four input ports instead of two, system inputs 51-54, and four output ports, system outputs 55-58, but provides full connectivity between all input and output ports. The selectors 41, 42, 43, 44 act as address filters. The purpose of such an address filter is to select to which of the switching means 11, 12, 13, 14 an incoming packet is to be sent. This is done using the incoming packet headers. For example the entire packet may be copied and sent to the filter unit of each switching device 11, 12, 13, 14 so that only one filter allows the packet to pass. Such filter units can also be located in the exchange devices 11-14. In the case of multicast packets, it may be necessary to store the payload in several switching devices 11-14, especially if this is in no more than two devices. In addition, the arbiters 45, 46, 47, 48 select which of the switching devices 11, 12, 13, 14 has the authority to send its packets from its output ports 31-38 to the system outputs 55, 56, 57, 58 one of the. Purpose control with this facility is mainly limited to the automaticity of directly using the purpose information in the packet header. For an example with two inputs and two outputs, the binary code of two bits is drawn. The system output 55 has a binary code 60. System output 56 has binary code 01. System output 57 has binary code 10. System output 58 has binary code 11. In addition, the switching devices have been assigned a binary number, ie switching device 11 is the number 0, switching device 12 is the number 1, switching device 13 is the number 0 and switching device 14 is the number 1. Each switch 11-14 further has a code for each output port 31-38. Odd output ports are 0 and even output ports are 1. A packet arriving at any input 51-54 of the system with a destination code of a particular system output 55-58 in the header will automatically arrive at that system output 55-58. For example, the first bit of the destination code is used by the selector as an identification of the switch 11-14. The second bit identifies which output port of the marked switching device 11-14 is to be selected. The destination "10" then represents a packet arriving at the system input 53, the output 37 of the selective switch 14. This is true for all system input/system output combinations. Of course the encoding would be different if a greater number of input ports 21-28 and output ports 31-38 and/or system inputs 51-54 and system outputs 55-58 were used.

Packets processed with the means described above using coded values for the different switching means 11-14 and/or output ports can also be managed with bitmaps, as they have been for multicast packets. This means that all packets are handled as multicast packets and thus assigned a bitmap, and the packets are simply multiplexed in selectors 41-44 and sent to several switching means 11-14. Then the bitmap is only suitable for the configuration of the switching device 11-14, that is, a packet arriving at the switching device 11-14 but not to be stored is assigned a bitmap consisting only of logic "0", and for the correct switching device 11 -14, the bitmap draws the correct output port 31-38 to send the packet to. With such a bitmap, the adaptation of the encoding of the output ports 31-38 of the switching means 11-14 can also be easily handled by shifting the bitmap, for example by half its number of bits. This method is noted as the best when the whole device has been designed to be used for multicast packets.

In order to maintain the modular concept of switching devices 11, 12, 13, 14, it is possible to change the configuration, that is, arbitrators 45, 46, 47, 48 and selectors 41, 42, 43, 44 are symmetrically arranged on a common circuit board. It is integrated with switching devices 11, 12, 13, 14. This is called on-board arbitration, and it saves hardware costs.

In Figure 5 is drawn a configuration that includes arbitration in the board design. As long as the same elements are considered, the same numbering as in Figure 4 is retained. Each switching device 11 - 12 is now mounted on a separate printed circuit board (PCB) 59 , 60 , 61 , 62 . The selectors 41-44 are positioned exactly as the selectors 41-44 in Figure 4, only now evenly spaced so that one selector 41-44 is positioned on each PCB 59-62. But on the other side of the switching device 11-14, in order to obtain the same configuration of the PCBs 59-62, the connection between the arbiters 45-48 and the switching device 11-14 must be reconfigured. The first arbiter 45 now has an output port 31 as a first input and an output port 36 as a second input. Its output is defined as the first system output 55 . The second arbiter now has an output port 32 as a first input and an output port 35 as a second input. Its output is defined as the second system output 56 . The third arbiter now has an output port 34 as a first input and an output port 37 as a second input. Its output is defined as the third system output 57 . The fourth arbiter now has an output port 33 as the first input and an output port 38 as the sum input. Its output is defined as the fourth system output 58 . In fact, all PCB59-62 are now the same, which simplifies the product.

However, for this hardware device, destination control must be managed through redirection of packets. Whereas the switching means 11 and 12 do not require any redirection, the switching means 13 and 14 give the opposite action of the second bit, which means that eg a packet with destination 01 is actually sent to destination 00. This difficulty can be solved, for example, by implementing a mapping function in the adapter that sends the packets. A change from one of the two systems would result in many changes in multiple adapters because the switching system structure is no longer transparent to the adapters. Another solution is to add a redirection device to the selectors 41-44 which recognizes the problematic combination and assigns the correct code to the packet. This increases the complexity of the hardware structure.

Another solution to this problem is to implement a port mapping device in the switching device 11-14. This is given in Figure 6. Again the numbering of the same elements as in the previous figure is retained.

Each switching device 11-14 now includes a port mapping device programmed according to the application of the switching device 11-14. To illustrate that, each switching device 11-14 has been assigned an enlarged designation in the figure. Switching device 11 now has an enlarged designation OP0. Switching device 12 now has an enlarged designation 1P0. The switching device 13 now has an enlarged identification OP1. Switching device 14 now has an enlarged designation 1P1. The port mapping information for each switching device 11-14 is then contained in the "P0" or "P1" symbol. "p0" indicates that the binary coding of the output ports 31-38 of the respective switching devices 11-14 remains unchanged. "P1" indicates that the bit value ratio of the output port of each switching device must be inverted in order to transmit the packet correctly. By simple programming of the port mapping device, the entire hardware of all printed circuit boards 59-62 can be processed identically, which results in a cheaper product price. For configurations with more ports, flipping the bits can be replaced by swapping the port IDs, ie by moving the port IDs by approximately half the number of ports. The port mapping device may comprise a simple look-up table whose contents are programmed according to the system configuration or even multiple look-up tables selected corresponding to the system configuration. The second solution is easier to program. For multicast packets, it appears to be best to place a port mapping facility within the output queue access manager 18 so that the bitmap can be used to determine the assigned output ports 31-38 prior to port mapping.

Rate scaling can be achieved through link parallelism or a master/slave unit. In Figure 7 a master/slave configuration is given.

The first switching device 90 and the second switching device are arranged in parallel. A first system input 92 is split by a first splitting device 131 into two input ports 97,98. A second system input 93 is split by a second splitting device 132 into two input ports 96,99. The input ports 96 , 99 belong to the first switching device 90 and the input ports 98 , 99 belong to the second switching device 91 . The first switching device 90 has a first output 109 and a second output 110 . The second switching device 91 has a first output 119 and a second output 120 . Outputs 109 and 120 are combined by a first combining device 133 into a first system output 94 and outputs 119 and 110 are combined by a second combining device 134 into a second system output 95 .

The input ports 96-99 are divided by splitting means 131, 132 so that half of the incoming bits of a byte of an incoming packet are sent to the first switching means 90 and the other half are sent to the second switching means 91. The first switching device 90 is called master and the second switching device 91 is called slave. The master/slave arrangement uses the storage parts (storage devices, input devices, output facilities) and routers of the two switching devices 90, 91, but only the control part of the master device 91 (queue control devices, output queues, bookkeeping devices). The routing process in the slave device 90 is the same as in the master device 91 . Thus, it is generally possible to use a chip that does not contain any control part as the slave device 90 . In addition, it is possible to use a chip without any memory section as the main device 91 .

Since the length of the packet payload is reduced by such partitioning of the data, each switching device 90, 91 requires less storage space to store the entire packet payload. Through this reduction in packet length, routing time is also greatly reduced. In addition, more memory cells are used to store payloads in the switches 90, 91, which enhances performance by reducing the likelihood of back pressure, i.e. from one or more switches to the next Or the process by which a packet sending device sends a signal that the corresponding packet cannot be received because the storage area is full or the output queue is full. The combining devices 133, 134 simply put together the groups of bits received from the master 91 and the slave 90, which together retrieve the entire packet.

For storage expansion, correspondingly for performance expansion, several switching devices can be connected in parallel. Each switching device works in parallel, but considering an output port, usually only one switching device is active at a time. This is controlled by an input arbitration device. Each switching device receives a predetermined minimum number of packets for each output queue until the input arbitration device switches to another output queue for the same output port in another switching device. The input arbitration device then signals to the next switching device that it is requested to be responsible for receiving packets for that output port. This can be done in a loop. The order of the packets per output port is maintained by using tag information which tells the output arbitrator which switch contains the output queue containing the next payload address to send the packet to a particular output port. The marking information may, for example, be added to the last packet before the next packet is stored in a different switching device.

All expansion units can be combined with each other to bring higher performance.

Switching devices are best suited for ATM-based broadband communications. But with suitable adapters, the concept can also be applied in non-ATM structured environments. Single-stage or multi-stage structures can be constructed in a modular manner. Shared memory areas can also be expanded by linking multiple switching devices.

It should be noted that the functions described above are not necessarily realized by the exact configuration of the elements. For example, the storage unit number does not have to be sent by the group input controllers 1501-1532 to the output queue access manager 18, but can get there in a different way. Obviously, the only important fact is that the bank number should be stored in the corresponding output queue 261-268 to complete the payload address. Likewise, the functions of the selectors 41-44 do not have to be centralized in the selectors 41-44, but can be distributed and even integrated with corresponding parts of the selectors 41-44 on the printed circuit boards 59-62 or integrated in Inside the switching device 11-14.

Claims (32)

1. the grouping of the fixed-length data of the information that comprises a purpose head and pay(useful) load form that enters is sent to the switch of a plurality of output ports (501-508) from a plurality of input ports (101-108), comprise the input equipment (86) that is used for the above-mentioned above-mentioned pay(useful) load that enters grouping is delivered to the memory device (87) that includes a plurality of memory cell (6001-6128), and comprise and be used for reading the pay(useful) load of above-mentioned storage and they are sent into one the output equipment of selecting from above-mentioned output port (501-508), this option is pre-determined by the above-mentioned purpose head, it is characterized in that, at least one switching equipment (3401-3432) is provided, each switch output (291-294) of being linked one of said memory cells (6001-6128) that it comprises more than above-mentioned pay(useful) load from above-mentioned input equipment (121-128,4001-4256,1301-1332) switch that arrives this place is imported (85), with in the above-mentioned switch output (291-294) at least two be exclusively used in same above-mentioned switch input (85), and when above-mentioned switching equipment (3401-3432) can switch between with the predetermined switch output (291-294) of order in above-mentioned special use, above-mentioned pay(useful) load is imported (85) lead switch of its special use from above-mentioned switch export (291-294).

2. according to the switch in the claim 1, it is characterized in that in order to handle the above-mentioned packet type that enters the different length of grouping, the said memory cells (6001-6128) of linking above-mentioned switching equipment is by following definite size, thereby their size is littler than a large scale packet type, and the length with the above-mentioned pay(useful) load of a small size packet type is the same at least, and under a situation of dividing into groups to arrive of above-mentioned large scale packet type, above-mentioned switching equipment (3401-3432) can be controlled as follows, and the above-mentioned pay(useful) load of promptly above-mentioned large scale packet type is divided into the pay(useful) load section with in the sequential cells that is stored in the said memory cells (6001-6128) of linking above-mentioned switching equipment (3401-3432).

3. according to the switch of claim 2, it is characterized in that, the number of the above-mentioned mailbox memory (6001-6128) of above-mentioned switching equipment (3401-3432) is following selected, thereby their element length summation is at least enough stored the whole pay(useful) load that will be scheduled to a grouping of full-size packet type by one of this switch processing.

4. according to the switch one of in the claim 1 to 3, it is characterized in that all above-mentioned mailbox memories (6001-6128) that are connected to one of above-mentioned switching equipment (3401-3432) are incorporated in the single storage sets (1401-1432) of the group output control equipment (1601-1632) that has an appointment, group output control device is used for the said memory cells (6001-6128) of above-mentioned storage sets (1401-1432) is controlled synchronous readout.

5. according to one of any switch of claim 1 to 3, it is characterized in that, the output queue (261-268) of a special use is provided for each above-mentioned output port (501-508), be used for receiving and transmit about which said memory cells (6001-6128) and include the segment information that to deliver to corresponding to the above-mentioned pay(useful) load of the above-mentioned output port (501-508) of above-mentioned output queue (261-268) to a special o controller (201-208)

6. according to the switch of claim 5, it is characterized in that, input controller (1501-1532) is provided, be used for controlling the switch of above-mentioned switching equipment (3401-3432) and, deliver to above-mentioned output queue (261-268) including the part of the information of the above-mentioned pay(useful) load that will deliver to above-mentioned output port (501-508) as above-mentioned that section about which said memory cells (6001-6128) about the information of this switch.

7. according to claim 1 to 3 or 6 one of any switches, it is characterized in that, interpreting equipment is provided, is used for above-mentioned head is translated into a data pattern, this pattern comprises about above-mentioned and enters the information which above-mentioned output port (501-508) grouping will be sent to.

8. according to the switch of claim 6, it is characterized in that, formation control appliance (18) is provided, be used to receive above-mentioned data pattern, and above-mentioned that section is sent to the above-mentioned output queue of being determined by this data pattern (261-268) about including the information that will deliver to corresponding to the above-mentioned pay(useful) load of the above-mentioned output port (501-508) of above-mentioned output queue (261-268) in which said memory cells (6001-6128).

9. according to the switch of claim 8, it is characterized in that, above-mentioned formation control appliance (18) is designed to a plurality of above-mentioned data patterns of parallel receive, and a plurality of above-mentioned those are included the parallel above-mentioned output queue (261-268) that sends to of information of the above-mentioned pay(useful) load that will send about which said memory cells (6001-6128).

10. according to claim 1 to 3,6,9 one of any switches, it is characterized in that providing counting equipment (7 3,74,72), be used to each above-mentioned storage sets (1401-1408) and/or said memory cells (6001-6128) to calculate the readout number and determine whether a pay(useful) load has been delivered to the output port (501-508) of its correspondence fully.

11. the switch according to claim 10 is characterized in that, above-mentioned counting equipment (73,74,72) be designed to receive take from above-mentioned data pattern information as the deviant that is used to calculate above-mentioned readout number of times.

12. switch according to claim 11, it is characterized in that above-mentioned counting equipment comprises first counter (74 that is used for receiving from above-mentioned data mode above-mentioned information for each above-mentioned storage sets (1401-1408) and/or said memory cells (6001-6128), 79), with second counter (73 that is used to calculate corresponding readout number of times, 80), and be used for more above-mentioned counter (73,74,79,80) Zhi comparator device.

13., it is characterized in that described switching equipment is set to the above-mentioned pay(useful) load that enters grouping that makes a multicasting type and is only deposited in above-mentioned memory device once, and be read out repeatedly according to the switch of claim 1.

14. switch according to claim 1, it is characterized in that providing book card management equipment (71), it comprises one and contains the above-mentioned storage sets (1401-1408) that do not comprise the no show pay(useful) load and/or the address queue (75) of said memory cells (6001-6128) address.

15. switching equipment according to comprising of claim 1 of a plurality of switches (11-14), the input port (21-28) that it is characterized in that above-mentioned switch (11-14) is connected via selection equipment (41-44) is parallel, this selection equipment achieves a butt joint and receives the selection of one of above-mentioned switch (11-14) that arrives grouping, and the output port (31-38) of above-mentioned switch (11-14) connected via arbitration equipment (45-48) is parallel, and this arbitration equipment (45-48) is realized the selection that goes out one of above-mentioned switch (11-14) that grouping sends from above-mentioned output port (55-58) to one.

16., it is characterized in that each above-mentioned switch (11-14) is grouped together with one of above-mentioned arbitration equipment (45-48) and one of above-mentioned selection equipment (41-44) as the module of scaling (59-62) in proportion according to the switching equipment of claim 15.

17. according to the switching equipment of claim 16, it is characterized in that providing port mapping equipment, it is realized according to the appointment of the purpose head of going into grouping to output port according to the interconnection of a plurality of above-mentioned switches (11-14).

18. according to comprising of claim 1 of a plurality of switches (90,91) switching equipment, it is characterized in that above-mentioned switch (90,91) input port (96-99) is linked splitting equipment (131-132), this equipment is divided into the bit group to a byte of going into grouping, each group is sent to switch (90,91) in one, and output port (109,110,119,120) linked unit equipment (133,134), this equipment is grouped into the bit group of taking from above-mentioned switch (90,91) together.

19. the grouping of the fixed-length data of the information that comprises a purpose head and pay(useful) load form that enters is delivered to the method for a plurality of output ports (501-508) from a plurality of input ports (101-108), comprise a step of the above-mentioned above-mentioned pay(useful) load that enters grouping being delivered to the memory device (1401-1432) that includes a plurality of memory cell (6001-6128), with the pay(useful) load of above-mentioned storage is read and they are delivered to one the step of selecting from above-mentioned output port (501-508), this selection is pre-determined by the above-mentioned purpose head, it is characterized in that above-mentioned pay(useful) load imports the switch output (291-294) that (85) deliver to above-mentioned special use via switching equipment (3401-3432) from above-mentioned switch, switch between the switch output (291-294) of above-mentioned special use with a predetermined order simultaneously, each switch output (291-294) of being linked one of said memory cells (6001-6128) that this commutating device comprises more than above-mentioned pay(useful) load from above-mentioned input equipment (121-128,4001-4256,1301-1332) switch that arrives this place is imported (85), and at least two are exclusively used in same switch input (85) in the above-mentioned switch output (291-294).

20. method according to claim 19, it is characterized in that, for handling the above-mentioned packet type that enters the different length of grouping, the following size of determining to link the said memory cells (6001-6128) of above-mentioned switching equipment (3401-3432), thereby their size is littler and the length with the above-mentioned pay(useful) load of a small size packet type is the same at least than the length of the above-mentioned pay(useful) load of a large scale packet type, and under a situation of dividing into groups to arrive of above-mentioned large scale packet type, above-mentioned switching equipment (3401-3432) is controlled as follows, and the above-mentioned pay(useful) load of promptly above-mentioned large scale packet type is divided into the pay(useful) load section with in the sequential cells that is stored in the said memory cells (6001-6128) of linking above-mentioned switching equipment (3401-3432).

21. method according to claim 20, the number of above-mentioned mailbox memory (6001-6128) that it is characterized in that above-mentioned switching equipment (3401-3432) is following selected, thereby their memory cell length summation is at least enough stored the whole pay(useful) load of a grouping of the predetermined full-size packet type that will be handled by this switch.

22. method according to claim 19 or 20, all above-mentioned mailbox memories (6001-6128) that one of it is characterized in that being connected in the above-mentioned switching equipment (3401-3432) are incorporated in the single storage sets (1401-1432) of the group output control equipment (1601-1632) that has an appointment, and the group output control equipment is used for the said memory cells (6001-6128) of above-mentioned storage sets (1401-1432) is controlled synchronous readout.

23. method according to claim 19 or 20, it is characterized in that for each above-mentioned output port (501-508), the output queue of a special use (261-268) receives the segment information that will deliver to corresponding to the above-mentioned pay(useful) load of the above-mentioned output port (501-508) of above-mentioned output queue (261-268) about including in which said memory cells (6001-6128), and delivers to a special output queue (261-268).

24. method according to claim 23, the switch Be Controlled that it is characterized in that above-mentioned switching equipment (3401-3432), and about the information of this switch by as the part of above-mentioned that section about the information of the above-mentioned pay(useful) load that includes the above-mentioned output port (501-508) that will deliver to above-mentioned output queue (261-268) in which said memory cells (6001-6128), send to above-mentioned output queue (261-268).

25. according to the method for claim 19,20 or 24, it is characterized in that above-mentioned head is translated into a data pattern, this pattern comprises about above-mentioned and enters the information which above-mentioned output port (501-508) grouping will be sent to.

26. method according to claim 24, it is characterized in that above-mentioned data pattern is received in the formation control appliance (18), and by as above-mentioned that section about including the information that will deliver to corresponding to the above-mentioned pay(useful) load of the above-mentioned output port (501-508) of above-mentioned output queue (261-268) in which said memory cells (6001-6128), send to the above-mentioned output queue of determining by this data pattern (261-268).

27. method according to claim 26, it is characterized in that a plurality of above-mentioned data patterns of above-mentioned formation control appliance (118) parallel receive, and a plurality of above-mentioned parallel above-mentioned output queues (261-268) that send to of information that include the above-mentioned pay(useful) load that will send about which said memory cells (6001-6128).

28. according to claim 19,20,24 or 27 method, it is characterized in that counting equipment (23,74,72) number that calculates readout for each above-mentioned storage sets (1401-1408) and/or said memory cells (6001-6128) determines whether that a pay(useful) load delivered to the output port (501-508) of its correspondence fully.

29., it is characterized in that above-mentioned counting equipment (73,74,72) receives and take from the information of above-mentioned data pattern as the deviant that is used to calculate above-mentioned readout number of times according to the method for claim 28.

30. the method according to claim 29 is characterized in that, for each above-mentioned storage sets (1401-1408) and/or said memory cells (6001-6128), at above-mentioned counting equipment (73,74,72) receive above-mentioned information in first counter (74,79) from above-mentioned data pattern, at second counter (73,80) calculate corresponding readout number of times in, and in a comparator device more above-mentioned counter (73,74,79,80) value.

31., it is characterized in that the above-mentioned pay(useful) load that enters grouping of a multicasting type is only deposited in above-mentioned memory device once, and be read out repeatedly according to the method for claim 19.

32. method according to claim 19, it is characterized in that an address administration equipment (71) that comprises address queue (75), the address of above-mentioned storage sets (1401-1408) and/or said memory cells (6001-6128) is not comprised the Payload that is not transmitted by lining up.

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