CN1181525C - Wafer type diffusion type packaging system - Google Patents
Wafer type diffusion type packaging system Download PDFInfo
- Publication number
- CN1181525C CN1181525C CNB021017522A CN02101752A CN1181525C CN 1181525 C CN1181525 C CN 1181525C CN B021017522 A CNB021017522 A CN B021017522A CN 02101752 A CN02101752 A CN 02101752A CN 1181525 C CN1181525 C CN 1181525C
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- Prior art keywords
- wafer
- hard base
- packaging system
- type diffusion
- input
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 21
- 238000009792 diffusion process Methods 0.000 title claims abstract 17
- 239000013078 crystal Substances 0.000 claims abstract description 60
- 238000006073 displacement reaction Methods 0.000 claims abstract description 29
- 239000011521 glass Substances 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004925 Acrylic resin Substances 0.000 claims description 3
- 229920000178 Acrylic resin Polymers 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 239000005011 phenolic resin Substances 0.000 claims description 3
- 229920001568 phenolic resin Polymers 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 claims description 2
- 239000002390 adhesive tape Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims 4
- 238000012360 testing method Methods 0.000 abstract description 10
- 235000012431 wafers Nutrition 0.000 description 56
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 42
- 238000005538 encapsulation Methods 0.000 description 28
- 238000005516 engineering process Methods 0.000 description 12
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Images
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a wafer type diffusion type packaging system, comprising: a wafer input/output device, a wafer step displacement device, which is a carrier for bearing the wafer in the wafer input/output device, a hard base step displacement device, which is a carrier for bearing the hard base in the hard base input/output device, a crystal grain taking and placing device, which makes the crystal grains with good test results take out according to a certain sequence and rearranges the crystal grains on the hard base, a central computer control device for controlling the operations of the wafer input/output device, the wafer step displacement device, the hard base input/output device, the hard base step displacement device and the crystal grain taking and placing device, so as to achieve the purpose of taking out the crystal grains and rearranging the crystal grains on the hard base.
Description
Technical field
The present invention is relevant with a kind of semiconductor crystal wafer kenel diffused package system, and particularly native system helps the taking-up and the placement of crystal grain, is beneficial to finish wafer form (wafer levelpackaging) diffused (fan out type) encapsulation.
Background technology
After the downsizing along with electronic component dimensions, many new challenges appear on the manufacture process of integrated circuit.And because computer and mechanics of communication is flourish, what follow needs is the electronic component of more variety classeses and application.For example, all need many memory cells and dissimilar semiconductor elements by the computer interface of voice operating or the interface of other communications.So the trend of integrated circuit still can develop towards high integration.Quick evolution along with semiconductor technology, electronic product is under the promotion of the fast trend of compact, multi-functional speed, the not only more and more density of the semi-conductive I/O number of IC are also more and more higher, make that the number of pins of potted element is also more and more thereupon, and the requirement of speed is also more and more faster.Semiconductor wafer individually is encapsulated within the packaging body of plastic cement or ceramic material usually.The structure of packaging body must be able to be protected wafer and the heat that is produced in the wafer operating process is shed the usefulness when traditional encapsulation also is used as the wafer functional test.
Early stage encapsulation technology is main encapsulation technology based on lead frame, utilizes input and the output of pin as signal.And under the demand of high density input and output, the encapsulation of lead frame has not met above-mentioned demand at present.At present, under above-mentioned demand, encapsulation is also done littler and littler meeting present trend, and ball arranged encapsulation technology (ball grid array is also followed in the encapsulation of high density I/O; Hereinafter to be referred as BGA encapsulation) development of technology and haveing breakthrough, therefore, the encapsulation of IC semiconductor carrying trends towards utilizing ball arranged encapsulation technology (BGA).The characteristics of BGA structure dress are, the pin of being responsible for I/O is spherical elongate pins than the lead frame packaging element apart from short and be difficult for impaired distortion, and the short speed of the electrical transmission range of its potted element is fast, can meet at present and the demand of following digital system speed.For example, in United States Patent (USP) U.S.Patent No.5,629,835, by Mahulikar etc. the structure of a kind of BGA is proposed just, denomination of invention is " METAL BALL GRIDARRAY PACKAGE WITH IMPROVED THERMAL CONDUCTIVITY ".The semiconductor packages that many different kenels have been arranged at present is as above-mentioned lead frame or BGA encapsulation.For example, as United States Patent (USP) U.S.Patent No.5,239,198 disclose a kind of packing forms, and this encapsulation comprises a substrate that is assembled on the printed circuit board (PCB), and substrate utilizes the FR4 material to form, and has the surface that a conducting wire is formed at substrate on this substrate.
In addition, the semiconductor packages of many different kenels has been arranged a few days ago, no matter be the encapsulation of any kenel, most being encapsulated as encapsulates and tests after being cut into individuality in advance.And United States Patent (USP) has a kind of wafer form encapsulation of exposure, see also, and US5323051, denomination of invention is " Semiconductor wafer level package ".This patent encapsulated before cutting crystal grain in advance, utilized glass to be used as a bonding material and made element be encapsulated in the hole.One perforation that hides allows the passage as electrically connect.Therefore, wafer form is encapsulated as a kind of trend of semiconductor packages.
In addition, in the encapsulation technology field in the past, I/O aluminium pad (Pad) part is the surface that is connected to crystal grain, because chip area is limited, I/O aluminium pad will limit its aluminium pad number under limited area.Moreover the spacing of I/O aluminium pad is too small will to cause coupling (signal coupling) between signal or the interference between signal.
Because the wafer form encapsulation will become the trend of encapsulation technology, the present invention has replaced in the past the position that on grain surface I/O plants ball, and in diffused (fan out) mode, contact point is implanted the ball of planting as I/O toward outdiffusion to promote bigger scope, therefore, its advantage comprises can increase the number that I/O plants ball, that is the more I/O of increase, or at crystal grain under the trend of downsizing, the minimum spacing (pitch) that keeps I/O is to prevent too to disturb (signal couplig) problem near the signal that is caused.
Because the packaged type of the overwhelming majority is traditionally: be cut into individuality in advance, afterwards, carry out again encapsulating on the crystal grain one by one, last, test again.Its shortcoming is that spent time is many, and can't avoid bad die package.
And the improvement method of above-mentioned shortcoming is: the cutting crystal wafer of going ahead of the rest, relend by the mode of a block of a block and test crystal grain, through screening, will be by the crystal grain after the quality control, the crystal grain of choosing (die), see through to draw with the action of placing and rearrange on a new glass pedestal, and finish the encapsulation of diffused wafer scale.So, can reduce being made into wood on the one hand, another goes into face can be very little to avoid bad die package.
Therefore, the crystal grain that the invention provides diffusion-type wafer encapsulation takes out place system, is beneficial to carrying out of above-mentioned purpose.
Summary of the invention
Purpose of the present invention is beneficial to crystal grain taking-up placement and finishes the diffusion-type wafer encapsulation for a kind of diffusion-type wafer package system is provided.
The present invention discloses a kind of diffusion-type wafer package system, comprises: the wafer I/O device, it comprises mechanical arm and transports a pending wafer to first predeterminated position.The wafer gearshift, is beneficial to carry out the plane and moves this wafer to second precalculated position by the wafer that this wafer I/O device is transmitted in order to carrying.Hard pedestal I/O device, it comprises mechanical arm and transports the hard pedestal to second predeterminated position.
Hard pedestal gearshift, the hard pedestal that it is transmitted by this hard pedestal I/O device for carrying is beneficial to carry out the plane and moves this hard pedestal to the four predeterminated positions.Crystal grain takes out apparatus for placing, wherein comprise and have a mechanical arm movably, when taking out apparatus for placing, this crystal grain utilize this mechanical arm to draw specific die on the wafer in this wafer gearshift, vacuum robot is a distance up immediately, horizontal direction by a horizontal stepper moves then, to the hard pedestal gearshift and again alignment arrangements in this crystal grain on this hard pedestal ad-hoc location.The central computer system with above-mentioned wafer I/O device, wafer step-wise displacement device, hard pedestal I/O device, hard pedestal step-wise displacement device and the binding of crystal grain taking-up apparatus for placing, takes out the control of placing in order to carry out crystal grain.
Description of drawings
Fig. 1 is shown to place the mechanical device schematic diagram for crystal grain of the present invention takes out;
Fig. 2 is shown to make up schematic diagram for crystal grain of the present invention takes out the place system mechanical device;
The shown signal of taking out placement for wafer-level packaging crystal grain of the present invention of Fig. 3.
The figure number explanation:
10,300-wafer
310-crystal grain
The 330-clear area
The 20-aluminium chassis
The 30-vacuum robot
The 35-absorption heads
The 350-shift action
40,70,90-X direction stepper
50,80-Y direction stepper
60,320-hard pedestal
100-wafer I/O device
110-wafer step-wise displacement device
120-hard pedestal I/O device
130-hard pedestal step-wise displacement device
140-crystal grain takes out apparatus for placing
150-central computer control device
Embodiment
Purpose of the present invention is for providing a kind of diffusion-type wafer package system, and it utilizes a central computer to come the interior device of control system, takes out and rearrange the purpose of placement crystal grain on hard pedestal (rigid base) to reach the product grain.
Diffusion-type wafer package system of the present invention is described in detail as follows, and it is non-in order to limit the present invention that an explanation is only done in described preferred embodiment.
See also Fig. 1 and Fig. 2, one wafer 10, it is the wafer of crossing through cutting (sawing), test (testing) 10, has just finished the test of wafer form, through screening good crystal grain (good die) location information is transferred to central authorities and handles computer 150.The processing procedure of above-mentioned crystal grain and wafer form test are another technical scope, and non-emphasis of the present invention is not so described in detail.By the running of wafer I/O device 100, pending wafer can be transported on the wafer step-wise displacement device 110 via the mechanical arm on the I/O device 100.And the wafer 10 after the cutting supports by aluminium chassis (frame) 20 and adhesive tape (tape).The wafer step-wise displacement device 110 of carrying wafer 10 comprises directions X stepper 40 and Y direction stepper 50.Utilize two above-mentioned directions X steppers 40 can make wafer 10 carry out two dimensional surface and move to a precalculated position with Y direction stepper 50.Above-mentioned plane mobile technology can be consulted stepper motor and wafer step-wise displacement technology.One machine crystal grain takes out placing device 140 and comprises mechanical arm 30 and a level (directions X) stepper 90 at least.Mechanical arm 30 can be done by the control of computer and known Automatic Control Theory and pick up and put action.Level (directions X) stepper 90 can utilize stepper motor to do linear moving, and utilizes in the appropriate location to move up and down and picks up the indicated garbled good dies (good die) by central computer system 150.Relend by level (directions X) stepper 90 crystal grain is sent to specified position, crystal grain is placed to a hard pedestal with mechanical arm 30.
Running by hard pedestal I/O device 120, make the mechanical arm in the hard pedestal I/O device 120 transport on above-mentioned hard pedestal 60 to the one hard pedestal step-wise displacement devices 130, hard pedestal step-wise displacement device 130 is the carrier of hard pedestal 60 in the carrying hard pedestal I/O device 120.In like manner, above-mentioned hard pedestal step-wise displacement device 130 utilizes the stepper technology to be implemented.The hard pedestal step-wise displacement device 130 of carrying hard pedestal 60 can carry out a plane and move to a precalculated position, makes that the hard pedestal 60 on the hard pedestal step-wise displacement device 130 is rough parallel with the wafer 10 on the wafer step-wise displacement device 110.Above-mentioned plane is moved by directions X stepper 70 and Y direction stepper 80 and is finished.
The top surface area of above-mentioned hard pedestal 60 is bigger than the top surface area of wafer 10, is beneficial to make the diffused encapsulation.And the geometry of hard pedestal 60 is similar to wafer 10.Hard pedestal 60 materials can be glass (glass), pottery (ceramics) or silicon crystal (silicon), and coating one adhesive agents above the hard pedestal 60, and it is used for the crystal grain of adhering.The composition of adhesive agent generally can be epoxy resin (Epoxy Resin), acrylic resin (Acrylic Resin) or phenolic resins (Phenolic Resin).It is non-in order to limit the present invention that above-mentioned composition or material are only done an explanation.And the coating process of hard pedestal 60 can utilize a coating machine (coater), laminator to be coated with, and coating thickness is about 10 microns (μ m).
Then, utilize above-mentioned crystal grain to take out apparatus for placing 140, use movably vacuum robot (arm) 30.After crystal grain takes out apparatus for placing 140 and utilizes absorption heads 35 on the vacuum robot 30 to draw a certain crystal grain of the wafer 10 in (pick) wafer step-wise displacement devices 110, vacuum robot 30 is (Up) a little distance vertically up immediately, then, drive along the horizontal direction parallel with directions X stepper 90 and to move the top of hard pedestal 60 in hard pedestal step-wise displacement device 130 with hard pedestal 60, wafer 10.Afterwards, vacuum robot 30 is vertical toward (down) a little distances once, and puts (Place) crystal grain in hard pedestal 60 above a certain position.Above-mentioned horizontal direction moves by directions X stepper 90 and finishes.The above-mentioned relevant position that picks up and put is controlled by the central computer system.
See also Fig. 3, the taking-up of crystal grain is to select the good crystal grain of test result on the above-mentioned sliced wafer 300, for example crystal grain 310, it takes out according to certain order, and rearranging placement crystal grain 310 on hard pedestal 320 crystal grain reception areas 330, above-mentioned shift action 350 sees through crystal grain taking-up apparatus for placing 140 to carry out.Wherein also can comprise the side that electric capacity (capacitor) or other crystal grain 340 are disposed at crystal grain 310 on the hard pedestal 320, to promote filter effect or to make multiple die package structure (multi-chip package).With an embodiment, wherein the order that takes out of crystal grain is to comply with left-to-right principle from top to down to carry out, and crystal grain to rearrange the order of placement also be to comply with left-to-right principle from top to down to carry out.Crystal grain rearranges controlled being formed in 2 microns (μ m) of precision of placement.Finish after the configuration of crystal grain, then can carry out the processing procedure and the final test of diffusion-type wafer encapsulation.
Above-mentioned wafer I/O device 100, wafer step-wise displacement device 110, hard pedestal I/O device 120, hard pedestal step-wise displacement device 130 are controlled by a central computer control device 150 with the action that crystal grain takes out each step in the apparatus for placing 140.The foundation (set up) that sees through central computer control device 150 job-program modes (job file) can be carried out the process that whole crystal grain takes out placement.
Major advantage of the present invention is as follows:
1, the present invention is by the wafer process screening of testing and cutting, will be by the crystal grain after the quality control, the crystal grain of choosing (die) sees through crystal grain and draws the action of apparatus for placing and rearrange on a new glass base, can reduce cost of manufacture and finish the diffused encapsulation.
2, the present invention can be applied to 8 cun with the encapsulation of 12 cun diffusion-type wafers.
3, the present invention can integrate crystal grain and electric capacity in same encapsulation monomer.
4, the present invention can be integrated in same monomer with polycrystalline grain (multi-chip) or multiple passive device, central processing unit for example, and DRAM, SRAM or the like is in the encapsulation process of encapsulation base plate.
5, the glass of hard pedestal use of the present invention, (glass, ceramic silicon) can improve its reliability to pottery with silicon crystal.
To being familiar with this field skill person, though the present invention illustrates as above with a preferred embodiments, so it is not in order to limit spirit of the present invention.Modification of being done in not breaking away from spirit of the present invention and scope and similarly arrangement all should be included in the described claim scope.
Claims (15)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021017522A CN1181525C (en) | 2002-01-17 | 2002-01-17 | Wafer type diffusion type packaging system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021017522A CN1181525C (en) | 2002-01-17 | 2002-01-17 | Wafer type diffusion type packaging system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1363951A CN1363951A (en) | 2002-08-14 |
| CN1181525C true CN1181525C (en) | 2004-12-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021017522A Expired - Lifetime CN1181525C (en) | 2002-01-17 | 2002-01-17 | Wafer type diffusion type packaging system |
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| Country | Link |
|---|---|
| CN (1) | CN1181525C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7459781B2 (en) * | 2003-12-03 | 2008-12-02 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
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2002
- 2002-01-17 CN CNB021017522A patent/CN1181525C/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| CN1363951A (en) | 2002-08-14 |
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