CN118157816A - Inquiry end circuit supporting asymmetric data mode - Google Patents

Abstract

The present invention relates to an inquiry end circuit supporting an asymmetric data mode, and proposes an inquiry end circuit in a vehicle Ethernet network system, which comprises: a mixing circuit, which is configured to perform data communication with an inquiry end circuit through a medium-related interface circuit; a transmission circuit, which is coupled to the mixing circuit and configured to generate and provide a transmission signal to the mixing circuit; a receiving circuit, which is coupled to the mixing circuit and configured to receive and analyze a reception signal transmitted from the mixing circuit to generate a data signal; a processing circuit, which is coupled to the receiving circuit and configured to process the data signal; a physical coding sublayer circuit, which is coupled to the processing circuit and configured to perform physical coding operation to control the operation of the transmission circuit; and an echo cancellation circuit, which is coupled between the transmission circuit and the receiving circuit and configured to generate an echo cancellation signal.

Description

Inquiry circuit supporting asymmetric data mode

Technical Field

The present invention relates to automotive Ethernet communication technologies, and more particularly to an inquiry end circuit supporting an asymmetric data mode.

Background technique

With the development of technology, the application of automotive Ethernet communication technology is becoming more and more popular, and the number of Ethernet communication devices (for example, various Ethernet communication chips) installed on vehicles is also increasing. According to the specifications of the automotive Ethernet communication protocol, full-duplex transmission mechanism must be used for various data communications between two devices using the automotive Ethernet communication protocol.

As we all know, full-duplex transmission mechanism consumes more power. However, for many vehicles (especially electric vehicles), the power efficiency of vehicle devices is a very important performance indicator. Therefore, if the power consumption of vehicle Ethernet communication devices cannot be effectively reduced, the development of vehicle Ethernet communication technology will inevitably be hindered.

Summary of the invention

In view of this, how to reduce the power consumption of the vehicle Ethernet communication device is indeed a problem to be solved.

The present specification provides an embodiment of an inquiry end circuit, which includes: a mixing circuit, configured to perform data communication with an inquiry end circuit through a media-related interface circuit; a transmitting circuit, coupled to the mixing circuit, configured to generate and transmit a transmitting signal to the mixing circuit; a receiving circuit, coupled to the mixing circuit, configured to receive and analyze a receiving signal transmitted by the mixing circuit to generate a data signal; a processing circuit, coupled to the receiving circuit, configured to process the data signal; a physical coding sublayer circuit, coupled to the processing circuit, configured to perform a physical coding operation to control the operation of the transmitting circuit; and an echo cancellation circuit, coupled between the transmitting circuit and the receiving circuit, configured to generate an echo cancellation signal.

One of the advantages of the above embodiment is that the inquiring circuit can determine whether the interrogated circuit can support an asymmetric data mode.

Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified functional block diagram of a vehicle Ethernet system according to an embodiment of the present invention.

2 and 3 are simplified flow charts of an embodiment of a data communication method used in the vehicle Ethernet system of the present invention.

FIG. 4 is a simplified timing diagram of different embodiments of the asymmetric data mode of the present invention.

Symbol Description

100...Automotive Ethernet system

102, 104... twisted pair

110...Inquirer-side circuit

111...Medium dependent interface circuit (MDI circuit)

112...Hybrid circuit

113...transmitting circuit

114...Receiving circuit

115...Processing circuit

116...physical coding sublayer circuit

117...Echo cancellation circuit

120...respondent-side circuit

121...Media Dependent Interface Circuit (MDI circuit)

122...Hybrid circuit

123...transmitting circuit

124...Receiving circuit

125...Processing circuit

126...physical coding sublayer circuit

127...Echo cancellation circuit

202～212、302～310...operation process (operation)

410...First asymmetry data mode

411, 421...data transmission cycle

413, 415, 423, 425...data transmission period

415...Data transmission period

420...Second asymmetry data mode

Sd1, Sd2...data signal

Sr1, Sr2...received signal

St1, St2...transmission signal

Detailed ways

The embodiments of the present invention will be described below in conjunction with the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar elements or method flows.

1 is a simplified functional block diagram of a vehicle Ethernet system 100 according to an embodiment of the present invention. The vehicle Ethernet system 100 includes an interrogating circuit 110 and an interrogated circuit 120. Various data communications can be performed between the interrogating circuit 110 and the interrogated circuit 120.

As shown in FIG1 , the inquiring end circuit 110 includes a medium-dependent interface circuit 111, a mixing circuit 112, a transmitting circuit 113, a receiving circuit 114, a processing circuit 115, a physical coding sublayer circuit 116, and an echo cancellation circuit 117. The interrogated end circuit 120 includes a medium-dependent interface circuit 121, a mixing circuit 122, a transmitting circuit 123, a receiving circuit 124, a processing circuit 125, a physical coding sublayer circuit 126, and an echo cancellation circuit 127.

In the inquiring end circuit 110, the medium-dependent interface circuit 111 is configured to be coupled to a twisted pair 102, and can transmit signals to the interrogated end circuit 120 through the twisted pair 102, or receive signals from the interrogated end circuit 120 through the twisted pair 102. The hybrid circuit 112 is configured to be coupled to the medium-dependent interface circuit 111, so as to perform various data communications with the interrogated end circuit 120 through the medium-dependent interface circuit 111.

The transmitting circuit 113 is coupled to the mixing circuit 112 and configured to generate and transmit a transmitting signal St1 to the mixing circuit 112. The receiving circuit 114 is coupled to the mixing circuit 112 and configured to receive and analyze a receiving signal Sr1 from the mixing circuit 112 to generate a data signal Sd1.

The processing circuit 115 is coupled to the receiving circuit 114 and configured to process the data signal Sd1 and control the operation of the inquiry end circuit 110. The physical coding sublayer circuit 116 is coupled to the processing circuit 115 and configured to perform a physical coding operation according to the instruction of the processing circuit 115 to control the operation of the transmitting circuit 113.

The echo cancellation circuit 117 is coupled between the output end of the transmitting circuit 113 and the input end of the receiving circuit 114, and is configured to generate an echo cancellation signal according to the transmitting signal St1 to cancel or reduce the echo component in the receiving signal Sr1. As is known to all, when the inquiry end circuit 110 operates in full duplex mode, the transmitting circuit 113 and the receiving circuit 114 operate simultaneously. In this case, the receiving signal Sr1 transmitted by the mixing circuit 112 to the receiving circuit 114 may include an echo component corresponding to the transmitting signal St1 generated by the transmitting circuit 113. Therefore, when the transmitting circuit 113 and the receiving circuit 114 operate simultaneously, the echo cancellation circuit 117 is required to generate an echo cancellation signal to cancel or reduce the echo component in the receiving signal Sr1, thereby improving the accuracy of the signal received by the receiving circuit 114.

In the interrogated end circuit 120, the medium-dependent interface circuit 121 is configured to be coupled to a twisted pair 104, and can transmit signals to the interrogating end circuit 110 through the twisted pair 104, or receive signals from the interrogating end circuit 110 through the twisted pair 104. In one embodiment, the twisted pair 102 and the twisted pair 104 are the same twisted pair. In another embodiment, the twisted pair 104 is indirectly connected to the twisted pair 102 through an intermediate circuit (e.g., an adapter, a hub, a switch). The hybrid circuit 122 is configured to be coupled to the medium-dependent interface circuit 121, so as to perform various data communications with the interrogating end circuit 110 through the medium-dependent interface circuit 121.

The transmitting circuit 123 is coupled to the mixing circuit 122 and configured to generate and transmit a transmitting signal St2 to the mixing circuit 122. The receiving circuit 124 is coupled to the mixing circuit 122 and configured to receive and analyze a receiving signal Sr2 from the mixing circuit 122 to generate a data signal Sd2.

The processing circuit 125 is coupled to the receiving circuit 124 and configured to process the data signal Sd2 and control the operation of the polled circuit 120. The physical coding sublayer circuit 126 is coupled to the processing circuit 125 and configured to perform a physical coding operation according to the instruction of the processing circuit 125 to control the operation of the transmitting circuit 123.

The echo cancellation circuit 127 is coupled between the output end of the transmitting circuit 123 and the input end of the receiving circuit 124, and is configured to generate an echo cancellation signal according to the transmitting signal St2 to eliminate or reduce the echo component in the receiving signal Sr2. Similarly, when the interrogated circuit 120 operates in the full-duplex mode, the transmitting circuit 123 and the receiving circuit 124 operate simultaneously. In this case, the receiving signal Sr2 transmitted by the mixing circuit 122 to the receiving circuit 124 may include an echo component corresponding to the transmitting signal St2 generated by the transmitting circuit 123. Therefore, when the transmitting circuit 123 and the receiving circuit 124 operate simultaneously, the echo cancellation circuit 127 is required to generate an echo cancellation signal to eliminate or reduce the echo component in the receiving signal Sr2, thereby improving the accuracy of the signal received by the receiving circuit 124.

The different functional blocks in the aforementioned interrogation end circuit 110 can be implemented by different circuits, or integrated into a single circuit or a single device. Similarly, the different functional blocks in the aforementioned interrogation end circuit 120 can be implemented by different circuits, or integrated into a single circuit or a single device. For the sake of simplicity, other circuits, components and connection relationships are omitted in FIG. 1.

In actual applications, there are many different combinations of roles played by the interrogating circuit 110 and the interrogated circuit 120. For example, one of the interrogating circuit 110 and the interrogated circuit 120 may be an automotive central controller or a local circuit of the automotive central controller, while the other may be an automotive sensing device (e.g., tire pressure detector, driving recorder, reversing radar, voice detector, physiological characteristic sensor, air quality sensor, temperature sensor, etc.), an actuator circuit of an automotive device (e.g., accelerator, brake, door, wiper, rearview mirror, sunroof, etc.), a local circuit of the automotive sensing device, or a local circuit of the actuator circuit.

In the automotive Ethernet system 100, the inquiring end circuit 110 is configured to operate in an asymmetry data mode described in the following paragraphs of this specification. If the queried end circuit 120 can also support the asymmetry data mode proposed in this specification, the inquiring end circuit 110 and the queried end circuit 120 can use the asymmetry data mode proposed in this specification when performing data communication to obtain many technical advantages.

However, whether the interrogated end circuit 120 supports the asymmetric data mode proposed in this specification is not determined by the manufacturer of the interrogating end circuit 110. For example, in some application scenarios, the interrogated end circuit 120 in the automotive Ethernet network system 100 is configured to support the asymmetric data mode proposed in this specification, but the interrogated end circuit 120 may become unable to support the asymmetric data mode proposed in this specification due to various reasons such as circuit failure, maintenance, parts replacement, and parts update. For another example, in other application scenarios, the interrogated end circuit 120 in the automotive Ethernet network system 100 cannot support the asymmetric data mode proposed in this specification, but the interrogated end circuit 120 may be able to support the asymmetric data mode proposed in this specification due to various reasons such as parts replacement or parts update.

The inquiring circuit 110 can adjust the data communication mode with the interrogated circuit 120 according to the different conditions of the interrogated circuit 120. To achieve this purpose, the inquiring circuit 110 can dynamically check whether the interrogated circuit 120 supports the asymmetric data mode proposed in this specification.

The operation of the vehicle Ethernet system 100 will be further described below with reference to FIGS. 2 to 4. FIGS. 2 to 3 are simplified flow charts of an embodiment of a data communication method used by the vehicle Ethernet system 100 of the present invention. FIG. 4 is a simplified timing diagram of different embodiments of the asymmetric data mode of the present invention.

In the flowcharts of FIGS. 2 and 3 , the process in the column to which a specific device belongs represents the process performed by the specific device. For example, the part marked in the “inquiring end circuit” column is the process performed by the inquiring end circuit 110; the part marked in the “inquired end circuit” column is the process performed by the inquired end circuit 120.

In order to establish an Ethernet link between the inquiring circuit 110 and the interrogated circuit 120 , the inquiring circuit 110 and the interrogated circuit 120 first perform a handshake procedure to exchange information and/or parameters required to establish the link.

In this case, the inquiring end circuit 110 and the queried end circuit 120 will perform the process 202 in FIG. 2 to perform link synchronization (LinkSync) operation or auto-negotiation (also known as NWay) operation. Generally speaking, the inquiring end circuit 110 and the queried end circuit 120 only need to perform one of the link synchronization operation and the auto-negotiation operation in the process 202. The manufacturer of the automotive Ethernet system 100 can set in advance whether the inquiring end circuit 110 and the queried end circuit 120 are to perform link synchronization operation or auto-negotiation operation.

When performing a synchronous operation or an automatic negotiation operation, the transmitting circuit 113 of the inquiring circuit 110 transmits a handshake signal that complies with the automotive Ethernet communication protocol to the interrogated circuit 120, and the transmitting circuit 123 of the interrogated circuit 120 transmits a handshake signal that complies with the automotive Ethernet communication protocol to the inquiring circuit 110. On the other hand, the receiving circuit 114 of the inquiring circuit 110 receives the handshake signal from the interrogated circuit 120, and the receiving circuit 124 of the interrogated circuit 120 receives the handshake signal from the inquiring circuit 110.

As mentioned above, the inquiring circuit 110 can adjust the data communication method with the queried circuit 120 according to different conditions of the queried circuit 120 .

In this embodiment, in order to confirm whether the interrogated circuit 120 supports the asymmetric data mode proposed in this specification, the inquiring circuit 110 performs process 204 before entering a training mode after completing the link synchronization operation or the automatic negotiation operation.

In process 204, the physical coding sublayer circuit 116 controls the transmission circuit 113 to generate an asymmetry mode identification signal to indicate that the inquiring end circuit 110 can support an asymmetric data mode proposed in this specification. In process 204, the transmission circuit 113 also transmits the asymmetry mode identification signal to the inquired end circuit 120 through the hybrid circuit 112 and the medium-dependent interface circuit 111.

The aforementioned asymmetric pattern recognition signal can be implemented by a signal including a predetermined pattern or a signal having a predetermined format. Alternatively, the aforementioned asymmetric pattern recognition signal can also be implemented by a signal including a predetermined value, a predetermined random code, a predetermined flag, and/or a predetermined identification data.

Next, the interrogated circuit 120 performs a process 206 , and the inquiring circuit 110 performs a process 208 .

In process 206 , the receiving circuit 124 of the interrogated circuit 120 receives the asymmetric pattern recognition signal from the inquiring circuit 110 through the medium dependent interface circuit 121 and the mixing circuit 122 .

If the interrogated circuit 120 can support the asymmetric data mode proposed in this specification, then the receiving circuit 124 should be able to correctly interpret the asymmetric mode identification signal transmitted from the inquiring circuit 110. In this case, the processing circuit 125 of the interrogated circuit 120 can perform the process 304 in FIG. 3 . In other words, if the interrogated circuit 120 can interpret the asymmetric mode identification signal transmitted from the inquiring circuit 110 and can support the asymmetric data mode proposed in this specification, the processing circuit 125 will perform the process 304 in FIG. 3 . In the process 304, the physical coding sublayer circuit 126 will control the transmitting circuit 123 to generate a predetermined response signal (predetermined response signal) to indicate that the interrogated circuit 120 can support an asymmetric data mode proposed in this specification.

The predetermined response signal may be implemented by a signal including a predetermined pattern or a signal having a predetermined format. Alternatively, the predetermined response signal may be implemented by a signal including a predetermined target value, a predetermined target flag, and/or a predetermined target data.

In addition, in the process 304 , the transmitting circuit 123 may also transmit the predetermined response signal to the inquiry end circuit 110 via the mixing circuit 122 and the medium related interface circuit 121 .

On the contrary, if the receiving circuit 124 cannot interpret the asymmetric mode identification signal sent by the inquiring circuit 110 or the interrogated circuit 120 does not support the asymmetric data mode proposed in this specification, the processing circuit 125 of the interrogated circuit 120 will perform the process 212 in FIG. 2 .

On the other hand, as shown in FIG. 2 , after the inquiry end circuit 110 transmits the asymmetric pattern identification signal to the query end circuit 120 , the process 208 is performed.

In process 208, the receiving circuit 114 of the inquiring circuit 110 waits for and receives a signal from the interrogated circuit 120. In addition, the inquiring circuit 110 further determines whether the interrogated circuit 120 can support the asymmetric data mode proposed in this specification based on the subsequent signal from the interrogated circuit 120.

After the inquiring circuit 110 and the interrogated circuit 120 complete the connection synchronization operation or the automatic negotiation operation, if the receiving circuit 114 receives the aforementioned predetermined response signal from the interrogated circuit 120 before the inquiring circuit 110 and the interrogated circuit 120 start to enter the training mode, the processing circuit 115 can determine that the interrogated circuit 120 can support the asymmetric data mode proposed in this specification.

For example, in this embodiment, if the interrogated circuit 120 transmits the aforementioned predetermined response signal to the inquiring circuit 110 within a predetermined time length after the inquiring circuit 110 sends the aforementioned asymmetric mode identification signal, the processing circuit 115 of the inquiring circuit 110 can determine that the interrogated circuit 120 can support the asymmetric data mode proposed in this specification. The aforementioned predetermined time length can be the time length required for receiving a predetermined number of signals.

On the contrary, if the interrogated circuit 120 does not send the predetermined response signal to the inquiring circuit 110 within the predetermined time period, the processing circuit 115 of the inquiring circuit 110 will determine that the interrogated circuit 120 cannot support the asymmetric data mode proposed in this specification.

For example, the processing circuit 115 may start to count the number of signals transmitted from the interrogated circuit 120 after the transmitting circuit 113 transmits an asymmetric mode identification signal to the interrogated circuit 120. If the receiving circuit 114 receives a predetermined response signal from the interrogated circuit 120 before the number of signals received from the interrogated circuit 120 reaches a predetermined number, the processing circuit 115 will perform the process 308 in FIG. 3 to determine whether the interrogated circuit 120 can support the asymmetric data mode proposed in this specification.

On the contrary, if the receiving circuit 114 receives the predetermined number of signals but still does not receive the predetermined response signal from the interrogated circuit 120, the processing circuit 115 will perform the process 210 in Figure 2 to determine that the interrogated circuit 120 cannot support the asymmetric data mode proposed in this specification, and then perform the process 212.

In practice, the aforementioned predetermined time length may also be changed to a fixed time length, for example, 0.5 seconds, 1 second, 1.5 seconds, 2.0 seconds, 2.5 seconds, 3.0 seconds, etc.

In process 212, the inquiring end circuit 110 and the interrogated end circuit 120 operate in a training mode to perform a signal training operation. In other words, the action of the inquiring end circuit 110 transmitting the asymmetric pattern recognition signal to the interrogated end circuit 120 is performed before the inquiring end circuit 110 and the interrogated end circuit 120 perform the signal training operation. During the operation, one of the inquiring end circuit 110 and the interrogated end circuit 120 may play the role of a master device, and the other may play the role of a slave device. In process 212, the master device may transmit a training data signal to the slave device, and the slave device may perform a timing recovery operation according to the training data signal transmitted from the master device to correct the frequency and/or phase of the internal working clock of the slave device, so that the working clocks between the master device and the slave device can be synchronized.

In other words, the signal training operation performed by the inquiring circuit 110 and the interrogated circuit 120 in the process 212 can enable the working clocks of the inquiring circuit 110 and the interrogated circuit 120 to be synchronized.

As shown in FIG3 , after the inquiring circuit 110 and the queried circuit 120 complete the signal training operation in process 212, the inquiring circuit 110 and the queried circuit 120 will perform process 302 to operate in a traditional symmetry data mode. According to the specification of the traditional automotive Ethernet communication protocol, the aforementioned symmetry data mode is a full duplex mode.

In other words, in process 302, the inquiring end circuit 110 can perform data transmission and data reception at the same time. Similarly, the interrogated end circuit 120 can also perform data transmission and data reception at the same time. Therefore, the inquiring end circuit 110 and the interrogated end circuit 120 can transmit data to each other at the same time, and can also receive data from each other at the same time.

As mentioned above, if the interrogated circuit 120 is able to interpret the asymmetric mode identification signal transmitted by the inquiring circuit 110 and can support the asymmetric data mode proposed in this specification, the interrogated circuit 120 will perform the process 304 in Figure 3 to transmit a predetermined response signal to the inquiring circuit 110 representing that the interrogated circuit 120 can support the asymmetric data mode.

In this case, the receiving circuit 114 of the inquiring circuit 110 performs the process 306 to receive the predetermined response signal transmitted from the interrogated circuit 120 through the medium dependent interface circuit 111 and the mixing circuit 112 .

As can be seen from the above description, if the receiving circuit 114 receives a predetermined response signal from the interrogated circuit 120 within a predetermined time length after the inquiring circuit 110 sends the asymmetric mode identification signal, the processing circuit 115 of the inquiring circuit 110 will perform process 308 to determine that the interrogated circuit 120 is capable of supporting the asymmetric data mode proposed in this specification, and then perform process 310.

In process 310, the inquiring circuit 110 can operate in an asymmetry data mode proposed in this specification with the interrogated circuit 120 under the control of the processing circuit 115 to perform various data communications between each other. That is, only when the processing circuit 115 determines that the interrogated circuit 120 can support the asymmetry data mode, the processing circuit 115 will control the inquiring circuit 110 to operate in the asymmetry data mode. In other words, the action of the interrogated circuit 120 transmitting the predetermined response signal to the inquiring circuit 110 is after the inquiring circuit 110 and the interrogated circuit 120 complete the connection synchronization operation or the automatic negotiation operation.

In some embodiments, the inquiring circuit 110 and the interrogated circuit 120 may also perform a signal training operation as described in the aforementioned process 212 between the process 308 and the process 310, so that the working clocks between the inquiring circuit 110 and the interrogated circuit 120 can be synchronized. At this time, the processing circuit 115 controls the inquiring circuit 110 and the interrogated circuit 120 to perform the signal training operation.

Please note that the asymmetric data mode proposed in this specification is not a data mode specified by the conventional automotive Ethernet communication protocol, and therefore is not a full-duplex mode.

For example, FIG4 shows simplified timing diagrams of two different embodiments of the asymmetric data mode of the present invention, including a timing diagram of a first asymmetric data mode 410 and a timing diagram of a second asymmetric data mode 420. In FIG4, "Dumb" means "the transmitting end does not send a signal"; "Blind" means "the receiving end does not receive a signal".

In the first asymmetric data pattern 410, each data transmission cycle 411 includes a first data transmission period 413, a second data transmission period 415, and a plurality of other purpose periods, wherein the first data transmission period 413 and the second data transmission period 415 do not overlap each other, and the time length of the first data transmission period 413 is greater than the time length of the second data transmission period 415. The time length of the first data transmission period 413 can be 2 times, 2.5 times, 3 times, or more than 3 times that of the second data transmission period 415.

In the second asymmetric data pattern 420, each data transmission cycle 421 includes a first data transmission period 423, a second data transmission period 425, and a plurality of other purpose periods, wherein the first data transmission period 423 and the second data transmission period 425 do not overlap each other, and the duration of the first data transmission period 423 is shorter than the duration of the second data transmission period 425. The duration of the second data transmission period 425 can be 2 times, 2.5 times, 3 times, or more than 3 times of the first data transmission period 423.

In one embodiment, the inquiring circuit 110 and the interrogated circuit 120 may operate in a first asymmetric data mode 410. In this case, the transmitting circuit 113 of the inquiring circuit 110 transmits data to the interrogated circuit 120 in the first data transmission period 413, but does not transmit data to the interrogated circuit 120 in the second data transmission period 415. On the other hand, the transmitting circuit 123 of the interrogated circuit 120 transmits data to the inquiring circuit 110 in the second data transmission period 415, but does not transmit data to the inquiring circuit 110 in the first data transmission period 413.

In the first asymmetric data pattern 410, in order to cooperate with the data transmission timing of the interrogated circuit 120, the receiving circuit 114 of the inquiring circuit 110 will receive the data transmitted from the interrogated circuit 120 in the second data transmission period 415, but will not receive the data transmitted from the interrogated circuit 120 in the first data transmission period 413. On the other hand, in order to cooperate with the data transmission timing of the inquiring circuit 110, the receiving circuit 114 of the interrogated circuit 120 will receive the data transmitted from the inquiring circuit 110 in the first data transmission period 413, but will not receive the data transmitted from the inquiring circuit 110 in the second data transmission period 415.

In other words, the data transmission period and data receiving period of the inquiry end circuit 110 are staggered and do not overlap each other. Similarly, the data transmission period and data receiving period of the inquiry end circuit 120 are staggered and do not overlap each other.

In another embodiment, the inquiring circuit 110 and the interrogated circuit 120 may operate in the second asymmetric data mode 420. In this case, the transmitting circuit 113 of the inquiring circuit 110 transmits data to the interrogated circuit 120 in the second data transmission period 425, but does not transmit data to the interrogated circuit 120 in the first data transmission period 423. On the other hand, the transmitting circuit 123 of the interrogated circuit 120 transmits data to the inquiring circuit 110 in the first data transmission period 423, but does not transmit data to the inquiring circuit 110 in the second data transmission period 425.

In the second asymmetric data pattern 410, in order to cooperate with the data transmission timing of the interrogated circuit 120, the receiving circuit 114 of the inquiring circuit 110 will receive the data transmitted from the interrogated circuit 120 in the first data transmission period 423, but will not receive the data transmitted from the interrogated circuit 120 in the second data transmission period 425. On the other hand, in order to cooperate with the data transmission timing of the inquiring circuit 110, the receiving circuit 114 of the interrogated circuit 120 will receive the data transmitted from the inquiring circuit 110 in the second data transmission period 425, but will not receive the data transmitted from the inquiring circuit 110 in the first data transmission period 423.

It can be seen from the above description that the first asymmetric data mode 410 and the second asymmetric data mode 420 are not full-duplex modes specified by the conventional automotive Ethernet communication protocol.

In applications where the amount of data to be transmitted by the inquiring circuit 110 is greater than that of the interrogated circuit 120 , the inquiring circuit 110 and the interrogated circuit 120 may operate in the first asymmetric data mode 410 in the process 310 to improve data transmission efficiency.

On the contrary, in applications where the amount of data to be transmitted by the interrogated circuit 120 is greater than that of the inquiring circuit 110 , the inquiring circuit 110 and the interrogated circuit 120 may operate in the second asymmetric data mode 420 in the process 310 to improve data transmission efficiency.

During operation, the inquiring circuit 110 and the queried circuit 120 can also dynamically switch between the aforementioned first asymmetric data mode 410 and the second asymmetric data mode 420 when the data transmission volume of both parties changes significantly.

In actual applications, the amount of data that needs to be transmitted between the inquiring end circuit 110 and the interrogated end circuit 120 in the automotive Ethernet system 100 is often unequal, and may even differ greatly. Therefore, if the inquiring end circuit 110 uses the confirmation mechanism in the aforementioned flow chart 2 and FIG. 3 to determine that the interrogated end circuit 120 can support the asymmetric data mode proposed in this specification, the asymmetric data mode proposed in this specification can be used to replace the traditional symmetric data mode.

In this way, not only the data transmission efficiency between the inquiring end circuit 110 and the queried end circuit 120 can be greatly improved, but also the bandwidth utilization rate between the inquiring end circuit 110 and the queried end circuit 120 can be effectively improved.

In addition, as mentioned above, when the transmitting circuit 113 and the receiving circuit 114 in the interrogating circuit 110 are operated simultaneously, the echo cancellation circuit 117 is required to generate an echo cancellation signal to improve the accuracy of the signal received by the receiving circuit 114. Similarly, when the transmitting circuit 123 and the receiving circuit 124 in the interrogated circuit 120 are operated simultaneously, the echo cancellation circuit 127 is required to generate an echo cancellation signal to improve the accuracy of the signal received by the receiving circuit 124.

However, it can be seen from the above description that when the inquiring circuit 110 and the interrogated circuit 120 operate in the asymmetric data mode proposed in this specification (for example, the first asymmetric data mode 410 or the second asymmetric data mode 420 mentioned above), the transmitting circuit 113 and the receiving circuit 114 in the inquiring circuit 110 will not operate at the same time, and the transmitting circuit 123 and the receiving circuit 124 in the interrogated circuit 120 will not operate at the same time.

Therefore, when the inquiring end circuit 110 operates in the asymmetric data mode, the echo cancellation circuit 117 in the inquiring end circuit 110 can be temporarily turned off, so that the echo cancellation circuit 117 stops operating. Similarly, when the interrogated end circuit 120 operates in the asymmetric data mode, the echo cancellation circuit 127 in the interrogated end circuit 120 can be temporarily turned off, so that the echo cancellation circuit 127 stops operating. In this way, the power consumption of the inquiring end circuit 110 and the power consumption of the interrogated end circuit 120 can be effectively saved.

Furthermore, since the action of the inquiring end circuit 110 transmitting the asymmetric pattern identification signal to the interrogated end circuit 120 (and the action of the interrogated end circuit 120 transmitting the predetermined response signal to the inquiring end circuit 110) is performed after the inquiring end circuit 110 and the interrogated end circuit 120 complete the connection synchronization operation (or automatic negotiation operation), it will not interfere with the connection synchronization operation (or automatic negotiation operation) between the inquiring end circuit 110 and the interrogated end circuit 120. This method can effectively avoid significantly increasing the overall control complexity of the automotive Ethernet system 100.

Obviously, the aforementioned inquiring end circuit 110 will dynamically check whether the queried end circuit 120 supports the asymmetric data mode proposed in this specification, and can adjust the data communication method with the queried end circuit 120 according to the different conditions of the queried end circuit 120. Such a mechanism allows the inquiring end circuit 110 to have greater application flexibility in working with different queried end circuits.

Certain words are used in the specification and claims to refer to specific components, while those skilled in the art may use different terms to refer to the same components. This specification and claims do not use differences in names as a way to distinguish components, but use differences in the functions of the components as the basis for distinction. The term "including" mentioned in the specification and claims is an open-ended term and should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect connection means. Therefore, if the text describes a first circuit coupled to a second circuit, it means that the first circuit can be directly connected to the second circuit through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or can be indirectly electrically or signal connected to the second circuit through other devices or connection means.

The description method of "and/or" used in the specification includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular term also includes the meaning of the plural term.

The above are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims (10)

1. An inquiry end circuit (110), comprising: A hybrid circuit (112) configured to perform data communication with an interrogated end circuit (120) via a medium-dependent interface circuit (111); A transmission circuit (113), coupled to the mixing circuit (112), configured to generate and transmit a transmission signal (St1) to the mixing circuit (112); A receiving circuit (114), coupled to the mixing circuit (112), configured to receive and analyze a receiving signal (Sr1) transmitted from the mixing circuit (112) to generate a data signal (Sd1); a processing circuit (115), coupled to the receiving circuit (114), configured to process the data signal (Sd1); a physical coding sublayer circuit (116), coupled to the processing circuit (115), configured to perform a physical coding operation to control the operation of the transmission circuit (113); and An echo cancellation circuit (117) is coupled between the transmitting circuit (113) and the receiving circuit (114) and is configured to generate an echo cancellation signal. 2. The inquiring end circuit (110) as claimed in claim 1, wherein, after the inquiring end circuit (110) and the inquired end circuit (120) complete a line synchronization operation or an automatic negotiation operation, if the receiving circuit (114) receives a predetermined response signal from the inquired end circuit (120) before the inquiring end circuit (110) and the inquired end circuit (120) perform a signal training operation, the processing circuit (115) determines that the inquired end circuit (120) can support an asymmetric data mode. 3. The inquiring end circuit (110) as described in claim 2, wherein the processing circuit (115) controls the inquiring end circuit (110) to operate in the asymmetric data mode only when the processing circuit (115) determines that the queried end circuit (120) can support the asymmetric data mode. 4. The inquiring end circuit (110) as claimed in claim 2, wherein before the inquiring end circuit (110) operates in the asymmetric data mode, the processing circuit (115) controls the inquiring end circuit (110) to first perform the signal training operation with the interrogated end circuit (120). 5. The inquiry end circuit (110) as claimed in claim 2, wherein when the inquiry end circuit (110) operates in the asymmetric data mode, the echo cancellation circuit (117) stops operating. 6. The inquiring end circuit (110) as claimed in claim 2, wherein when the inquiring end circuit (110) operates in the asymmetric data mode, the transmitting circuit (113) transmits data to the interrogated end circuit (120) in a first data transmission period (413), and the receiving circuit (114) receives the data transmitted by the interrogated end circuit (120) in a second data transmission period (415); The first data transmission period (413) and the second data transmission period (415) do not overlap each other, the transmitting circuit (113) will not transmit data to the queried end circuit (120) in the second data transmission period (415), and the receiving circuit (114) will not receive data transmitted from the queried end circuit (120) in the first data transmission period (413). 7. The inquiry end circuit (110) as claimed in claim 6, wherein the first data transmission period (413) and the second data transmission period (415) have different durations. 8. The inquiring end circuit (110) as claimed in claim 2, wherein, after the inquiring end circuit (110) and the interrogated end circuit (120) complete the line synchronization operation or the automatic negotiation operation, the physical coding sublayer circuit (116) controls the transmission circuit (113) to generate an asymmetric mode identification signal representing that the inquiring end circuit (110) can support the asymmetric data mode, and before the inquiring end circuit (110) and the interrogated end circuit (120) perform the signal training operation, the asymmetric mode identification signal is transmitted to the interrogated end circuit (120) through the mixing circuit (112) and the medium-dependent interface circuit (111). 9. The inquiring end circuit (110) as claimed in claim 8, wherein, after the inquiring end circuit (110) transmits the asymmetric mode identification signal to the interrogated end circuit (120), if the receiving circuit (114) receives a predetermined number of signals from the interrogated end circuit (120) but has not received a predetermined response signal from the interrogated end circuit (120), then the processing circuit (115) determines that the interrogated end circuit (120) cannot support the asymmetric data mode. 10. The inquiring end circuit (110) as claimed in claim 9, wherein, after the processing circuit (115) determines that the interrogated end circuit (120) cannot support the asymmetric data mode, the processing circuit (115) controls the inquiring end circuit (110) to start the signal training operation with the interrogated end circuit (120), and after the inquiring end circuit (110) and the interrogated end circuit (120) complete the signal training operation, the processing circuit (115) controls the inquiring end circuit (110) to operate in a symmetric data mode.