CN118131006A

CN118131006A - ATPG test vector simplifying method and device, storage medium and electronic device

Info

Publication number: CN118131006A
Application number: CN202410106163.1A
Authority: CN
Inventors: 蔺欣瑶; 叶靖
Original assignee: Zhongke Jianxin Beijing Technology Co ltd
Current assignee: Zhongke Jianxin Beijing Technology Co ltd
Priority date: 2024-01-25
Filing date: 2024-01-25
Publication date: 2024-06-04

Abstract

The application discloses a method and a device for simplifying ATPG test vectors, a storage medium and an electronic device. Wherein the method comprises the following steps: and taking out target faults which are not automatically generated by the test vectors from the fault list, if N first test cubes (namely incompatible test cubes generated after combination) do not exist in the vector cache, generating a second test cube for the target faults by adopting an unconstrained single fault test generation mode, if the second test cubes exist, generating a second test cube which accords with the first constraint for the target faults according to the single fault test generation mode, combining the generated second test cubes with the N first test cubes, and writing the combined second test cubes into the vector cache.

Description

ATPG test vector simplifying method and device, storage medium and electronic device

Technical Field

The application relates to the field of testability design of chips, in particular to a method and a device for simplifying ATPG test vectors, a storage medium and an electronic device.

Background

This section is intended to provide a background or context for the matter recited in the claims or specification, which is not admitted to be prior art by inclusion in this section.

With the increasing chip scale, electronic design automation (Electronic Design Automation, EDA) tools are becoming indispensable in the field of chip design. In the actual chip generation process, defects are unavoidable, and in order to detect defects in chip manufacturing as early as possible, a design for testability (Desing For Testability, DFT) method becomes an important process in chip design. The Automatic TEST PATTERN Generation (ATPG) method generates a test vector for a chip to be tested in a design stage, the chip is loaded on an Automatic tester (Automaci Test Equipment, ATE) after manufacturing is completed, and the previously generated vector is applied to a machine to detect defects in the chip. Test application time (Test Application Time, TAT) and Test Volume (TV) are important indicators for evaluating the quality of Test vectors generated by ATPG.

In order to generate high-quality test vectors and reduce test costs, in recent years, many test-reduction-oriented test vector generation methods have been proposed. The structured ATPG method will generate one test cube for a single fault, the test cube being a test vector containing X bits (X is the uncertainty bit, towards one concept opposite to the uncertainty bit, 0 and 1 are the uncertainty bits), the test compaction mainstream method aims at exploring the filling of multiple test cubes of different faults into one compact test cube, one mainstream method being test merging.

The test merging method simplifies the test vector by searching the compatibility of the local test vector, specifically, each time a test cube is generated, the test cube is temporarily stored through a certain structure, the information about the compatibility is also calculated and stored in a specific structure, after m test cubes are generated, the test merging method compatibly merges the generated m test cubes into n (n < m) test cubes by utilizing the previously maintained compatibility information, so that the test is simplified, and the test merging algorithm can quickly simplify the test.

In view of the above problems, no effective solution has been proposed at present.

Disclosure of Invention

The embodiment of the application provides a method and a device for simplifying an ATPG test vector, a storage medium and an electronic device, which are used for at least solving the technical problem of low test vector generation efficiency.

According to an aspect of an embodiment of the present application, there is provided a method for simplifying an ATPG test vector, including: taking out a target fault from a fault list, wherein a plurality of faults of a target chip, which need to be tested, are stored in the fault list, and the target fault is a fault which does not generate an automatic test vector; generating a second test cube for the target fault by adopting an unconstrained single fault test generation mode under the condition that N first test cubes do not exist in the vector cache, wherein the N first test cubes are incompatible test cubes generated after combination, and N bits are preset integers larger than 2; generating a second test cube conforming to a first constraint for the target fault according to a single fault test generation mode under the condition that N first test cubes exist in the vector cache, wherein the first constraint is generated according to the N first test cubes and is used for avoiding the generated test cubes from entering conflict spaces of the N first test cubes; and merging the generated second test cubes with the N first test cubes, and writing the merged second test cubes into the vector cache.

Optionally, before generating the second test cube conforming to the first constraint for the target fault in a single fault test generation manner, the method further includes: acquiring bit vectors at the same positions in the N first test cubes, wherein each test cube in the N first test cubes is a vector comprising M bit vectors, and M is a preset positive integer; and generating the first constraint according to the relation between bit vectors at the same positions in the N first test cubes, wherein the bit number M of the first constraint.

Optionally, generating the first constraint according to a relationship between bit vectors at the same positions in the N first test cubes includes: crossing bit vectors at the same position in the N first test cubes according to a preset rule to obtain crossing results at the position; and combining intersection results of all positions in the N first test cubes according to the sequence of the positions to obtain the first constraint.

Optionally, intersecting bit vectors at the same position in the N first test cubes according to a preset rule to obtain an intersecting result of the position, including: and intersecting bit vectors at the same position in the N first test cubes according to the preset rule shown as follows to obtain intersecting results of the position: x & x=x, 1&X =x, 0&X =x, 1&0 =x, 0&0 =0, 1& 1=1, where X represents an uncertain bit and 1 and 0 represent a certain bit.

Optionally, merging the generated second test cube with the N first test cubes and writing the merged second test cubes into the vector cache, including: detecting whether the second test cube conflicts with the N first test cubes; and merging and writing the second test cube and the first test cubes which do not conflict into the vector cache under the condition that the first test cubes which do not conflict with the second test cube exist in the N first test cubes.

Optionally, after detecting whether the second test cube collides with the N first test cubes, the method further comprises: under the condition that the N first test cubes collide with the second test cubes, writing the target faults back to the fault list, and updating the merging failure times of the vector cache; and under the condition that the merging failure times reach the preset times, no new test cubes are written into the vector cache.

Optionally, after merging the generated second test cube with the N first test cubes and writing into the vector cache, the method further comprises: and intersecting bit vectors at the same position in the second test cube and the first constraint according to a preset rule, and taking the obtained intersection result as a second constraint.

According to another aspect of the embodiment of the present application, there is also provided a simplifying apparatus for ATPG test vectors, including: the fault selection module is used for taking out a target fault from a fault list, wherein a plurality of faults of a target chip, which need to be tested, are stored in the fault list, and the target fault is a fault which does not generate an automatic test vector; the first generation module is used for generating a second test cube for the target fault by adopting an unconstrained single fault test generation mode under the condition that N first test cubes do not exist in the vector cache, wherein the N first test cubes are incompatible test cubes generated after combination, and N bits are preset integers which are larger than 2; the second generation module is used for generating a second test cube conforming to a first constraint for the target fault according to a single fault test generation mode under the condition that N first test cubes exist in the vector cache, wherein the first constraint is generated according to the N first test cubes and is used for avoiding the generated test cubes from entering conflict spaces of the N first test cubes; and the writing module is used for merging the generated second test cubes with the N first test cubes and writing the merged second test cubes into the vector cache.

Optionally, the apparatus further includes: a constraint generation module for: before a second test cube conforming to a first constraint is generated for the target fault according to a single fault test generation mode, bit vectors at the same positions in the N first test cubes are obtained, wherein each test cube in the N first test cubes is a vector comprising M bit vectors, and M is a preset positive integer; and generating the first constraint according to the relation between bit vectors at the same positions in the N first test cubes, wherein the bit number M of the first constraint.

Optionally, the constraint generating module is further configured to: crossing bit vectors at the same position in the N first test cubes according to a preset rule to obtain crossing results at the position; and combining intersection results of all positions in the N first test cubes according to the sequence of the positions to obtain the first constraint.

Optionally, the constraint generating module is further configured to: and intersecting bit vectors at the same position in the N first test cubes according to the preset rule shown as follows to obtain intersecting results of the position: x & x=x, 1&X =x, 0&X =x, 1&0 =x, 0&0 =0, 1& 1=1, where X represents an uncertain bit and 1 and 0 represent a certain bit.

Optionally, the writing module is further configured to: detecting whether the second test cube conflicts with the N first test cubes; and merging and writing the second test cube and the first test cubes which do not conflict into the vector cache under the condition that the first test cubes which do not conflict with the second test cube exist in the N first test cubes.

Optionally, the writing module is further configured to: after detecting whether the second test cube conflicts with the N first test cubes, writing the target fault back to the fault list and updating the merging failure times of the vector cache under the condition that the N first test cubes conflict with the second test cubes; and under the condition that the merging failure times reach the preset times, no new test cubes are written into the vector cache.

Optionally, the writing module is further configured to: after merging the generated second test cube and the N first test cubes and writing the merged second test cubes into the vector cache, carrying out intersection on bit vectors at the same positions in the second test cube and the first constraint according to a preset rule, and taking an obtained intersection result as a second constraint.

According to another aspect of the embodiments of the present application, there is also provided a storage medium including a stored program that executes the above-described method when running.

According to another aspect of the embodiments of the present application, there is also provided an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor executing the method described above by the computer program.

According to one aspect of the present application, there is provided a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the steps of any of the embodiments of the method described above.

In the embodiment of the application, a target fault which is not automatically generated by a test vector is taken out from a fault list, under the condition that N first test cubes (namely, incompatible test cubes generated after combination) do not exist in a vector cache, an unconstrained single fault test generation mode is adopted to generate a second test cube for the target fault, under the condition that N first test cubes exist in the vector cache, a second test cube conforming to the first constraint is generated for the target fault according to the single fault test generation mode, the first constraint is a common constraint which is generated according to the N first test cubes and is used for preventing the generated test cubes from entering conflict spaces of the N first test cubes, the generated second test cubes and the N first test cubes are combined and then written into the vector cache, so that the generation of a simplified test vector based on the common constraint is realized, the invalid vector generated by ATPG is reduced, the success rate of the generation of the test vector and the vector quality are improved, the technical problem that the generation efficiency of the test vector is lower is solved, and the test vector is generated within a shorter time.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a flow chart of an alternative method of simplifying ATPG test vectors in accordance with embodiments of the present application;

FIG. 2 is a schematic diagram of an alternative ATPG test vector reduction scheme in accordance with an embodiment of the present application;

FIG. 3 is a schematic diagram of an alternative ATPG test vector merging scheme in accordance with an embodiment of the present application;

FIG. 4 is a schematic diagram of the common constraints of an alternative ATPG test vector in accordance with an embodiment of the present application;

FIG. 5 is a schematic diagram of an alternative collision space for ATPG test vectors in accordance with an embodiment of the present application;

FIG. 6 is a schematic diagram of an alternative ATPG test vector reduction apparatus in accordance with an embodiment of the present application;

Fig. 7 is a block diagram of a structure of a terminal according to an embodiment of the present application.

Detailed Description

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In automatic test vector generation ATPG, a test cube (test cube) is a concept for describing a test pattern. The test cube is a multi-dimensional boolean vector representing the combination of values of the various input signals in the test pattern. The test cube is typically made up of several components: input Variables (Input Variables): these variables represent the input signals of the circuit to be tested. Each input variable may take a number of possible values, typically 0 and 1. Output Variables (Output Variables): these variables represent the output signal of the circuit to be tested. Each output variable may take a number of possible values, typically 0 and 1. Control variable (Control Variables): these variables are used to control the generation and execution of test patterns. They can affect the dimensions of the test cube and the coverage of the test pattern. Dimension (Dimensions): the dimension of the test cube refers to the number of input variables contained in the test pattern. Each dimension corresponds to an input variable. Value combination (Value Combinations): each dimension in the test cube may take a number of possible combinations of values. By traversing different combinations of values, different test patterns can be generated.

The goal of the test cube is to cover as much as possible the functionality and faults of the circuit to be tested. By generating different test patterns and applying these patterns on the circuit, faults and errors in the circuit can be detected. The design and generation of test cubes is an important task in automatic test vector generation to ensure high quality test coverage and fault detection capability.

After analyzing the related art, the inventor realizes that the maximum clique (maximum clique refers to a complete subgraph with the maximum number of top points in a given graph, the complete subgraph refers to that each pair of top points are connected by edges, the maximum clique is found to be an important problem in graph theory, and the method has wide application in the fields of social network analysis, bioinformatics, scheduling and the like, and the maximum clique problem is regarded as an NP difficult problem, which means that no known efficient algorithm can be solved in polynomial time for a large-scale graph at present, vector cache and the like are used for locally merging test cubes generated by ATPG. The maximum clique method regards the test merging problem as a maximum clique problem, each node on the graph is a test cube, and if the test cubes can be merged, an edge exists between the test cubes; in the ATPG process, one node is added to the graph every time a test cube is generated, and then the edges of the graph are updated by using an algorithm for solving the maximum clique; finally, the maximum number of clusters in the graph is equal to the number of test cubes after merging. The vector cache method maintains N caches that hold compatible test cubes, and when the number of incompatible test cubes is equal to N, different heuristic strategies may decide to continue generating or writing out test vectors. These methods may be given a certain termination limit (abort) and when the test cube that attempted to merge and failed reaches the termination limit, the test cube generated by the ATPG system at this stage is determined, the remaining X bits are randomly populated, and then a fault simulation is run to determine the fault detected by the generated test vector.

Although the above-mentioned method can merge test vectors, it is unavoidable that a large number of test cubes which cannot be merged due to collision are generated, the generation of these test cubes is meaningless, a large number of invalid ATPGs exist, a large number of easy-to-test faults exist in early stages of test generation, the test cubes generated by these faults are easy to merge, but as the generation of the test vectors proceeds, most of easy-to-test faults are detected, because easy-to-test faults are easily detected accidentally by the test vectors filled with X randomly, and in the middle and later stages of test generation, the test cubes generated by the rest faults are difficult to be compatible, and effective merging is often not generated, so that the utility of the test merging algorithm is greatly weakened.

Previous methods, which do not use any deterministic method to mitigate this but rather prefer to use heuristic algorithms, generate a large number of test cubes that cannot be merged with either vector cache, or either maximum clique. Based on this, according to an aspect of the embodiment of the present application, a method embodiment of a method for simplifying an ATPG test vector is provided. This phenomenon can be alleviated by deterministic methods, by analyzing test cubes in the vector cache that have been generated, the necessary constraints of some subsequent ATPGs can be identified, in which these constraints will be assigned to the ATPG circuit model, under which the ATPG will generate test vectors for faults.

Fig. 1 is a flowchart of an alternative method for simplifying ATPG test vectors according to an embodiment of the present application, as shown in fig. 1, the method can comprise the following steps:

Step S102, the target faults are taken out from a fault list, a plurality of faults of the target chip, which need to be tested, are stored in the fault list, and the target faults are faults which do not successfully perform automatic test vector generation.

Prior to performing the subsequent steps, common constraints need to be pre-generated: acquiring bit vectors (each bit vector can be a determined bit 1 or 0 or an uncertain bit X) at the same position in N first test cubes, wherein each test cube in the N first test cubes is a vector comprising M bit vectors, and M is a preset positive integer; generating a first constraint according to the relation between bit vectors at the same positions in the N first test cubes, wherein the first constraint is a common constraint with the number of bits being M, for example, intersection is carried out on the bit vectors at the same positions in the N first test cubes according to a preset rule (X & X=X, 1&X =X, 0&X =X, 1&0 =X, 0&0 =0, 1& 1=1) to obtain intersection results of the positions; and combining intersection results of all the positions in the N first test cubes according to the sequence of the positions to obtain first constraint.

Step S104, under the condition that N first test cubes do not exist in the vector cache, generating a second test cube for the target fault by adopting an unconstrained single fault test generation mode, wherein the N first test cubes are incompatible test cubes generated after combination, and N bits are preset integers larger than 2.

The number of vector caches may be plural, and if writing fails in one vector cache, processing may be performed in the other vector cache according to the same flow (e.g. step S104-step S108), and processing in one vector cache will be described as an example.

For the first test cube of the vector cache, the first test cube is directly stored, for the subsequent ith test cube (i is smaller than N), merging with other test cubes in the vector cache is tried, if merging is successful, the number of the test cubes in the vector cache is kept unchanged, and otherwise, 1 is added.

In step S106, in the case that N first test cubes exist in the vector cache, a second test cube conforming to a first constraint is generated for the target fault according to the single fault test generation mode, where the first constraint is generated according to the N first test cubes, and the first constraint is used to avoid the generated test cubes entering conflict spaces of the N first test cubes (i.e. solution spaces that must conflict with all test cubes in the test cubes).

And S108, merging the generated second test cubes with the N first test cubes, and writing the merged second test cubes into a vector cache.

In the scheme, whether the second test cube conflicts with the N first test cubes or not is detected; in the case that there is a first test cube of the N first test cubes that does not conflict with a second test cube, the second test cube is merged with the first test cubes that do not conflict and written into the vector cache.

After detecting whether the second test cube conflicts with the N first test cubes, under the condition that the N first test cubes conflict with the second test cubes, writing the target fault back to the fault list, and updating the merging failure times of the vector cache; and under the condition that the merging failure times reach the preset times, a new test cube is not written in the vector cache.

After merging the generated second test cube and N first test cubes and writing the merged second test cubes into a vector cache, intersecting bit vectors at the same positions in the second test cube and the first constraint according to a preset rule, and taking the obtained intersecting result as a second constraint.

Through the steps, the target faults which are not automatically generated by the test vectors are taken out from the fault list, under the condition that N first test cubes (namely, incompatible test cubes generated after combination) do not exist in the vector cache, an unconstrained single fault test generation mode is adopted to generate a second test cube for the target faults, under the condition that N first test cubes exist in the vector cache, the second test cubes which accord with the first constraint are generated for the target faults according to the single fault test generation mode, the first constraint is a common constraint which is generated according to the N first test cubes and is used for preventing the generated test cubes from entering conflict spaces of the N first test cubes, the generated second test cubes and the N first test cubes are combined and then written into the vector cache, so that the generation of invalid test vectors based on the common constraint is realized, the success rate of ATPG generation is reduced, the technical problem that the generation of test vectors is low in efficiency and the vector quality are solved, and the test vectors with higher quality are generated in a shorter time.

The application provides a method for generating the reduced test based on the common ATPG constraint, which reduces the invalid vector generated by the ATPG, improves the success rate of generating the test vector and the vector quality, reduces the total number of the generated test vectors and reduces the test cost of chips. As an alternative example, the following further details the technical solution of the present application in connection with the specific embodiments:

The overall structure of test vector generation and compaction of the ATPG system provided by the invention is shown in figure 2, and the ATPG system consists of a netlist parser, a fault list analyzer, single fault test generation, fault simulation and vector cache.

The ATPG system reads the netlist in verilog format from the outside, parses the netlist and stores the netlist in an internal structure, a fault list analyzer generates a simplified fault list for the read netlist analysis, the ATPG system randomly selects one fault from the fault list as a new fault f (namely a target fault), if N combined test cubes exist in the current vector cache, constraint single fault test generation is carried out, and otherwise unconstrained single fault test generation is carried out.

After the unconstrained test generation is completed, the vector cache is written, the writing process is the vector merging process, the ATPG system heuristically selects one vector cache to attempt merging, and if the merging fails, the ATPG system selects the other cache to attempt merging.

The test generation with the constraint generates a vector under the constraint of vector cache maintenance, and the generated vector performs the vector merging process which is the same as that of the vector generated by the unconstrained test; if the vector was not successfully generated due to a failure that proved to be redundant under the current constraint, the failure is re-added to the failure list. When there are already N incompatible merged test cubes in the vector cache, it will maintain the signals of a set of circuit input leads as constraints for ATPG generation vectors, which will be updated whenever a new test cube is merged; the conflict cache also maintains a termination limit AL for each cache that will not attempt to merge a new test cube if the test vector that failed to merge on that cache exceeds AL.

After a single test cube is generated, if X exists, the X bits are randomly filled to generate a complete test vector, the test vector is stored, after N test vectors are generated, a fault simulator simulates the test vectors, and if faults to be detected in a fault list can be detected by the test vectors, the states of the faults to be detected are set to be detected. When there are no faults in the fault list that can be tried, the system will report the number of all generated test vectors and the time of test generation.

The process of the reduced test generation method based on the common ATPG constraint of the present invention is described next with reference to examples.

The test merge scheme used by ATPG is shown in fig. 3, where each time a new test cube is generated, a vector cache is heuristically selected to attempt merging.

The current test cube tc= {10X1X0}, which fails to attempt merging with the first three caches, cannot merge correctly because they are at least one bit different from TC; the last buffer is compatible with the TC bits and can therefore be successfully merged. In the present invention, the definition operation intersection & has: 1&X =x, 0&X =x, 1&0 =x, 0&0 =0, 1& 1=1. It can be found that there are intersection constraints s= {1XXXXX } for four conflict caches, as shown in fig. 4. This constraint S will act as a constraint for the ATPG generation vector under which the decision tree of the ATPG is as shown in fig. 5. Constraint S can avoid ATPG making a decision of x1=0, thereby avoiding entering a solution space where collision must occur with all vector caches; thus, the effectiveness of ATPG test generation is greatly improved over previous methods.

In general, for a vector cache of maximum size N, we generate a constraint when its size reaches N for the first time, assuming values stored in the vector cache are T1, T2, &..tn, the constraint s=t1 & T2 &.& TN. And then each time the test cube successfully merges later, the new determination bit Sp filled in the test cube performs a & operation with the bits at the corresponding positions on the rest conflict caches to generate new constraint Sn, and finally the constraint S=S & Sn is updated.

In summary, the invention provides a reduced test generation method based on common ATPG constraint, which reduces invalid ATPG by maintaining intersection constraint of vector cache, improves success rate of test vector generation and vector quality, and reduces total number of generated test vectors. By using the invention, the test time and the generated test vector of the ATPG system are reduced, and the test cost is saved.

The invention optimizes the generating process of the test vector of the ATPG system, and the total number of the two index test vectors generated by the test vector and the test generating time are improved. Compared with the prior test merging method, the method for generating the reduced test based on the public ATPG constraint can generate the test vector with higher quality more quickly, and reduce the quantity of the generated test vectors.

It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

According to another aspect of the embodiment of the present application, there is also provided an ATPG test vector simplifying apparatus for implementing the above method for simplifying an ATPG test vector. Fig. 6 is a schematic diagram of an alternative ATPG test vector reduction apparatus according to an embodiment of the present application, and as shown in fig. 6, the apparatus may comprise:

the fault selection module 61 is configured to take out a target fault from a fault list, where the fault list stores a plurality of faults that need to be tested of a target chip, and the target fault is a fault that does not generate an automatic test vector;

the first generating module 63 is configured to generate, when N first test cubes do not exist in the vector cache, a second test cube for the target fault by adopting an unconstrained single fault test generating manner, where the N first test cubes are incompatible test cubes generated after merging, and N bits are preset integers greater than 2;

a second generating module 65, configured to generate, in the case that N first test cubes exist in the vector cache, a second test cube that conforms to a first constraint for the target fault according to a single fault test generating manner, where the first constraint is generated according to the N first test cubes and is used to avoid the generated test cubes from entering conflict spaces of the N first test cubes;

And the writing module 67 is configured to combine the generated second test cubes with the N first test cubes and write the combined second test cubes into the vector cache.

Through the module, the target fault which is not automatically generated by the test vector is taken out from the fault list, under the condition that N first test cubes (namely, the test cubes which are generated after combination and are incompatible) do not exist in the vector cache, a second test cube is generated for the target fault by adopting an unconstrained single fault test generation mode, under the condition that N first test cubes exist in the vector cache, a second test cube which accords with the first constraint is generated for the target fault according to the single fault test generation mode, the first constraint is a common constraint which is generated according to the N first test cubes and is used for preventing the generated test cubes from entering conflict spaces of the N first test cubes, the generated second test cubes and the N first test cubes are combined and then written into the vector cache, so that the generation of a simplified test vector based on the common constraint is realized, the invalid vector generated by ATPG is reduced, the success rate of the generation of the test vector and the vector quality are improved, the technical problem that the generation efficiency of the test vector is lower is solved, and the test vector with higher quality is generated in a shorter time is generally.

It should be noted that the above modules are the same as examples and application scenarios implemented by the corresponding steps, but are not limited to what is disclosed in the above embodiments. It should be noted that, the above modules may be implemented in a corresponding hardware environment as part of the apparatus, and may be implemented in software, or may be implemented in hardware, where the hardware environment includes a network environment.

According to another aspect of the embodiment of the present application, there is also provided a server or a terminal for implementing the above-mentioned method for simplifying ATPG test vectors.

Fig. 7 is a block diagram of a terminal according to an embodiment of the present application, and as shown in fig. 7, the terminal may include: one or more (only one is shown in fig. 7) processors 701, memory 703, and transmission means 705, as shown in fig. 7, the terminal may further comprise an input output device 707.

The memory 703 may be used for storing software programs and modules, such as program instructions/modules corresponding to the method and apparatus for simplifying ATPG test vectors in the embodiments of the present application, and the processor 701 executes the software programs and modules stored in the memory 703 to perform various functional applications and data processing, i.e., to implement the foregoing method for simplifying ATPG test vectors. The memory 703 may include high speed random access memory, but may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory. In some examples, the memory 703 may further include memory located remotely from the processor 701, which may be connected to the terminal through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 705 is used for receiving or transmitting data via a network, and may also be used for data transmission between a processor and a memory. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission device 705 includes a network adapter (Network Interface Controller, NIC) that may be connected to other network devices and routers via a network cable to communicate with the internet or a local area network. In one example, the transmission device 705 is a Radio Frequency (RF) module for communicating with the internet wirelessly.

Among them, the memory 703 is used to store, in particular, application programs.

The processor 701 may call an application program stored in the memory 703 through the transmission means 705 to perform the steps of:

Taking out a target fault from a fault list, wherein a plurality of faults of a target chip, which need to be tested, are stored in the fault list, and the target fault is a fault which does not generate an automatic test vector; generating a second test cube for the target fault by adopting an unconstrained single fault test generation mode under the condition that N first test cubes do not exist in the vector cache, wherein the N first test cubes are incompatible test cubes generated after combination, and N bits are preset integers larger than 2; generating a second test cube conforming to a first constraint for the target fault according to a single fault test generation mode under the condition that N first test cubes exist in the vector cache, wherein the first constraint is generated according to the N first test cubes and is used for avoiding the generated test cubes from entering conflict spaces of the N first test cubes; and merging the generated second test cubes with the N first test cubes, and writing the merged second test cubes into the vector cache.

Alternatively, specific examples in this embodiment may refer to examples described in the foregoing embodiments, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the structure shown in fig. 7 is only illustrative, and the terminal may be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a palm computer, a Mobile internet device (Mobile INTERNET DEVICES, MID), a PAD, etc. Fig. 7 is not limited to the structure of the electronic device. For example, the terminal may also include more or fewer components (e.g., network interfaces, display devices, etc.) than shown in fig. 7, or have a different configuration than shown in fig. 7.

Those of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be implemented by a program for instructing a terminal device to execute in association with hardware, the program may be stored in a computer readable storage medium, and the storage medium may include: flash disk, read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.

The embodiment of the application also provides a storage medium. Alternatively, in the present embodiment, the above-described storage medium may be used for program code for performing the compaction method of the ATPG test vector.

Alternatively, in this embodiment, the storage medium may be located on at least one network device of the plurality of network devices in the network shown in the above embodiment.

Alternatively, in the present embodiment, the storage medium is configured to store program code for performing the steps of:

Alternatively, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

The integrated units in the above embodiments may be stored in the above-described computer-readable storage medium if implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing one or more computer devices (which may be personal computers, servers or network devices, etc.) to perform all or part of the steps of the method described in the embodiments of the present application.

In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.

In several embodiments provided by the present application, it should be understood that the disclosed client may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units, such as the division of the units, is merely a logical function division, and may be implemented in another manner, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.

Claims

1. A method for simplifying ATPG test vectors, comprising:

Taking out a target fault from a fault list, wherein a plurality of faults of a target chip, which need to be tested, are stored in the fault list, and the target fault is a fault which does not generate an automatic test vector;

Generating a second test cube for the target fault by adopting an unconstrained single fault test generation mode under the condition that N first test cubes do not exist in the vector cache, wherein the N first test cubes are incompatible test cubes generated after combination, and N bits are preset integers larger than 2;

Generating a second test cube conforming to a first constraint for the target fault according to a single fault test generation mode under the condition that N first test cubes exist in the vector cache, wherein the first constraint is generated according to the N first test cubes and is used for avoiding the generated test cubes from entering conflict spaces of the N first test cubes;

And merging the generated second test cubes with the N first test cubes, and writing the merged second test cubes into the vector cache.

2. The method of claim 1, wherein prior to generating a second test cube conforming to the first constraint for the target fault in a single fault test generation manner, the method further comprises:

acquiring bit vectors at the same positions in the N first test cubes, wherein each test cube in the N first test cubes is a vector comprising M bit vectors, and M is a preset positive integer;

And generating the first constraint according to the relation between bit vectors at the same positions in the N first test cubes, wherein the bit number M of the first constraint.

3. The method of claim 2, wherein generating the first constraint from a relationship between bit vectors at the same location in the N first test cubes comprises:

crossing bit vectors at the same position in the N first test cubes according to a preset rule to obtain crossing results at the position;

and combining intersection results of all positions in the N first test cubes according to the sequence of the positions to obtain the first constraint.

4. The method of claim 3, wherein intersecting the bit vectors at the same location in the N first test cubes according to a preset rule to obtain an intersection result of the location, comprises:

And intersecting bit vectors at the same position in the N first test cubes according to the preset rule shown as follows to obtain intersecting results of the position: x & x=x, 1&X =x, 0&X =x, 1&0 =x, 0&0 =0, 1& 1=1, where X represents an uncertain bit and 1 and 0 represent a certain bit.

5. The method of claim 1, wherein merging the generated second test cube with the N first test cubes and writing the merged second test cubes into the vector cache comprises:

Detecting whether the second test cube conflicts with the N first test cubes;

And merging and writing the second test cube and the first test cubes which do not conflict into the vector cache under the condition that the first test cubes which do not conflict with the second test cube exist in the N first test cubes.

6. The method of claim 5, wherein after detecting whether the second test cube conflicts with the N first test cubes, the method further comprises:

under the condition that the N first test cubes collide with the second test cubes, writing the target faults back to the fault list, and updating the merging failure times of the vector cache;

and under the condition that the merging failure times reach the preset times, no new test cubes are written into the vector cache.

7. The method of any of claims 1 to 6, wherein after merging the generated second test cube with the N first test cubes and writing to the vector cache, the method further comprises:

and intersecting bit vectors at the same position in the second test cube and the first constraint according to a preset rule, and taking the obtained intersection result as a second constraint.

8. An ATPG test vector simplifying apparatus, comprising:

The fault selection module is used for taking out a target fault from a fault list, wherein a plurality of faults of a target chip, which need to be tested, are stored in the fault list, and the target fault is a fault which does not generate an automatic test vector;

The first generation module is used for generating a second test cube for the target fault by adopting an unconstrained single fault test generation mode under the condition that N first test cubes do not exist in the vector cache, wherein the N first test cubes are incompatible test cubes generated after combination, and N bits are preset integers which are larger than 2;

The second generation module is used for generating a second test cube conforming to a first constraint for the target fault according to a single fault test generation mode under the condition that N first test cubes exist in the vector cache, wherein the first constraint is generated according to the N first test cubes and is used for avoiding the generated test cubes from entering conflict spaces of the N first test cubes;

And the writing module is used for merging the generated second test cubes with the N first test cubes and writing the merged second test cubes into the vector cache.

9. A storage medium comprising a stored program, wherein the program when run performs the method of any one of the preceding claims 1 to 7.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor performs the method of any of the preceding claims 1 to 7 by means of the computer program.