CN118095180A - High-precision simulation system for standard unit of integrated circuit - Google Patents
High-precision simulation system for standard unit of integrated circuit Download PDFInfo
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- CN118095180A CN118095180A CN202410520378.8A CN202410520378A CN118095180A CN 118095180 A CN118095180 A CN 118095180A CN 202410520378 A CN202410520378 A CN 202410520378A CN 118095180 A CN118095180 A CN 118095180A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- G06F30/373—Design optimisation
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- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
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Abstract
The invention discloses a high-precision simulation system of an integrated circuit standard unit, which belongs to the field of simulation systems and comprises: the netlist analysis module is used for analyzing the file information of the simulated netlist, so that various information can be conveniently obtained; the standard unit time sequence arc calculation module calculates all time sequence arc information of the standard unit and calculates each time sequence arc; the standard unit simulation table definition module is used for customizing the format file, recording table information of each standard unit during simulation, and designating the setting of the external conditions of input conversion and output upper limit in various simulations; the standard unit input waveform generation module provides various input waveform generation algorithm selections; the standard unit simulation model library comprises setting information of each process simulation model; the standard unit simulation system main program comprises different simulation type generation functions, expands configuration and realizes optimization. According to the invention, the simulation work of the standard unit is completed in a short time, the simulation environment construction and simulation time is greatly shortened, and the simulation precision and simulation accuracy are ensured.
Description
Technical Field
The invention relates to the technical field of simulation systems, in particular to a high-precision simulation system for an integrated circuit standard unit.
Background
Std cell libraries are essentially built cells that are necessary for each process, including logic gates AND interconnections, such as AND gates, OR gates, flip-flops, etc., that are required to perform a particular function. The Std cell library design requirements for different processes are different, and in the early stage of process development, a wafer factory or IP manufacturing provider needs a design team to design the corresponding Std cell library for different processes. After advanced processes are entered, with the rise of collaborative optimization of process design, more chip designers are not limited to using general Std cell libraries, but instead study Std cell libraries designed to improve SOC performance. Including chip design companies, wafer factories, and IP manufacturing providers are researching how to develop more sophisticated and appropriate Std cell libraries under advanced process conditions in an effort to accelerate and effectively advance chip design flows.
The Std cell basic design flow is as follows: (1) Std cell schematic design: manually creating a standard design unit, and manually connecting lines to represent connection relations; (2) Std cell pre-simulation verification: manually setting up a simulation environment to carry out modeling simulation; (3) Std cell layout work: manually drawing a layout; (4) Std cell post-simulation verification: and manually setting up a simulation environment to extract parasitic resistance and capacitance and simulate the parasitic resistance and capacitance.
With the evolution of the process, the types and the number of Std cells which can be provided by the Std cell library are continuously increased, and a set of 22nm Std cell library provides more than 1000 different types of Std cells. During development of a process, it takes a developer to spend several months in Std cell design tasks to ensure delivery. In the process of collaborative optimization of process design, a lot of time is consumed for customizing and optimizing a part of Std cells in order to realize the optimization of high-level performance power consumption.
The pre-simulation and post-simulation verification of Std cells is typically performed using simulation tools such as Hspice, spectre. Because Std cells have different functions, a large amount of manual configuration is needed for simulating different Std cells, and various problems such as simulation precision, simulation setting correctness and the like also exist.
No commercial tools are currently available on the market for creating Std cell simulation environments during Foundation IP (integrated circuit standard cell) development. The corresponding work mostly needs to be carried out manually, and the workload is huge. The traditional manual setting mode also introduces uncertainty to cause inaccuracy of data, and increases the risk of streaming.
Disclosure of Invention
The invention aims to provide a high-precision simulation system for an integrated circuit standard unit, which aims to solve the problems in the background technology.
In order to solve the technical problems, the invention provides a high-precision simulation system of an integrated circuit standard unit, which comprises:
the netlist analysis module is used for analyzing netlist simulation file information and conveniently acquiring standard unit names, pin information, power supply information and mos tube information;
The standard unit time sequence arc calculation module calculates all time sequence arc information of the standard unit, calculates each time sequence arc, namely calculates all simulations to be completed, and sets the states of all pins of the standard unit in each time sequence arc simulation;
The standard unit simulation table definition module is used for customizing a format file, recording delay table, power table, setup time and holding time information when each standard unit is simulated, and setting the transition time of an input signal and the external conditions of the capacitance value of an output pin in various simulations;
The standard unit input waveform generation module provides various input waveform generation algorithm selections;
The standard unit simulation model library comprises setting information of each process simulation model;
the standard unit simulation system main program comprises different simulation type generation functions, expands configuration and realizes optimization.
In one embodiment, the netlist analyzing module analyzes the standard cell netlist file to obtain standard cell pin information, and classifies input, output, power supply pins and substrate pins; and determines whether the obtained standard cell is a register or a combinational logic.
In one embodiment, the standard unit time sequence arc calculation module performs time sequence arc calculation, if the standard unit is a combinational logic, the combinational logic spice simulation is performed by using different input 0/1 sequences to obtain a result of an output pin, and the result is combined by different inputs and outputs to form a plurality of time sequence arc simulation results of the standard unit simulation;
if the standard unit is of a sequential logic circuit type, a rising edge signal or a falling edge signal is poured into a clock trigger end of the standard unit, and before the rising edge signal, the input pins are poured into for excitation under the condition that the sufficient data pin establishment time is met, and different input pin state combinations are set; and finally, simulating the output result and summarizing.
In one embodiment, the standard cell input waveform generation module is configured to fit a more realistic signal waveform; wherein the signal waveform generation mode is realized through configuration.
In one embodiment, the generating mode includes piecewise linear function, linear and exponential function splicing, polynomial function fitting and custom generating function.
In one embodiment, the standard unit simulation table definition module is divided into manual definition and automatic definition, and a user self-defines the values of a specific input transit time upper limit and an output capacitance upper limit according to simulation setting; or only defining the maximum value and the minimum value in the table and the number of table splitting, and automatically generating setting information of the simulation delay condition setting table and the power consumption condition setting table.
In one embodiment, the main program of the standard cell simulation system selects a corresponding Spice model according to different simulation process angle settings; obtaining all simulation vector simulation results according to the time sequence arc calculation results; according to the definition in the standard unit simulation condition setting table, selecting a single value of input transition time as a simulation input value, and sending the single value to an input waveform generation module, wherein in the input waveform generation module, a determined piecewise linear waveform is obtained for simulation; and determining simulation measurement points through definition of simulation types, automatically generating an Hsps simulation file by a main program, carrying out Hsps simulation on batches by the main program to obtain standard unit simulation results, and finally summarizing the results.
In one embodiment, the netlist parsing module and the standard cell timing arc calculation module are both for python writing.
The integrated circuit standard unit high-precision simulation system provided by the invention automatically completes the configuration of Std Cell simulation environment, the generation of simulation files, the execution of simulation tasks and the summarization of simulation results, and has extremely short time consumption; and the simulation work of the std cell can be completed in a short time, the simulation environment construction and simulation time is greatly shortened, and the simulation precision and the simulation accuracy are ensured.
Drawings
FIG. 1 is a schematic diagram of the overall structure of a high-precision simulation system for standard cells of an integrated circuit according to the present invention.
Fig. 2 is a schematic diagram of a Std cell timing arc calculation flow provided by the present invention.
Detailed Description
The invention provides a high-precision simulation system for standard cells of an integrated circuit, which is further described in detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a high-precision simulation system of an integrated circuit standard unit, which structurally comprises the following parts as shown in figure 1:
1. the netlist analysis module is used for python writing, realizing analysis of simulated netlist file information, and conveniently obtaining information including std cell names, pin information, power supply information, mos tube information and the like;
2. STD CELL TIMING ARC (timing arc) calculating module, which is used for python writing, calculating all TIMING ARC information of std cell, calculating each TIMING ARC, namely calculating all simulations to be completed, and setting the states of pins of std cell in each TIMING ARC simulation;
3. the Std cell simulation table definition is used for customizing a format file, recording information such as delay tables, power tables, constraint tables or establishment maintaining time tables and the like when each Std cell is simulated, and designating settings of external conditions such as input transition time, output cap and the like in various simulations;
4. Std cell input Waveform (input Waveform) generation module for providing multiple input Waveform generation algorithm selections;
5. the Std cell simulation Model library is used for containing the setting information of each process simulation Model;
6. the Std cell simulation system main program is used for containing different simulation type generation functions, and can expand configuration and realize optimization.
The specific working flow of the integrated circuit standard unit high-precision simulation system is as follows:
The netlist analysis module analyzes Std Cell netlist files to obtain STD CELL PIN information, and classifies input, output, power supply pin, substrate pin and the like; and judges whether the obtained standard cell is a register, or a combinational logic, etc.
The Std cell timing arc calculation module performs timing arc calculation, and the flow of the Std cell timing arc calculation module is shown in FIG. 2; if Std Cell is the combinational logic, performing combinational logic spice simulation by using different input 0/1 sequences to obtain the result of output pin, and combining different input and output to form a plurality of sequential arcs of Std Cell simulation; if Std Cell is time sequence logic, then the rising edge or the falling edge is filled in the clock trigger end of Std Cell, and different input pin input state combinations are set before the filling time (under the condition that the sufficient data pins establish the holding time); and finally simulating the result of output, and summarizing. Different inputs and outputs are combined together to form a plurality of timing arcs simulated by the timing logic Std Cell.
The Std cell input waveform generation module is used for fitting a more real signal waveform. The generation mode can be configured, and the invention provides various generation mode selections, such as piecewise linear function, linear and exponential function splicing, polynomial function fitting, custom PWL (Piece-wise linear), and the like.
The Std cell simulation table definition is divided into manual definition and automatic definition, and a user can customize the values of a specific input transition time upper limit and an output capacitance upper limit according to simulation setting; or only defining the maximum value and the minimum value of the table, automatically completing the splitting of the input transition time table and the output capacitance table, and automatically generating the setting information of the tables such as simulation delay, power and the like.
And selecting a corresponding Spice Model according to the setting of a simulation process angle, such as information of a process, voltage, temperature and the like by the main program of the Std cell simulation system. And obtaining all simulation vectors (and value setting based on each input pin during simulation) according to the time sequence arc calculation result. And according to the definition in the Std cell simulation table, selecting a single input transition time value as a simulation input value, and transmitting the simulation input value to the waveform generation module for conversion. In the input waveform generation module, a determined input waveform is obtained for simulation. By definition of simulation types, simulation measurement points are determined, and an Hsepice simulation file is automatically generated by a main program. Then, the main program carries out Hspice simulation in batches to obtain Std Cell simulation results, and finally, results are summarized.
The invention realizes the complete set of work for automatically building stdcell simulation environment and verifying the correctness of data. In the process of collaborative optimization of process design and development of process procedures, different types of std cells are faced to a plurality of different processes, and simulation environments required for verifying the designs of the std cells with different functions, including pre-simulation and post-simulation, are automatically built at one time, and the simulation environments comprise perfect simulation inspection: delay time, transit time, capacitance value, setup time, hold time, etc. The simulation time is optimized for supporting multi-thread batch processing for a large amount of data. Compared with the traditional design method, the time for manually configuring the simulation environment is huge, and by adopting the simulation system, the simulation environment construction and simulation time is greatly shortened, and the simulation precision and simulation accuracy are ensured.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (8)
1. An integrated circuit standard cell high precision simulation system, comprising:
the netlist analysis module is used for analyzing netlist simulation file information and conveniently acquiring standard unit names, pin information, power supply information and mos tube information;
The standard unit time sequence arc calculation module calculates all time sequence arc information of the standard unit, calculates each time sequence arc, namely calculates all simulations to be completed, and sets the states of all pins of the standard unit in each time sequence arc simulation;
The standard unit simulation table definition module is used for customizing a format file, recording delay table, power table, setup time and holding time information when each standard unit is simulated, and setting the transition time of an input signal and the external conditions of the capacitance value of an output pin in various simulations;
The standard unit input waveform generation module provides various input waveform generation algorithm selections;
The standard unit simulation model library comprises setting information of each process simulation model;
the standard unit simulation system main program comprises different simulation type generation functions, expands configuration and realizes optimization.
2. The integrated circuit standard cell high-precision simulation system of claim 1, wherein the netlist parsing module parses a standard cell netlist file to obtain standard cell pin information, and classifies input, output, power supply pins, and substrate pins; and determines whether the obtained standard cell is a register or a combinational logic.
3. The integrated circuit standard cell high-precision simulation system according to claim 1, wherein the standard cell timing arc calculation module performs timing arc calculation, if the standard cell is a combinational logic, performs combinational logic spice simulation by using different input 0/1 sequences to obtain a result of an output pin, and combines different inputs and outputs together to form a plurality of timing arc simulation results of the standard cell simulation;
if the standard unit is of a sequential logic circuit type, a rising edge signal or a falling edge signal is poured into a clock trigger end of the standard unit, and before the rising edge signal, the input pins are poured into for excitation under the condition that the sufficient data pin establishment time is met, and different input pin state combinations are set; and finally, simulating the output result and summarizing.
4. The integrated circuit standard cell high precision simulation system of claim 1, wherein the standard cell input waveform generation module is configured to fit a more realistic signal waveform; wherein the signal waveform generation mode is realized through configuration.
5. The integrated circuit standard cell high precision simulation system of claim 4, wherein the generation mode comprises piecewise linear function, linear and exponential function concatenation, polynomial function fitting, custom generation function.
6. The integrated circuit standard cell high-precision simulation system of claim 1, wherein the standard cell simulation table definition module is divided into manual definition and automatic definition, and a user self-defines the values of a specific input transit time upper limit and an output capacitance upper limit according to simulation setting; or only defining the maximum value and the minimum value in the table and the number of table splitting, and automatically generating setting information of the simulation delay condition setting table and the power consumption condition setting table.
7. The integrated circuit standard cell high-precision simulation system of claim 1, wherein the standard cell simulation system main program selects a corresponding Spice model according to different simulation process angle settings; obtaining all simulation vector simulation results according to the time sequence arc calculation results; according to the definition in the standard unit simulation condition setting table, selecting a single value of input transition time as a simulation input value, and sending the single value to an input waveform generation module, wherein in the input waveform generation module, a determined piecewise linear waveform is obtained for simulation; and determining simulation measurement points through definition of simulation types, automatically generating an Hsps simulation file by a main program, carrying out Hsps simulation on batches by the main program to obtain standard unit simulation results, and finally summarizing the results.
8. The integrated circuit standard cell high precision simulation system of claim 1, wherein the netlist parsing module and the standard cell timing arc calculation module are both for python writing.
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