CN1180473C - high density integrated circuit package structure and method thereof - Google Patents

Abstract

The invention relates to a structure and a forming method of a packaged Integrated Circuit , in particular to a structure and a forming method of a high-density packaged Integrated Circuit.

Description

High-density integrated circuit packaging structure and method

technical field

The present invention relates to a structure and forming method of a packaged integrated circuit, in particular to a high-density integrated circuit package structure and its method, which can increase the integration degree of circuits in the packaged integrated circuit, simplify the manufacturing process, reduce manufacturing costs, and increase product quality. rate and improve the reliability of integrated circuit packaging.

Background technique

Integrated circuits generally need to be structured within packaging materials, such as traditional quad flat packages (Quad Flat Package, QFP). The flat package structure includes a lead frame on which there are many leads contacting an integrated circuit chip (Chip). The chip is packaged in a strong plastic that is mechanically supported and insulated from the circuit, while the leads are mainly soldered to the printed circuit board.

In the past, integrated circuit packaging technology developed by integrated circuit manufacturers has attempted to meet the miniaturization requirements. The improvement method for miniaturized integrated circuits is to enable it to combine millions of transistor circuit components including circuits, chips, etc. on a silicon substrate. These improved methods have led to a greater emphasis on methods of packaging circuit assemblies in limited space.

Integrated circuits are manufactured in integrated circuit equipment from a silicon wafer through complex etching, doping, deposition and cutting techniques. A silicon wafer contains at least one integrated circuit chip, each chip representing an individual integrated circuit. Finally, the chip can be packaged by a plastic molding compound (Molding Compound) surrounding the chip, and has a variety of pin exposure and interconnection designs. For example: provide a fairly flat package M-type dual-in-line-package (M Dual-In-Line-Package; M-Dip), which has two parallel rows of pins extending from the bottom through holes, contacting and Fixed on the integrated circuit board below. Printed circuit boards that allow higher-density integrated circuits are Single-In-Line-Package (SIP) and Small Outline J-leaded (SOJ), which are packages using models.

According to the number of integrated circuit chips combined in the package, the types of packaged integrated circuits can be roughly divided into two categories: single chip package (Single Chip Package; SCP) and multichip package (Multichip Package; MCP). Package (MultichipModule; MCM). According to the bonding method of components and circuit boards, packaged integrated circuits can be divided into two categories: Pin-Through-Hole (PTH) and Surface Mount Technology (SMT). The pins of the pin-inserted components are thin needle-shaped or thin-plate-shaped metals, which can be inserted into the socket (Socket) or the guide hole (Via) of the circuit board for soldering and fixing. The surface mount components are first pasted on the circuit board and then fixed by soldering. The more advanced packaging technology currently used is Direct Chip Attach (DCA) packaging to reduce the size of the packaged integrated circuit and increase the integration of circuits inside the packaged integrated circuit. The technology of direct chip bonding is to directly fix the integrated circuit chip (Integrated Circuit Chip) to the substrate (Substrate), and then connect the circuit.

Referring to FIG. 1 , this is a schematic diagram of traditionally using a photosensitive solder mask to fix a chip on a substrate. First, a substrate 10 and a chip 40 are provided, wherein the substrate 10 includes a plurality of circuit wires 25 laid out, a plurality of first welding pads (Solder Pad) 20, a solder mask 30, and a pre-welding platform 18 (can be omitted as necessary). The chip includes a plurality of second solder pads 45 and a plurality of solder bumps (Solder Bump) 15 . The solder bumps 15 are connected to the chip 40 via the second solder pads 45 . Next, the chip 40 can be connected to a plurality of first welding pads 20 or pre-soldering platforms 18 on the substrate 10 by means of a plurality of welding bumps 15, so as to fix the chip 40 on the substrate 10, wherein any welding bump 15 The positions of all correspond to any one of the first welding pads 20 .

In the traditional structure of packaged integrated circuits, the purpose of using the solder resist film 30 is to prevent the on-line circuit wires 25 on the substrate 10 from being infringed by the external environment, and to prevent the circuit gap caused by the overflow of the solder bumps 15 in the subsequent process. between defects. Therefore, in the conventional packaged integrated circuit structure including a solder resist film, the solder resist film 30 must cover the circuit 25 distributed on the substrate to protect the circuit 25 distributed on the substrate 10 . In order to provide a better protection function, the solder mask 30 must cover part of any first soldering pad 20 distributed on the substrate 10, so as to avoid defects caused by soldering bumps 15 due to overflow in subsequent manufacturing processes. . Since the solder resist film must cover any of the first solder pads 20 that are partially distributed on the substrate 10, in the traditional packaging integrated circuit structure that uses a solder mask film, an additional boundary needs to be reserved around the first solder pad 20 In order to have sufficient error tolerance width to carry the soldering bumps, the number of wires that can be tolerated between the first soldering pads 20 on the substrate and the first soldering pads 20 will be reduced. This phenomenon will result in the inability to reduce the volume of the packaged integrated circuit structure using the solder mask, so that this technology cannot be applied to the increasingly smaller demands of the integrated circuit.

For packaged integrated circuits using a solder mask, since the solder mask must cover any part of the first solder pads, when the solder bumps are connected to the first solder pads, the problem of inaccurate positioning of the solder bumps will occur. Affect the quality of packaged integrated circuits. Also, the solder mask will cause defects to easily occur. When the package used is Flip Chip (FC) that does not fully cover the Molding Compound or the replaced Underfill (Flip Chip; FC), the solder mask covering the circuit The circuit on the substrate is prone to poor packaging reliability and defects due to weak bonding and easy peeling.

Contents of the invention

The main purpose of the present invention is to overcome the deficiencies and defects of the prior art, to provide a high-density integrated circuit packaging structure and its method, using a metal with solder adhesion (Solder Wettability) as the material of the first solder pad, and A high-reliability shielding layer is formed on the metal layer of the circuit to avoid defects in the packaged integrated circuit.

The second object of the present invention is to use metal with soldering adhesion as the material of the first soldering pad, and form a high-reliability shielding layer on the metal layer as the circuit, so as to improve the reliability of the packaged integrated circuit on the substrate. Circuit integration.

The third object of the present invention is to use a metal with soldering adhesion as the material of the first pad, and form a high reliability shielding layer on the metal layer as the circuit, so as to increase the reliability of the packaged integrated circuit.

The fourth object of the present invention is to use a metal with soldering adhesion as the material of the first pad, and form a high-reliability shielding layer on the metal layer as the circuit, so as to improve the yield rate of the packaged integrated circuit ( yield).

The fifth object of the present invention is to use a metal with soldering adhesion as the material of the first pad, and to form a high-reliability shielding layer on the metal layer as the circuit, so as to improve the production efficiency of packaged integrated circuits.

Another object of the present invention is to use metal with soldering adhesion as the material of the first pad, and form a high-reliability shielding layer on the metal layer as the circuit, so as to reduce the production cost of the integrated circuit package.

According to the above-mentioned purpose, the present invention provides a high-density integrated circuit packaging structure and method thereof, using metal with soldering adhesion as the material of the first soldering pad, and forming a high-density circuit board on the metal layer as the circuit. Reliability shield to avoid defects in packaged integrated circuits that do not include a solder mask. The structure includes: a substrate; a plurality of metal layers located on a portion of the substrate to serve as a circuit on the substrate; a plurality of solder pads located on a portion of the metal layer to form a plurality of soldering interfaces; a shielding layer, Covering the plurality of metal layers and exposing the welding pad on the surface of the shielding layer; wherein, there is no solder mask between the metal layer and the welding interface. The method includes: first providing a substrate and forming a whole surface metal layer on the substrate, wherein most of the metal layer is made of copper (Copper). Next, the position of the first welding pad is defined on the metal layer and a first photoresist layer is formed on part of the metal layer, wherein the first photoresist layer contains a plurality of first openings. Next, form a first soldering pad on the metal layer at the bottom of any opening and remove the first photoresist layer, wherein the first soldering pad is a metal with soldering adhesion, by means of electrical/chemical plating or Formed by physical/chemical deposition. Next, a second photoresist layer is formed on part of the metal layer to remove part of the metal layer, and the second photoresist layer is removed to form a plurality of welding interfaces and a plurality of metal layers on the substrate, wherein any welding interface The first welding pad and the metal layer are included, and the plurality of metal layers are used as a circuit on the surface of the substrate. Next, a shielding layer is formed on the substrate, the metal layer and the first welding pad, and part of the shielding layer is removed to expose the first welding pad. Finally, according to the requirements of the process and products, it is possible to choose whether to form a small bump on the first soldering pad or a pre-soldering platform as the interface between the first soldering bump and the first soldering pad in the subsequent process, and the high-end The fabrication process of substrates in density-packed integrated circuits. A chip connected to a plurality of first soldering bumps by means of a plurality of second soldering pads can be directly connected to a plurality of first soldering pads by means of reflow heating of a plurality of first soldering bumps, so that the chip is directly fixed on the substrate. Finally, a layer of molding compound or underfill is covered on the substrate to protect the circuits and chips formed on the substrate, and the process of high-density packaging integrated circuits can be completed.

Utilizing the manufacturing process and structure of the present invention can increase the circuit integration degree of the packaged integrated circuit on the substrate, and increase the reliability of the packaged integrated circuit. Utilizing the manufacturing process and structure of the present invention can also improve the packaging yield of integrated circuits and the efficiency of producing packaged integrated circuits. The manufacturing process and structure of the present invention can further reduce the production cost of packaged integrated circuits.

Description of drawings

Figure 1 is a schematic diagram of traditionally using a solder mask to fix a chip on a substrate;

2 is a schematic diagram of forming a metal layer on a substrate;

3 is a schematic diagram of forming a first photoresist layer on part of the metal layer;

4 is a schematic diagram of forming a first welding pad on the metal layer at the bottom of any opening;

5 is a schematic diagram of removing the first photoresist layer and forming a first welding pad on a part of the metal layer;

6 is a schematic diagram of forming a second photoresist layer on a part of the metal layer;

7 is a schematic diagram of removing part of the metal layer;

8 is a schematic diagram of removing the second photoresist layer to form a plurality of metal layers and a plurality of soldering interfaces on the substrate;

9 is a schematic diagram of forming a high-reliability shielding layer on the substrate, the metal layer and the first welding pad;

10 is a schematic diagram of removing part of the high-reliability shielding layer to form a plurality of second openings inside the high-reliability shielding layer;

11 is another schematic diagram of removing part of the high-reliability shielding layer to expose the first soldering pad;

FIG. 12 is a schematic diagram of forming small bumps on the first welding pad;

13 is a schematic diagram of forming a pre-soldering platform on the first welding pad;

FIG. 14 is a schematic diagram of a chip connected to a substrate; and

FIG. 15 is a schematic diagram of forming encapsulation compound on the chip and the substrate and connecting a plurality of second soldering bumps on the bottom of the substrate.

Explanation of symbols in the figure

10 substrates

15 solder bumps

18 pre-soldered platforms

20 first solder pads

25 circuit wire

30 solder mask

40 chips

45 second solder pad

100 substrates

110 metal layers

120 first photoresist layer

122 first opening

130 first solder pad

140 second photoresist layer

160 welding interface

170 high reliability shielding layer

200 second opening

210 first axis

220 second axis

230 angle

240 small bumps

250 pre-soldered platform

300 chips

310 second solder pad

320 first solder bump

400-pack potting mix

500 third solder pad

510 second solder bump

Detailed ways

The specific implementation manner of the present invention will be described in detail below in conjunction with the accompanying drawings and examples.

The present invention provides an integrated circuit packaging structure and forming method that does not require the use of traditional photosensitive solder mask, using metal with soldering adhesion as the material of the first soldering pad, and forming a high-altitude soldering pad on the metal layer as the circuit Reliability shielding layer to avoid defects in traditional photosensitive solder mask packaged integrated circuits that cannot completely cover the metal layer of the circuit due to inaccurate alignment. Referring to FIG. 2 , it is a schematic diagram of forming a metal layer on a substrate. The present invention must firstly provide a substrate 100 and form a metal layer 110 on the substrate. The metal layer 110 can be made of different materials according to product requirements. Usually, the metal layer 110 is made of copper. Referring to FIG. 3 , it is a schematic diagram of forming a first photoresist layer on a part of the metal layer. After defining the position of the first welding pad to be formed on the substrate 100 on the metal layer 110, a first photoresist layer 120 can be formed on the metal layer 110, and a plurality of solder pads can be formed in the first photoresist layer 120. The first pad opening 122 .

Referring to FIG. 4 , which is a schematic diagram of forming a first solder pad on the metal layer at the bottom of any first solder pad opening. Referring to FIG. 5 , it is a schematic diagram of removing the first photoresist layer and forming the first welding pad on part of the metal layer. After forming a plurality of first openings 122 on the metal layer 110 by means of the first photoresist layer 120, a first soldering pad 130 is formed on the metal layer 110 at the bottom of any first opening 122 and the first photoresist is removed. Layer 120. The first welding pad 130 is used to connect the first welding bump in the subsequent process, so that the chip can be fixed on the substrate. The first solder pad 130 is a metal material with solder wettability. The thickness of the first soldering pad 130 can vary with different products and process requirements. Generally, if the first welding pad 130 is used to connect the first welding bump in the subsequent process so that the chip can be fixed on the substrate 100 , the first welding pad 130 is usually formed by electrical/electroless plating. If the first welding pad 130 is used to connect other wires to connect other circuit components, the first welding pad 130 is usually formed by physical/chemical deposition.

Referring to FIG. 6 , this is a schematic diagram of forming a second photoresist layer on a part of the substrate. After the first photoresist layer 120 is removed, a second photoresist layer 140 is formed on a portion of the metal layer 110 . The purpose of the second photoresist layer 140 is to layout the circuits on the substrate 100 .

Referring to FIG. 7 , it is a schematic diagram of removing part of the metal layer. After the second photoresist layer 140 is formed on part of the metal layer, the second photoresist layer 140 and the first welding pad 130 are used as a shield to remove part of the metal layer 110 and remove the second photoresist layer 140 (refer to 8 ), to form a plurality of metal layers 110 and a plurality of soldering interfaces 160 on the substrate 100 , wherein any soldering interface 160 includes the metal layer 110 and the first soldering pad 130 . After the second photoresist layer 140 is removed, the metal layers 110 remaining on the substrate 100 are circuits to be formed on the substrate 100 . In the process of removing part of the metal layer 110, the metal layer 110 in the soldering interface 160 and below the first soldering pad 130 is protected by the first soldering pad 130, so even if the first soldering pad 130 is not formed above the first soldering pad 130 The second photoresist layer 140 and the metal layer 110 in the soldering interface will not be removed either.

Referring to FIG. 9, this is a schematic diagram of forming a high reliability mask layer (High Reliability Mask Layer) on the substrate, the metal layer and the first welding pad. After forming a plurality of metal layers 110 and a plurality of soldering interfaces 160 on the substrate 100, a high-reliability shielding layer 170 is formed on the substrate 100, the metal layer 110 and the first soldering pad 130, wherein the high-reliability shielding layer 170 is usually a non-photosensitive dielectric material. The thickness of the high-reliability shielding layer 170 can vary according to different products and process requirements. Therefore, the high-reliability shielding layer 170 is usually a non-photosensitive material, so when removing part of the high-reliability shielding layer 170, it can be removed directly by laser or plasma etching without using a photoresist layer. .

After forming a high-reliability shielding layer 170 on the substrate 100 , the metal layer 110 and the first soldering pad 130 , a part of the high-reliability shielding layer can be removed to expose the first soldering pad 130 . The following description is only an example of the present invention, but does not limit the scope of the present invention. Referring to FIG. 10 , it is a schematic diagram of removing part of the high-reliability shielding layer to form a plurality of second openings inside the high-reliability shielding layer. After forming a high-reliability shielding layer 170 on the substrate 100, the metal layer 110 and the first welding pad 130, a part of the high-reliability shielding layer 170 is removed to form a plurality of second Openings 200 , wherein the bottom of any second opening 200 exposes the first welding pad 130 . The sidewall of any second opening 200 forms an angle 230 with a first axis 210 to improve the stability of the connection between the first soldering bump and the first soldering pad 130 in the subsequent process, wherein the first The axial direction 210 is a direction parallel to the surface of the substrate 100 . The height of the plane of any first soldering pad on the second axis 220 is lower than the height of the plane of the high-reliability shielding layer 170 on the second axis 220, wherein the second axis 220 is perpendicular to the substrate 100 surface orientation.

In the process of removing part of the high-reliability shielding layer 170 in the present invention, laser (Laser) or plasma etching (Plasma Etching) is used to remove part of the high-reliability shielding layer 170 . Therefore, in the process of removing part of the high-reliability shielding layer 170 , there is no need to use a photoresist layer to protect components on the surface of the substrate.

The following description is another embodiment of the present invention, but does not limit the scope of the present invention. Referring to FIG. 11 , this is another schematic diagram of removing part of the high-reliability shielding layer to expose the first soldering pad. After forming a high-reliability shielding layer 170 on the substrate 100 , the metal layer 110 and the first welding pad 130 , a part of the high-reliability shielding layer 170 is removed to expose the first welding pad 130 . In the process of removing part of the high-reliability shielding layer 170, the method adopted is non-directional etching to reduce the height of the plane of the high-reliability shielding layer 170 on the second axis 220 until the first soldering pad is exposed. 130 , wherein the second axis 220 is a direction perpendicular to the surface of the substrate 100 and the metal layer 110 will not be exposed during the process of removing part of the high-reliability shielding layer 170 . In order to expose the first soldering pad 130 , the height of the plane of the first soldering pad 130 on the second axis 220 is higher than the height of the plane of the high-reliability shielding layer 170 on the second axis 220 .

Referring to FIG. 12 , this is a schematic diagram of forming a small bump (MiniBump) 240 on the first pad. Referring to FIG. 13 , it is a schematic diagram of forming a pre-soldering platform 250 on the first soldering pad. In order to increase the bonding, stability and coplanarity between the first soldering bump and the first soldering pad 130 in the subsequent process, a small bump 240 or a pre-soldering platform 250 can usually be formed on the first soldering pad 130 as a The interface between the first welding bump and the first welding pad 130 enables the chip to be carried on the substrate more stably. In the process of making the small bumps 240 , the substrate can be soaked in a tin-lead solution or electroless plated to form a tin layer on the first pad layer 130 as the small bumps 240 . In the process of making the pre-soldering platform 250, usually a solder ball/solder paste is reflowed and bonded to the first solder pad 130 and the solder ball is flattened as the pre-soldering platform 250 to increase the subsequent process. The contact area of the first bump connected to the soldering interface provides good coplanarity and soldering reliability. In the present invention, the small bumps and the pre-soldering platform can be applied to another substrate in which the first soldering pad is exposed, and the scope of use thereof is not limited. In the present invention, the first soldering pad can be directly connected with the first soldering bump in the subsequent process, so as to be fixed on the substrate via the chip.

Referring to FIG. 14 , it is a schematic diagram of connecting the chip to the substrate. After the first bonding pad is exposed, the chip 300 and the substrate 100 can be connected to each other. The chip 300 is connected to the plurality of first soldering bumps 320 via a plurality of second soldering pads 310 , and any second soldering pad 310 corresponds to any one of the first soldering bumps 320 . A protective layer is further included on the chip to prevent the chip from being damaged during reflow heating and bonding. The plurality of first solder bumps 320 can be connected to the plurality of first solder pads 130 on the substrate 100 by means of reflow heating to fix the chip 300 on the substrate 100 . Any first solder bump 320 can easily correspond to any first solder pad 130 . Since the solder mask is not used in the present invention and there is no positioning problem in the process of connecting the first soldering bump 320 to the first soldering pad 130, the present invention can increase the process operation efficiency of the integrated circuit and reduce the production cost. The cost required to package an integrated circuit. Fixing the chip on the substrate is only one embodiment of the present invention, but does not limit the protection scope of the present invention. The present invention can also utilize the first soldering pad on the soldering interface to be connected to other circuit components via a wire. After the chip 300 is fixed on the substrate 100, the joint between the chip 300 and the substrate and the chip can be fixed by using Package Molding Compound 400 packaging method or flip-chip filler (Underfill) packaging method, and A plurality of second soldering bumps 510 (shown in FIG. 15 ) are connected to the bottom of the substrate to protect the circuit on the chip 300 and the substrate 100 from being affected by the external environment during operation and reduce its operation performance, and complete the process. Process for packaging integrated circuits that do not include a solder mask. The bottom of the substrate can be connected to a plurality of second solder bumps 510 by means of a plurality of third solder pads 500 , so that the packaged integrated circuit that does not include a solder mask can be connected to other components. Referring to FIG. 11 , the plurality of second solder bumps 510 connected to the bottom of the substrate 100 is only an embodiment of the present invention and does not limit the scope of the present invention. The packaged integrated circuit designed with the non-photosensitive dielectric pad opening designed by the present invention can still be connected to other components in other package forms.

In the present invention, since no solder mask is used, no additional borders need to be reserved around the first soldering pads, and more circuits can be laid out between any two first soldering pads. This phenomenon can smoothly reduce the volume of packaged integrated circuits that do not contain solder mask and can contain more circuits, so as to improve the performance of packaged integrated circuits after reducing the size, and can improve the stability of packaged integrated circuits

In summary, the present invention provides an integrated circuit packaging structure and method thereof without using a solder mask, using a metal with soldering adhesion as the material of the first soldering pad, and as A high-reliability shielding layer is formed on the metal layer of the circuit to avoid defects in packaged integrated circuits that do not include solder mask. Firstly, a substrate is provided and a metal layer is formed on the substrate, wherein the metal layer is mostly made of copper. Next, the position of the first welding pad is defined on the metal layer and a first photoresist layer is formed on part of the metal layer, wherein the first photoresist layer contains a plurality of first openings. Next, form a first soldering pad on the metal layer at the bottom of any opening and remove the first photoresist layer, wherein the first soldering pad is a metal with soldering adhesion, by means of electrical/chemical plating or Formed by physical/chemical deposition. Next, a second photoresist layer is formed on part of the metal layer to remove part of the metal layer, and the second photoresist layer is removed to form a plurality of welding interfaces and a plurality of metal layers on the substrate, wherein any welding interface The first welding pad and the metal layer are included, and the plurality of metal layers are used as a circuit on the surface of the substrate. Next, a high-reliability shielding layer is formed on the substrate, the metal layer and the first welding pad, and part of the high-reliability shielding layer is removed to expose the first welding pad. Finally, according to the requirements of the process and products, it is possible to choose whether to form a small bump on the first soldering pad or a pre-soldering platform as the interface between the first soldering bump and the first soldering pad in the subsequent process, and the high-end The fabrication process of substrates in density-packed integrated circuits. A chip connected to a plurality of first soldering bumps by means of a plurality of second soldering pads can be directly connected to a plurality of first soldering pads by means of reflow heating of a plurality of first soldering bumps, so that the chip is directly fixed on the substrate. Finally, cover the substrate with a layer of encapsulation potting compound or fill it with underfill to protect the circuits and chips formed on the substrate, and the process of high-density packaging integrated circuits can be completed.

Utilizing the manufacturing process and structure of the present invention can increase the circuit integration degree of the packaged integrated circuit on the substrate, and increase the reliability of the packaged integrated circuit. Utilizing the manufacturing process and structure of the present invention can also improve the yield rate of packaged integrated circuits and the efficiency of producing packaged integrated circuits. Utilizing the process and structure of the present invention can reduce the production cost of packaged integrated circuits, not only has practical effects, but also has an unprecedented design, and has improved effects and progress.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention; all other equivalent changes or modifications that do not deviate from the spirit disclosed in the present invention should be included in the claims within the scope of the book.

Claims (16)

1. a high density integrated circuit encapsulating structure is characterized in that, this structure comprises:

One substrate;

A plurality of metal levels are positioned on this substrate of part in order to as the circuit on this substrate;

A plurality of welded gaskets are positioned on this metal level of part to form a plurality of weld interfaces;

One screen covers these a plurality of metal levels and exposes this welded gasket on the surface of this screen; And

Wherein, do not have weld-proof membrane between above-mentioned metal level and the weld interface.

2. high density integrated circuit encapsulating structure as claimed in claim 1 is characterized in that, comprises a plurality of openings in the above-mentioned screen.

3. high density integrated circuit encapsulating structure as claimed in claim 2 is characterized in that, above-mentioned welded gasket is positioned at a bottom of this opening.

4. high density integrated circuit encapsulating structure as claimed in claim 1 is characterized in that, the height of above-mentioned welded gasket is lower than the height of this screen.

5. high density integrated circuit encapsulating structure as claimed in claim 2 is characterized in that, the sidewall of above-mentioned opening and this substrate surface present an angle.

6. high density integrated circuit encapsulating structure as claimed in claim 1 is characterized in that, the height of above-mentioned welded gasket is higher than the height of this screen.

7. high density integrated circuit encapsulating structure as claimed in claim 1 is characterized in that, more comprises a small lugs on the above-mentioned welded gasket.

8. high density integrated circuit encapsulating structure as claimed in claim 1 is characterized in that, more comprises a prewelding platform on the above-mentioned welded gasket.

9. high density integrated circuit encapsulating structure as claimed in claim 1 is characterized in that, above-mentioned screen is a non-photosensitive type dielectric material layer.

10. a method that forms the high-density packages integrated circuit is characterized in that, this method comprises:

One substrate is provided;

Form a metal level on this substrate;

Form one first photoresist layer on this metal level of part, and in this first photoresist layer, form a plurality of openings;

Form a plurality of welded gaskets, wherein arbitrary this welded gasket is positioned at the bottom of arbitrary this opening and on this metal level;

Remove this first photoresist layer;

Form one second photoresist layer on this metal level of part;

With this second photoresist layer and this first welded gasket serves as that shielding removes this metal level of part and removes this second photoresist layer to form a plurality of circuit and a plurality of weld interface on this substrate, and wherein arbitrary circuit is this metal level and arbitrary weld interface is formed by this metal level and this welded gasket on it;

Form a screen on this substrate, this welded gasket and this metal level; And

The screen that removes part is to expose this welded gasket on the surface of this screen.

11. the method for formation high-density packages integrated circuit as claimed in claim 10 is characterized in that, comprises a plurality of openings in the above-mentioned screen.

12. the method for formation high-density packages integrated circuit as claimed in claim 11 is characterized in that, above-mentioned welded gasket is positioned at a bottom of this opening.

13. the method for formation high-density packages integrated circuit as claimed in claim 11 is characterized in that, the height of above-mentioned welded gasket is lower than the height of this screen.

14. the method for formation high-density packages integrated circuit as claimed in claim 11 is characterized in that, the sidewall of above-mentioned opening and this substrate surface present an angle.

15. the method for formation high-density packages integrated circuit as claimed in claim 10 is characterized in that, the height of above-mentioned welded gasket is higher than the height of this screen.

16. the method for formation high-density packages integrated circuit as claimed in claim 10 is characterized in that, above-mentioned screen is a non-photosensitive type dielectric material.

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