CN117971349A - Computing device, method of configuring virtual registers for a computing device, control device, computer-readable storage medium, and computer program product - Google Patents

Abstract

The present disclosure provides a computing device, a method of configuring virtual registers for a computing device, a control device, a computer-readable storage medium, and a computer program product. The computing device includes: a plurality of computing units, each configured to run one thread of a thread bundle; a plurality of thread local registers dedicated to each compute unit for registering data associated with threads operated by the compute unit; and a shared buffer for the plurality of computing units, wherein a portion of the shared buffer is configured as a virtual register for the plurality of computing units, and at least one of the plurality of thread local registers of each computing unit is configured as a staging register for threads operated by the computing unit to access the virtual register.

Description

Computing device, method for configuring virtual registers for computing device, control device, computer readable storage medium and computer program product

Technical Field

The present disclosure generally relates to the field of processors, and more particularly, to a computing device, a method for configuring a virtual register for a computing device, a control device, a computer-readable storage medium, and a computer program product.

Background technique

Currently, with the development of artificial intelligence (AI) technology, AI chips often need to process large amounts of data quickly, so it is hoped that the data can be as close as possible to the computing unit that accesses the data. In addition, compared with cache and memory, the overhead of accessing data in registers is lower, which can improve the performance of operators, so operator development usually gives priority to using registers to store data. However, the number of local registers fixedly configured for a computing unit is often limited. When the number of registers required by an operator exceeds the number of configured hardware registers, the compiler will save part of the data in memory or cache to ensure that the operator can execute normally. The access overhead to memory or cache is very high, which will cause a huge loss in operator performance.

Summary of the invention

In view of the above problems, the present disclosure provides a solution for configuring virtual registers for multiple computing units or each computing unit in a shared cache for data sharing between multiple computing units to speed up data access of the computing units.

According to one aspect of the present disclosure, a computing device is provided, which includes: a plurality of computing units, each of which is configured to run a thread of a thread warp; a plurality of thread-local registers dedicated to each computing unit, for storing data associated with the thread run by the computing unit; and a shared buffer for the plurality of computing units, wherein a portion of the shared buffer is configured as a virtual register for the plurality of computing units, and at least one thread-local register of the plurality of thread-local registers of each computing unit is configured as a transit register for the thread run by the computing unit to access the virtual register.

In some implementations, the virtual registers include one or more thread virtual registers dedicated to the threads of each computing unit, respectively, and each computing unit is configured to access the one or more thread virtual registers through the transfer register of the computing unit when running the thread.

In some implementations, the computing unit is configured to write the data to the transfer register upon determining that the thread is to write the data to the one or more thread virtual registers, and the transfer register is configured to write the data to the one or more thread virtual registers of the computing unit.

In some implementations, the computing unit is configured to send a read request to the transfer register when determining that the thread wants to read data from the one or more thread virtual registers, and the transfer register is configured to read the data from the one or more thread virtual registers of the computing unit in response to the read request for reading by the thread running the computing unit.

In some implementations, the virtual registers include one or more warp virtual registers shared by warps of the plurality of compute units, and each compute unit is configured to access the one or more warp virtual registers through a transit register of the compute unit when executing the warp.

In some implementations, upon determining that the thread warp is to write data to the one or more thread warp virtual registers, one of the plurality of computing units is configured to write the data to a transfer register of the computing unit, and the transfer register is configured to write the data to the one or more thread warp virtual registers.

In some implementations, when it is determined that the thread warp is to read data from the thread warp virtual register, each of the plurality of computing units sends a read request to a respective transfer register, and each transfer register is configured to read the data from the thread warp virtual register in response to the read request for reading by a thread executed by the corresponding computing unit.

In some implementations, when it is determined that the thread warp is to read data from the thread warp virtual register, each of the multiple computing units sends a read request to a transfer register of the computing unit, and the transfer register of one of the multiple computing units is configured to read the data from the thread warp virtual register in response to the read request and broadcast it to the multiple computing units.

According to another aspect of the present disclosure, a method for configuring virtual registers for a computing device is provided, wherein the computing device comprises: a plurality of computing units, each computing unit being configured to run a thread of a thread warp; a plurality of thread local registers dedicated to each computing unit, for registering data associated with the threads run by the computing unit; and a shared buffer for the plurality of computing units. The method comprises: configuring a portion of the shared buffer as a virtual register for the plurality of computing units; and configuring at least one thread local register of the plurality of thread local registers of each computing unit as a transit register for the thread run by the computing unit to access the virtual register.

In some implementations, configuring a portion of the shared cache as a virtual register for the multiple computing units includes: configuring one or more thread virtual registers dedicated to the threads of each computing unit, and the method also includes: configuring each computing unit to access the one or more thread virtual registers through a transfer register of the computing unit when running the thread.

In some implementations, configuring each computing unit to access the one or more thread virtual registers through a transfer register of the computing unit when running the thread includes: configuring the computing unit to write the data to the transfer register when determining that the thread is to write data to the one or more thread virtual registers, and configuring the transfer register to write the data to the one or more thread virtual registers of the computing unit.

In some implementations, configuring each computing unit to access the one or more thread virtual registers through a transfer register of the computing unit when running the thread includes: configuring the computing unit to send a read request to the transfer register when determining that the thread wants to read data from the one or more thread virtual registers, and configuring the transfer register to read the data from the one or more thread virtual registers of the computing unit in response to the read request for reading by the thread running the computing unit.

In some implementations, configuring a portion of the shared buffer as a virtual register for the plurality of computing units includes: configuring one or more warp virtual registers shared by warps of the plurality of computing units, and the method further includes: configuring each computing unit to access the one or more warp virtual registers through a transit register of the computing unit when executing the warp.

In some implementations, configuring each computing unit to access the one or more warp virtual registers through a transfer register of the computing unit when running the warp includes: configuring one computing unit among the plurality of computing units to write the data to the transfer register of the computing unit when determining that the warp is to write data to the one or more warp virtual registers, and configuring the transfer register to write the data to the one or more warp virtual registers.

In some implementations, configuring each computing unit to access the one or more warp virtual registers through a transfer register of the computing unit when running the warp includes: configuring each computing unit of the plurality of computing units to send a read request to a respective transfer register when determining that the warp is to read data from the warp virtual register, and configuring each transfer register to read the data from the warp virtual register in response to the read request for reading by a thread run by the corresponding computing unit.

In some implementations, configuring each computing unit to access the one or more warp virtual registers through the transfer register of the computing unit when running the warp includes: configuring each computing unit of the multiple computing units to send a read request to the transfer register of the computing unit when determining that the warp wants to read data from the warp virtual register, and configuring the transfer register of one computing unit of the multiple computing units to read the data from the warp virtual register in response to the read request and broadcast it to the multiple computing units.

According to another aspect of the present disclosure, a control device is provided, comprising: at least one processor; and at least one memory, wherein the at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor, wherein the instructions, when executed by the at least one processor, cause the control device to perform the steps of the method as described above.

According to yet another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program code is stored. When the computer program code is executed, the method described above is executed.

According to yet another aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein the computer program performs the method described above when executed by a machine.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be better understood and other objects, details, features and advantages of the present disclosure will become more apparent through the description of specific embodiments of the present disclosure given with reference to the following drawings.

FIG1 shows a schematic diagram of the structure of a computing device.

FIG. 2 shows a schematic diagram of the structure of a computing device according to an embodiment of the present invention.

FIG. 3A is a schematic diagram showing a computing device for a thread operation according to an embodiment of the present invention.

FIG. 3B is a schematic diagram showing a computing device for another thread operation according to an embodiment of the present invention.

FIG. 4 shows an exemplary flow chart of a method for configuring virtual registers for a computing device according to an embodiment of the present invention.

Detailed ways

The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one embodiment" and "some embodiments" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

FIG. 1 shows a schematic diagram of the structure of a computing device 100. As shown in FIG. 1 , the computing device 100 may include multiple computing units 110 and multiple thread local registers 120 dedicated to each computing unit 110. FIG. 1 exemplarily shows eight computing units 110-1, 110-2 ... 110-8, and exemplarily shows four thread local registers 120-1, 120-2 ... 120-4 for each computing unit 110. Note that the number of computing units 110 and thread local registers 120 shown in FIG. 1 is merely exemplary and is not intended to limit the scope of the present invention. In addition, for ease of description, the thread local registers 120 of different computing units 110 are labeled with the same reference numerals, but those skilled in the art will understand that they are actually different physical registers. For example, the thread local register 120-1 of the computing unit 110-1 and the thread local register 120-1 of the computing unit 110-2 are different physical registers.

When the computing device 100 runs a warp, each computing unit 110 can run a thread in the warp. The multiple thread local registers 120 of each computing unit 110 are used to store data associated with the thread running on the computing unit 110, such as data required for the thread running or data generated by the thread running. The multiple thread local registers 120 are located near the computing unit 110, for example, on the same chip module as the computing unit 110, and can be directly accessed by the threads running on the computing unit 110.

In one example, the computing device 100 may be an AI chip, a GPU (Graphic Processing Unit), or a general-purpose computing unit CU (Computing Unit) in a general-purpose GPU (GPGPU), and the computing unit 110 may be a computing execution unit EU (Executing Unit) included in the general-purpose computing unit CU, etc. When the general-purpose computing unit CU runs a thread warp, each computing execution unit EU runs a thread in the thread warp according to task scheduling.

In addition, the computing device 100 may further include a shared buffer 130 for the plurality of computing units 110 . The shared buffer 130 is an on-chip memory of the computing device 100 and is used to exchange data between threads of the plurality of computing units 110 of the computing device 100 .

Currently, when a thread of each computing unit 110 is running, it can only access the thread local registers 120 of the computing unit 110. When the number of registers required to be used by a thread exceeds the number of thread local registers 120 of the computing unit 110, register overflow will occur.

One solution is to store the overflowed data in an off-chip memory of the computing device 100, such as a thread local memory (TLM), to ensure that the thread is executed normally. However, in this implementation, the compiler has a large access overhead to the off-chip memory, which will cause a huge loss in computing performance.

To solve the above problem, in the solution disclosed in the present invention, a part of the shared buffer 130 of the computing device is logically configured as a dedicated space for a warp or each thread so as to be used as a virtual register having a similar function to the thread local register 120 .

2 is a schematic diagram of the structure of a computing device 200 according to an embodiment of the present invention. The computing device 200 shown in FIG2 differs from the computing device 100 shown in FIG1 in that a portion of the shared buffer 130 is configured as a virtual register 132 for multiple computing units 110 of the computing device 200.

Since the thread running on the computing unit 110 can only directly access the thread local register 120 of the computing unit 110, in order to access the virtual register 132, at least one thread local register among the multiple thread local registers 120 of the computing unit 110 is configured as a transfer register for the thread running on the computing unit 110 to access the virtual register 132. In this case, the transfer register is only used for transfer between the thread on the computing unit 110 and the virtual register 132 in the shared buffer 130, and is not used to store the relevant data of the computing unit 110.

The transfer register is usually performed by the last one or more thread local registers 120 of each computing unit 110. For example, in FIG2 , the thread local register 120-4 can be used as the transfer register of the computing unit 110. Note that one transfer register is used as an example for description herein, but those skilled in the art can understand that the number of transfer registers of each computing unit 110 can be configured to one or more as required. In addition, the transfer register can be pre-fixedly configured in hardware, or can be flexibly configured as required by software (such as software of the control device of the computing device 200).

There may be two different types of thread operations for the warp operation of the computing device 200. In one type of thread operation, each thread in the warp performs the same operation on different data. In this case, a different virtual register needs to be configured for each thread for the operation of the corresponding thread, as described below in conjunction with FIG. 3A. In another type of thread operation, each thread in the warp performs the same operation on the same data. In this case, a virtual register may be uniformly configured for the entire warp for the operation of all threads, as described below in conjunction with FIG. 3B.

FIG3A shows a schematic diagram of a computing device 200 for a thread operation according to an embodiment of the present invention. As shown in FIG3A , the virtual register 132 includes one or more thread virtual registers 1322 dedicated to the thread of each computing unit 110, respectively. In this case, each computing unit 110 is configured to access the one or more thread virtual registers 1322 through the transfer register (such as the thread local register 120-4) of the computing unit 110 when running the thread. Here, the number of thread virtual registers 1322 of each computing unit 110 can be implemented by hardware pre-configuration, or flexibly configured as needed by software (such as software of a control device of the computing device 200). In some instances, the number of thread virtual registers 1322 of each computing unit 110 can be set to 1/2 to 2 times the number of thread local registers 120 of the computing unit 110.

The access to the thread virtual register 1322 by the threads of the computing unit 110 includes a write operation and a read operation.

For the write operation of the thread virtual register 1322, when the computing unit 110 determines that its thread wants to write data to one or more of its thread virtual registers 1322, the computing unit 110 writes the data to the transfer register of the computing unit 110 (such as the thread local register 120-4), and the transfer register writes the data to the thread virtual register 1322 of the computing unit 110.

More specifically, for example, when the computing unit 110 runs the thread, it can write the generated data into its multiple thread local registers 120 in sequence. When the data reaches a transfer register (such as thread local register 120-4) in the multiple thread local registers 120, the transfer register can directly write the written data into the thread virtual register 1322 of the computing unit 110, and so on until all thread virtual registers 1322 are filled.

For the read operation of the thread virtual register 1322, when the computing unit 110 determines that its thread wants to read data from the thread virtual register 1322, the computing unit 110 sends a read request to its transfer register (such as the thread local register 120-4), and the transfer register reads the data from the thread virtual register 1322 of the computing unit 110 in response to the read request for reading by the thread running by the computing unit 110.

More specifically, for example, when the computing unit 110 runs the thread, it needs to read the data required by the thread from its multiple thread local registers 120 in sequence. When the transfer register (such as the thread local register 120-4) in the multiple thread local registers 120 is read, the transfer register can read data from the thread virtual register 1322 of the computing unit 110, and the computing unit 110 can read the required data from the transfer register, for example, through software code or hardware configuration.

FIG3B shows a schematic diagram of a computing device 200 for another thread operation according to an embodiment of the present invention. As shown in FIG3B , the virtual register 132 includes one or more warp virtual registers 1324 shared by warps of multiple computing units 110. In this case, each computing unit 110 is configured to access the one or more warp virtual registers 1324 through the transit register (such as the thread local register 120-4) of the computing unit 110 when running the warp. Similarly, the number of warp virtual registers 1324 can also be implemented by hardware pre-configuration, or flexibly configured as needed by software (such as software of a control device of the computing device 200). In some instances, the number of warp virtual registers 1324 can be set to be tens of times the number of thread local registers 120 of each computing unit 110.

Similarly, access to the warp virtual register 1324 by the warps executed by the plurality of computing units 110 of the computing device 200 includes write operations and read operations.

For the write operation of the thread warp virtual register 1324, when it is determined that the thread warps executed by multiple computing units 110 are to write data to one or more thread warp virtual registers 1324, one computing unit 110 among the multiple computing units 110 (for example, computing unit 110-1) writes the data into a transfer register (such as thread local register 120-4) of the computing unit 110, and the transfer register writes the data into the thread warp virtual register 1324.

More specifically, for example, when multiple computing units 110 are running the thread warp, each computing unit 110 may write the generated data into its multiple thread local registers 120 in sequence. When the data reaches the transit register (such as thread local register 120-4) in the multiple thread local registers 120, the transit register may directly write the written data into the thread warp virtual register 1324 shared by the multiple computing units 110, and so on until all the thread warp virtual registers 1324 are filled. Here, since the threads of the multiple computing units 110 perform the same operation on the same data, the data generated in each computing unit 110 is the same. In this case, only the designated computing unit 110 may write to the thread warp virtual register 1324, or the multiple computing units 110 may write to the thread warp virtual register 1324 respectively. In the latter case, the data written by the later computing unit will overwrite the earlier data.

For the read operation of the warp virtual register 1324, when it is determined that the warp executed by the plurality of computing units 110 is to read data from the warp virtual register 1324, each computing unit 110 in the plurality of computing units 110 sends a read request to its respective transfer register (such as the thread local register 120-4), and each transfer register reads the data from the warp virtual register 1324 in response to the read request for reading by the thread executed by the corresponding computing unit 110.

More specifically, for example, during the execution of the thread warp, each computing unit 110 needs to read the data required for the thread warp from its multiple thread local registers 120 in sequence. When a transfer register (such as thread local register 120-4) among the multiple thread local registers 120 is read, the transfer register can read data from the thread warp virtual register 1324, and enable the computing unit 110 to read the required data from the corresponding transfer register.

Alternatively, in the case where the shared cache 130 has a broadcast function, when it is determined that the thread warps executed by multiple computing units 110 need to read data from the thread warp virtual register 1324, each computing unit 110 can send a read request to the corresponding transfer register, and only the transfer register of one computing unit 110 reads the data from the thread warp virtual register 1324 and broadcasts it to multiple computing units 110 through a broadcast operation.

Herein, when the transfer register is configured by software, one or more thread local registers 120 of the computing unit 110 can be configured as transfer registers according to the currently running thread warp. For example, assuming that the currently running thread warp has a high requirement for the speed of data reading and writing, multiple transfer registers (such as 2) can be configured, so that the reading and writing of two registers can be performed at one time.

In addition, when the virtual thread registers 1322 are configured by software, a required number of virtual thread registers 1322 may be configured in the shared buffer 130 by software instructions before the warp is executed, according to the warp to be executed.

Similarly, when the virtual warp registers 1324 are configured by software, a required number of virtual warp registers 1324 may be configured in the shared buffer 130 by software instructions before the warps are executed, according to the warps to be executed.

Note that although the virtual thread registers 1322 and the virtual thread warp registers 1324 are respectively shown and described above in Figures 3A and 3B, in some embodiments, the shared cache 130 may include both virtual thread registers 1322 dedicated to each computing unit 110 and virtual thread warp registers 1324 shared by multiple computing units 110.

FIG4 shows an exemplary flow chart of a method 400 for configuring a virtual register 132 for a computing device 200 according to an embodiment of the present invention. The computing device 200 is, for example, as shown above in conjunction with FIG2 , FIG3A , and FIG3B . The method 400 may be executed by a code solidified in the computing device 200, or may be controlled by a control device of the computing device 200 (for example, when the computing device 200 is a general purpose computing unit CU in a GPGPU, the control device may be a central processing unit CPU for controlling the computing device 200) through software.

As shown in FIG. 4 , the method 400 includes block 410 , in which a portion of the shared buffer 130 is configured as a virtual register 132 for a plurality of compute units 110 .

At block 420 , at least one thread local register 120 of the plurality of thread local registers 120 of each computing unit 110 may be configured as a transit register for the thread running on the computing unit 110 to access the virtual register 132 .

In some embodiments, block 410 may include configuring one or more thread virtual registers 1322 that are dedicated to the threads of each computing unit 110. In this case, method 400 also includes configuring each computing unit 110 to access the one or more thread virtual registers 1322 through the transit register of the computing unit 110 when running the thread.

Specifically, for write operations of the thread virtual register 1322, the computing unit 110 can be configured to write the data to the transfer register when it is determined that the thread wants to write data to one or more thread virtual registers 1322, and the transfer register can be configured to write the data to one or more thread virtual registers 1322 of the computing unit 110.

Specifically, for the read operation of the thread virtual register 1322, the computing unit 110 can be configured to send a read request to the transfer register when it is determined that the thread wants to read data from one or more thread virtual registers 1322, and the transfer register can be configured to read the data from one or more thread virtual registers 1322 of the computing unit in response to the read request for reading by the thread running the computing unit 110.

In some embodiments, block 410 may further include configuring one or more warp virtual registers 1324 shared by warps of multiple compute units 110. In this case, method 400 further includes configuring each compute unit 110 to access the one or more warp virtual registers 1324 through a transit register of the compute unit 110 when executing the warp.

Specifically, for the write operation of the thread warp virtual register 1324, one of the multiple computing units 110 can be configured to write the data to the transfer register of the computing unit 110 when it is determined that the thread warp is to write data to one or more thread warp virtual registers 1324, and configure the transfer register to write the data to one or more thread warp virtual registers 1324.

Specifically, for the read operation of the thread virtual register 1322, each computing unit 110 in the multiple computing units 110 can be configured to send a read request to the respective transfer register when it is determined that the thread warp wants to read data from the thread warp virtual register 1324, and each transfer register can be configured to read the data from the thread warp virtual register 1324 in response to the read request for reading by the thread running by the corresponding computing unit 110.

Alternatively, for the read operation of the thread virtual register 1322, each computing unit 110 in the multiple computing units 110 can also be configured to send a read request to the transfer register of the computing unit 110 when it is determined that the thread warp wants to read data from the thread warp virtual register 1324, and only the transfer register of one of the computing units 110 reads the data from the thread warp virtual register 1324 in response to the read request and broadcasts it to multiple computing units 110.

By utilizing the solution of the present invention, by logically configuring a portion of the shared buffer of the computing device as a virtual register of a thread warp or each thread and configuring one or more of the existing thread local registers as transfer registers to perform data transfer between threads/thread warps and virtual registers, the number of thread local registers available to the computing device when running thread warps can be expanded, thereby avoiding performance degradation caused by register overflow, and the increase in the number of registers also provides a larger operating space for thread warps running on the computing device.

Those skilled in the art will appreciate that the computing device 200 shown in the figure is merely illustrative and may include more or fewer components.

The computing device 200 and the method 400 for configuring a virtual register according to the present disclosure are described above in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that the computing device 200 does not necessarily include all the components shown in the drawings, and may only include some or more components necessary to perform the functions described in the present disclosure, and the connection method of these components is not limited to the form shown in the drawings, and the method 400 may also include more steps not shown in the drawings.

The present invention may be implemented as a method, a computing device, a control device of the computing device, a computer-readable storage medium and/or a computer program product. A computer-readable storage medium stores a computer program code, which is used to execute the method of the present disclosure when it is executed. The computer program product includes a computer program, which executes the method of the present disclosure when it is executed. The computing device and/or the computing device may include at least one processor and at least one memory coupled to the at least one processor, and the memory may store instructions for execution by the at least one processor. When the instruction is executed by the at least one processor, the computing device and/or the control device may execute the above method.

In one or more exemplary designs, the functions described in the present disclosure may be implemented using hardware, software, firmware, or any combination thereof. For example, if implemented using software, the functions may be stored as one or more instructions or codes on a computer-readable medium, or transmitted as one or more instructions or codes on a computer-readable medium.

Those skilled in the art should also understand that the various illustrative logical blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments of the present disclosure may be implemented as electronic hardware, computer software, or a combination of the two.

The above description of the present disclosure is intended to enable any person of ordinary skill in the art to implement or use the present disclosure. Various modifications of the present disclosure are obvious to those of ordinary skill in the art, and the general principles defined herein may also be applied to other variations without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is consistent with the broadest scope of the principles and novel features disclosed herein.

Claims (19)

1. A computing device, comprising:

a plurality of computing units, each configured to run one thread of a thread bundle;

A plurality of thread local registers dedicated to each compute unit for registering data associated with threads operated by the compute unit; and

A shared buffer for the plurality of computing units,

Wherein a portion of the shared buffer is configured as a virtual register for the plurality of compute units and at least one of the plurality of thread local registers of each compute unit is configured as a staging register for threads operated by the compute unit to access the virtual register.

2. The computing device of claim 1, wherein the virtual registers comprise one or more thread virtual registers that are respectively dedicated to threads of each computing unit, and each computing unit is configured to access the one or more thread virtual registers through a staging register of the computing unit when running the thread.

3. The computing device of claim 2, wherein

The computing unit is configured to, upon determining that the thread is to write data to the one or more thread virtual registers, write the data to the staging register, and

The staging register is configured to write the data to one or more thread virtual registers of the computing unit.

4. The computing device of claim 2, wherein

The computing unit is configured to send a read request to the staging register upon determining that the thread is to read data from the one or more thread virtual registers, and

The staging register is configured to read the data from one or more thread virtual registers of the computing unit for reading by a thread run by the computing unit in response to the read request.

5. The computing device of claim 1, wherein the virtual registers comprise one or more thread bundle virtual registers that are shared by thread bundles of the plurality of computing units, and each computing unit is configured to access the one or more thread bundle virtual registers through a staging register of the computing unit when running the thread bundle.

6. The computing device of claim 5, wherein

Upon determining that the thread bundle is to write data to the one or more thread bundle virtual registers, one of the plurality of computing units is configured to write the data to a staging register of the computing unit, an

The staging register is configured to write the data to the one or more thread bundle virtual registers.

7. The computing device of claim 5, wherein

Upon determining that the thread bundle is to read data from the thread bundle virtual register, each of the plurality of computing units sends a read request to a respective staging register, and

Each staging register is configured to read the data from the thread bundle virtual register for reading by a thread operated by a corresponding compute unit in response to the read request.

8. The computing device of claim 5, wherein

Upon determining that the thread bundle is to read data from the thread bundle virtual register, each of the plurality of computing units sends a read request to a staging register of the computing unit, and

The staging register of one of the plurality of computing units is configured to read the data from the thread bundle virtual register in response to the read request and broadcast to the plurality of computing units.

9. A method of configuring virtual registers for a computing device, wherein the computing device comprises:

a plurality of computing units, each configured to run one thread of a thread bundle;

A plurality of thread local registers dedicated to each compute unit for registering data associated with threads operated by the compute unit; and

A shared buffer for the plurality of computing units,

The method comprises the following steps:

configuring a portion of the shared buffer as a virtual register for the plurality of computing units; and

At least one of the plurality of thread local registers of each compute unit is configured as a staging register for threads operated by the compute unit to access the virtual registers.

10. The method of claim 9, wherein configuring a portion of the shared buffer as a virtual register for the plurality of computing units comprises:

one or more thread virtual registers are configured that are respectively dedicated to threads of each compute unit, and the method further comprises:

Each compute unit is configured to access the one or more thread virtual registers through the staging registers of the compute unit while running the thread.

11. The method of claim 10, wherein configuring each computing unit to access the one or more thread virtual registers through a staging register of the computing unit while running the thread comprises:

Configuring the computing unit to write data to the staging register upon determining that the thread is to write the data to the one or more thread virtual registers, and

The staging register is configured to write the data to one or more thread virtual registers of the computing unit.

12. The method of claim 10, wherein configuring each computing unit to access the one or more thread virtual registers through a staging register of the computing unit while running the thread comprises:

configuring the computing unit to send a read request to the staging register upon determining that the thread is to read data from the one or more thread virtual registers, an

The staging register is configured to read the data from one or more thread virtual registers of the compute unit for reading by a thread run by the compute unit in response to the read request.

13. The method of claim 9, wherein configuring a portion of the shared buffer as a virtual register for the plurality of computing units comprises:

one or more thread bundle virtual registers shared by thread bundles of the plurality of compute units are configured, and the method further comprises:

each compute unit is configured to access the one or more thread bundle virtual registers through the transit registers of the compute unit while running the thread bundle.

14. The method of claim 13, wherein configuring each computing unit to access the one or more thread bundle virtual registers through a staging register of the computing unit while running the thread bundle comprises:

Configuring one of the plurality of compute units to write data to the one or more thread bundle virtual registers upon determining that the thread bundle is to write the data to the transit register of the compute unit, and

The staging register is configured to write the data to the one or more thread bundle virtual registers.

15. The method of claim 13, wherein configuring each computing unit to access the one or more thread bundle virtual registers through a staging register of the computing unit while running the thread bundle comprises:

configuring each of the plurality of compute units to send a read request to a respective staging register upon determining that the thread bundle is to read data from the thread bundle virtual register, and

Each transfer register is configured to read the data from the thread bundle virtual register in response to the read request for reading by a thread operated by the corresponding compute unit.

16. The method of claim 13, wherein configuring each computing unit to access the one or more thread bundle virtual registers through a staging register of the computing unit while running the thread bundle comprises:

Configuring each of the plurality of compute units to send a read request to a staging register of the compute unit upon determining that the thread bundle is to read data from the thread bundle virtual register, and

The staging register of one of the plurality of computing units is configured to read the data from the thread bundle virtual register in response to the read request and broadcast to the plurality of computing units.

17. A control apparatus comprising:

At least one processor; and

At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, which when executed by the at least one processor, cause the control device to perform the steps of the method according to any one of claims 9 to 16.

18. A computer readable storage medium having stored thereon computer program code which, when executed, performs the method of any of claims 9 to 16.

19. A computer program product comprising a computer program which, when executed by a machine, performs the method of any of claims 9 to 16.