CN117949818A - FPGA-based general MCU chip function verification system and method - Google Patents

Abstract

The invention discloses a general MCU chip function verification system and method based on FPGA, the system mainly includes a main verification board, a function board, an upper computer, a power supply and a testing instrument; the main verification board is connected with the functional board through an interface and used for verifying the functions of the MCU chip; the testing instrument comprises an oscilloscope, a universal meter, a spectrum analyzer and a logic analyzer, and is used for system debugging and auxiliary verification of a testing result; the upper computer is used for compiling and downloading a main verification board program, comparing verification data with MPLAB X IDE engineering test case generation data and generating a verification report. The system verification mode is divided into a full-function automatic verification mode and a key control selection function verification mode, and is applicable to most chip function verification requirements; meanwhile, three modes are provided for obtaining the verification result, so that the accuracy of the verification result is improved; the invention ensures the accuracy and the perfection of the functions of the MCU chip by carrying out the cooperative verification of software and hardware on the MCU chip.

Description

A general MCU chip function verification system and method based on FPGA

Technical Field

The present invention relates to the field of integrated circuits, and in particular to a general MCU chip function verification method based on FPGA.

Background technique

In modern electronic devices, microcontroller unit (MCU) chips are widely used in various application fields, such as embedded systems, Internet of Things, industrial automation, etc. Whether the MCU chip function is perfect will directly affect the stable operation of the entire application system. In order to obtain high-quality and highly reliable chip products, chip verification has become an important link throughout the integrated circuit design, manufacturing, production, and chip quality assurance.

Currently, functional tests of MCU chips are mostly conducted in wafer packaging and testing plants, using automatic test equipment (ATE), such as the V93000 machine developed by Advantest, an American company, to apply stimulus signals to the chip under test through probes, and the test data is displayed and saved on the PC. However, for the very few problematic chips that appear after packaging and testing, they rely entirely on large-scale testing machines in packaging and testing plants, which is costly, time-consuming, and not conducive to problem feedback.

There are many patents for MCU chip function verification that are separated from large-scale test machines, but most of them face the following problems:

(1) Verification results usually require manual verification, and verification data reports cannot be obtained.

(2) The entire system usually contains multiple functions. When special function verification is required, it is often necessary to modify the system code, and the verification process is extremely cumbersome.

(3) The method for obtaining verification results is single, and when there are doubts about the verification data, the verification results cannot be verified.

(4) The chip to be verified and each functional module are integrated into the same circuit board, which makes the entire verification system bulky. When other functional modules need to be expanded, the hardware of the entire verification system will need to be reconstructed.

In summary, overcoming the defects of existing chip function verification technology is an urgent problem to be solved in this technical field.

Summary of the invention

The purpose of the present invention is to provide a general MCU chip function verification system and method based on FPGA. The invention verifies the software and hardware of the MCU chip to find out whether there are defects in the design and ensure the accuracy and completeness of the MCU chip function.

In order to solve the above technical problems, the present invention provides a general MCU chip function verification system and method based on FPGA, including a main verification board, a function board, a host computer, a power supply and a test instrument;

The main verification board is connected to the function board via an interface to verify the function of the MCU chip;

The power supply provides 5V, 0.5A power for the entire functional verification system;

The test instruments include oscilloscopes, multimeters, spectrum analyzers and logic analyzers, which are used for system debugging and auxiliary verification of test results;

The host computer is used to compile and download the main verification board program and compare the verification data with the data generated by the MPLAB X IDE engineering test case to generate a verification report.

The general MCU chip function verification system based on FPGA includes the following on the main verification board: FPGA chip, button control circuit, power circuit, signal indicator circuit, MCU_SQI circuit, USB interface circuit, JTAG harness isolation circuit, clock circuit, FPGA debugging and downloading circuit, MCU chip interface and function board interface.

The function of the button control circuit in the main verification board is to enable the system to have the ability to verify special functions; multiple functional modules are usually integrated in the functional module, and the operation button control circuit can select a separate function item for verification.

The interface circuits in the main verification board mainly include the MCU chip interface and the function board interface. The MCU chip interface can be used to expand other chips of the same type, and the function board interface can be used to expand other functions to be verified.

The signal indicator light circuit in the main verification board is used to display whether the verification result is passed and whether the verification program is downloaded successfully.

The general MCU chip function verification system based on FPGA includes: IIS module, CAN module, IRDA module, TTL module, LIN module, ETH module, SIM module and MEM module on the function board. Each function module is used to verify the development function of the MCU chip.

The FPGA-based general MCU chip function verification system can obtain verification reports in the following three ways:

(1) Preferably, under the normal working process of the system, the data in the MCU chip register is compared with the data generated by the MPLAB X IDE project test case to generate a verification report.

(2) Optionally, the function board interface circuit is directly connected to the host computer, and the host computer software is debugged to obtain verification data. The verification data is manually verified with the data manual or the data generated by the MPLAB X IDE project test case, and the verification results are checked to generate a verification report.

(3) Optionally, obtain verification data or waveforms through a test instrument, perform statistical analysis on the data or waveforms, and generate a verification report.

The FPGA-based general MCU chip function verification system is in a full-function automatic verification state under default conditions, that is, each function item is automatically verified according to the compilation process. Each function item will generate a corresponding verification report and save it to the project file.

Compared with the prior art, the present invention has the following beneficial effects:

(1) The present invention uses the FPGA chip as a bridge for chip verification through a one-to-one mapping between the MCU chip and the FPGA chip pins, thereby simplifying the hardware structure of the verification platform, shortening the verification cycle, improving the verification efficiency, and reducing the cost. In addition, the FPGA chip can realize the caching of verification data and cross-clock domain processing.

(2) The present invention provides a general MCU chip function verification method and system based on FPGA. The system is designed with two modes: full-function automatic verification and key control function module verification, which are applicable to most chip function verification requirements. The system design interface circuit enhances the scalability of the entire verification system, and at the same time makes the entire verification system miniaturized, which is easy to carry or transport. The diversity of verification results makes the verification results more reliable. The data in the MCU chip register is compared with the data generated by the MPLAB X IDE engineering test case, and a verification report is generated, making the verification results clearly visible.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a general MCU chip function verification system based on FPGA provided by the present invention;

FIG2 is a detailed structural diagram of a general MCU chip function verification system based on FPGA provided by the present invention;

FIG3 is a flow chart of a general MCU chip function verification system based on FPGA provided by the present invention;

Detailed ways

The specific implementation method of the present invention is described in detail below with reference to the accompanying drawings.

Please refer to Figure 1, which is a schematic diagram of the structure of a general MCU chip function verification system based on FPGA, which mainly includes a main verification board, a function board, a host computer, a power supply and a test instrument; the main verification board and the function board are connected through an interface to verify the function of the MCU chip; the power supply provides 5V, 0.5A power for the entire function verification system; the test instrument includes an oscilloscope, a multimeter, a spectrum analyzer and a logic analyzer, which are used for system debugging and auxiliary verification of test results; the host computer is used to compile and download the main verification board program and compare the verification data with the data generated by the MPLAB X IDE engineering test case to generate a verification report.

Please refer to Figure 2, which is a detailed structural diagram of the general MCU chip function verification system based on FPGA. In the example Figure 2, the main verification board includes: FPGA chip, key control circuit, power circuit, signal indicator circuit, MCU_SQI circuit, USB interface circuit, JTAG harness isolation circuit, clock circuit, FPGA debugging and downloading circuit, MCU chip interface circuit and function board interface circuit. The function board includes: IIS module, CAN module, IRDA module, TTL module, LIN module, ETH module, SIM module and MEM module. Each function module is used to verify the development function of the MCU chip.

The detailed description of some modules of the main verification board in Example Figure 2 includes:

(1) The FPGA chip in the main verification board uses the Cyclone series EP1C12Q240C8N chip as the intermediate medium between the MCU chip to be verified and the function board. The MCU chip pins are mapped one by one to the FPGA chip pins to send functional IP verification instructions and verify data caching and system cross-clock domain processing.

(2) The key control circuit in the main verification board enables the system to have special function verification. This design not only saves the tediousness of code modification, but also makes each module independent during verification.

(3) The power supply circuit in the main verification board uses the NCP59744MN2ADJTBG low-voltage dropout linear regulator chip to ensure that the entire verification system can obtain a stable power supply.

(4) The signal indicator circuit in the main verification board is used to display whether the verification result is passed and whether the verification program is downloaded successfully.

(5) The MCU_SQI circuit in the main verification board uses the SST26VF064B-104I/SM Flash memory chip to store the MCU chip MPLAB X IDE project program.

(6) The JTAG harness isolation circuit in the main verification board can disconnect the harness when a conflict occurs between the MPLAB X IDE project and the Quartus II project to ensure smooth downloading of the project files.

(7) The clock circuit in the main verification board is divided into MCU clock and FPGA clock. An integrated switch is used in the MCU clock module to manually switch between an external active 24M crystal oscillator and an external passive 24M crystal oscillator; the FPGA clock circuit is set to input a 50MHz crystal oscillator.

(8) The FPGA debugging and downloading circuit of the verification board in the main verification board sets the FPGA_ASP and FPGA_JTAG interfaces. Both interfaces can be used to download FPGA programs, but the difference is that the ALTERA_ASP interface pins are connected to the EPCS4 non-volatile storage chip. When the system is powered off, the program is saved. After the ALTERA_JTAG interface downloads the program, the power-off program needs to be reloaded.

(9) The MCU chip interface circuit in the main verification board is used to connect the MCU chip to be verified with the main verification board. This design can flexibly expand the functional verification of other chips of the same type.

(10) The function board interface circuit in the main verification board uses a 9001-11961C00A connector to connect the main verification board to the function board.

Please refer to Figure 3, which is a schematic diagram of the process flow of a general MCU chip function verification system based on FPGA. Example Figure 3 includes:

Step 1: The host computer compiles and downloads the verification program to the FPGA chip and MCU chip through the Quartus II project and MPLAB X IDE project respectively. When the Quartus II project and MPLAB X IDE project are successfully downloaded to the main verification board, the yellow and blue indicators in the main verification board flash alternately.

Step 2, detecting whether there is a function key command input;

Step 3, when a key is pressed, the FPGA chip sends a function item verification instruction corresponding to the key circuit to the MCU chip to be verified; after a delay of 5 seconds, when no key is pressed, the FPGA chip sends function item verification instructions to the MCU chip to be verified one by one according to the program compilation process;

Step 4: The MCU chip executes the corresponding function item program and feeds back the operation result to the FPGA chip;

Step 5: FPGA receives the instruction and drives the corresponding functional modules in the control function board to run;

Step 6: The function board feeds back the verification data to the FPGA chip, and the FPGA caches the data; or the function board feeds back the verification data to the host computer through the data transmission line; or the function board feeds back the verification data to the test instrument through the test line;

Step 7, FPGA feeds back the cached verification data to the MCU chip, and the MCU chip stores the data; or observes the verification result by debugging the host computer software; or observes the verification result by debugging the test instrument;

Step 8: Compare the data in the MCU chip register with the data generated by the MPLAB X IDE project test case and generate a verification report.

Example

The following is a detailed description of the functional verification example of the present invention in conjunction with the accompanying drawings and specific implementation methods.

The construction of a general MCU chip function verification platform based on FPGA includes:

Step 1, hardware configuration, connect the MCU chip to be verified through the MCU chip interface on the main verification board, and connect the JTAG interface of the MCU chip and the FPGA chip to the USB interface of the host computer respectively; connect the main verification board and the function board through the function verification interface, connect the function module to be verified in the function board to the host computer or the test instrument through the debugging interface, and configure a 5V, 0.5A power supply;

Step 2, software configuration, configure the FPGA chip through the Quartus II project on the host computer and the MCU chip through the MPLAB X IDE project, compile and download the project to the main verification board. At this time, the yellow and blue indicators in the main verification board flash alternately, the program is downloaded successfully, and the drive control function board works.

After the verification platform is built, the system will automatically detect whether there is any key control command input. If the system detects that there is no key control command input, the Quartus ll project will run and send the first function (IIS) module verification command. After the MPALAB project receives the verification command from the FPGA, it runs the first function (IIS) initialization function and function verification function.

Check the verification progress in the MPLAB X IDE software program running result window on the host computer, and open the MPLAB X IDE software observation window to view the register data. By default, the verification stops automatically after 5000 received data are verified. Compare each data in the register with the data generated by the MPLAB X IDE project test case, generate a verification report and store it; at the same time, the data comparison accuracy reaches 100%, the verification is passed, and the green LED light on the main verification board is on.

When the IIS function module is verified, the system will automatically jump to verify the next function module until all function modules are verified.

If there is any doubt about the verification result of a certain functional module in the automatic verification, you can use the button to control the module to re-verify; you can also re-obtain the verification result by changing the way to obtain the verification data; or use the two methods in combination; this will not affect the verification results of other modules and can also save verification time.

The above-described embodiments are only the optimal implementation schemes of the present invention, but are not limited thereto in specific applications. It should be pointed out that any improvements and modifications based on the technical principles of the present invention are within the protection scope of the present invention.

Claims (10)

1. A general MCU chip function verification system based on FPGA, characterized by comprising a main verification board, a function board, a host computer, a power supply and a test instrument; The main verification board is connected to the function board via an interface to verify the function of the MCU chip; The power supply provides 5V, 0.5A power for the entire functional verification system; The test instruments include oscilloscopes, multimeters, spectrum analyzers and logic analyzers, which are used for system debugging and auxiliary verification of test results; The host computer is used to compile and download the main verification board program and compare the verification data with the data generated by the MPLAB X IDE engineering test case to generate a verification report. 2. The FPGA-based general MCU chip function verification system as described in claim 1 is characterized in that the main verification board includes: FPGA chip, button control circuit, power supply circuit, signal indicator circuit, MCU_SQI circuit, USB interface circuit, JTAG harness isolation circuit, clock circuit, FPGA debugging and downloading circuit, MCU chip interface and function board interface. 3. The FPGA-based general MCU chip function verification system as described in claim 1 is characterized in that the function board includes: IIS module, CAN module, IRDA module, TTL module, LIN module, ETH module, SIM module and MEM module, and each function module is used to verify the development function of the MCU chip. 4. The FPGA-based universal MCU chip function verification system as described in claim 2 is characterized in that when multiple functional modules are integrated in the functional module, a key control circuit can be used to individually verify a certain function item of the chip. 5. The FPGA-based universal MCU chip function verification system as described in claim 2 is characterized by a signal indicator light circuit, which is used to display whether the verification result is passed and whether the verification program is downloaded successfully. 6. The FPGA-based universal MCU chip function verification system as claimed in claim 2, characterized in that the JTAG harness isolation circuit can disconnect the harness when a conflict occurs between the MPLAB X IDE project and the Quartus II project, thereby ensuring that the project file can be downloaded smoothly. 7. The FPGA-based general MCU chip function verification system as described in claim 2 is characterized in that the interface circuit mainly includes an MCU chip interface and a function board interface, the MCU chip interface can be used to expand other chips of the same type, and the function board interface can be used to expand other functions to be verified. 8. The FPGA-based universal MCU chip function verification system according to any one of claims 1 to 7, characterized in that the verification system hardware construction includes: The main verification board is connected to a DC regulated power supply via a power interface; The main verification board is connected to the MCU chip to be verified through the MCU chip interface; The host computer is connected to the JTAG interface in the main verification board via a USB interface; The function board is connected to the main verification board via a function board interface; Each functional module in the functional board is connected to a host computer or a test instrument via a debugging interface. 9. A method for verifying the function of a general MCU chip based on FPGA as claimed in claim 8, characterized in that the verification system is in a fully automatic verification state, comprising: Step 1, the host computer will detect whether there is a function key command input, and the detection state will last for 5 seconds. After 5 seconds, if no key command input is detected, the FPGA chip will send function item verification instructions to the MCU chip to be verified one by one according to the program compilation process; Step 2, the MCU chip to be verified executes the corresponding function item program and feeds back the operation result to the FPGA chip, and the FPGA chip receives the instruction and drives the corresponding function module in the control function board to run; Step 3, the function board feeds back the verification data to the FPGA chip, and the FPGA chip caches the data; Step 4, the FPGA chip feeds back the cached verification data to the MCU chip, and the MCU chip stores the data; Step 5, comparing the data in the MCU chip register with the data generated by the MPLAB X IDE engineering test case to generate a verification report; The above steps will stop after all verification items corresponding to the verification instructions are verified. 10. The FPGA-based universal MCU chip function verification method according to claim 9, wherein there are three ways to obtain the verification report: (1) Under the normal working process of the system, the data in the MCU chip register is compared with the data generated by the MPLAB X IDE project test case to generate a verification report; (2) Connect directly to the host computer through the function board interface circuit, debug the host computer software to obtain verification data, manually verify the verification data with the data manual or the data generated by the MPLAB X IDE project test case, check the verification results, and generate a verification report; (3) Obtain verification data or waveforms through test instruments, perform statistical analysis on the data or waveforms, and generate a verification report.