CN117935900A - Memory chip detection method and device and computer equipment - Google Patents
Memory chip detection method and device and computer equipment Download PDFInfo
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Abstract
The application relates to a memory chip detection method, a memory chip detection device and computer equipment. The memory chip detection method comprises the following steps: configuring a main program, an interrupt program and an interrupt signal; the interrupt program comprises a read-write interrupt program; associating the interrupt signal with the interrupt program; running the main program, and interrupting the main program to run the interrupt program when the interrupt signal occurs; the read-write result fed back by the interrupt program of the memory chip is obtained, and the detection result of the memory chip is judged based on the read-write result, so that the accuracy of the detection result of the memory chip is improved, and the real-time performance of the detection of the memory chip is also improved.
Description
Technical Field
The present application relates to the field of chip detection technologies, and in particular, to a method and apparatus for detecting a memory chip, and a computer device.
Background
With the development of semiconductor technology, the performance of the memory chip is continuously improved, and an effective memory chip detection method is important to further improve the performance of the memory chip. For example, an SRAM (Static Random-Access Memory) TQV chip based on an SRAM (Static Random-Access Memory) needs a reasonably designed and efficient method to realize the detection of the performance of the SRAM TQV chip in order to ensure the performance thereof.
In the related art, a testing machine is generally adopted to detect the read-write performance of a memory chip; however, in practical application, the testing machine adopted in the related art cannot meet the requirement of higher real-time control when detecting the read-write performance of the memory chip, and further cannot ensure the accuracy of the detection result of the memory chip, that is, the accuracy of the detection of the memory chip is lower.
Aiming at the problem of lower detection accuracy of a memory chip in the prior art, no effective solution is proposed at present.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, an apparatus, and a computer device for detecting a memory chip.
In a first aspect, the present application provides a method for detecting a memory chip, the method comprising:
configuring a main program, an interrupt program and an interrupt signal; the interrupt program comprises a read-write interrupt program;
Associating the interrupt signal with the interrupt program;
running the main program, and interrupting the main program to run an interrupt program when the interrupt signal occurs;
and acquiring a read-write result fed back by the memory chip based on the interrupt program, and judging the detection result of the memory chip based on the read-write result.
In one embodiment, the configuring the main program, the interrupt program, and the interrupt signal includes:
Configuring a rising edge or a falling edge of a clock signal as an interrupt signal;
dividing tasks in the testing process of the memory chip according to the intensity of real-time requirements, configuring tasks with high real-time requirements as interrupt programs, and configuring tasks with low real-time requirements as main programs.
In one embodiment, the running the main program and interrupting the main program from running the interrupt program when the interrupt signal occurs includes:
running the main program and acquiring an interrupt program identifier when the interrupt signal occurs;
if the interrupt program identifier is a first preset identifier, the interrupt program identifier is adjusted to a second identifier, and the main program is interrupted to run the interrupt program; when the running of the interrupt program is finished, the interrupt program identification is adjusted to be a first preset identification, and a main program is run;
and if the interrupt program identifier is a second preset identifier, stopping running the main program and the interrupt program.
In one embodiment, the running the main program and interrupting the main program from running the interrupt program when the interrupt signal occurs includes:
running the main program, and detecting whether an interrupt program exists currently when the interrupt signal occurs;
If the interrupt program exists, the interrupt main program runs the interrupt program, and the main program is run after the interrupt program runs.
In one embodiment, the interrupt main program runs an interrupt program, and running the main program after the interrupt program runs is finished includes:
configuring a plurality of interrupt programs, and setting priority for each interrupt program;
when the interrupt signal occurs, interrupting the main program, and detecting a plurality of interrupt programs;
And acquiring the priorities of the interrupt programs, sequentially operating all the interrupt programs according to the current priority from high to low, and operating the main program after the operation of all the interrupt programs is finished.
In one embodiment, the interrupt main program runs an interrupt program, and running the main program after the interrupt program runs is finished includes:
when the interrupt signal occurs, the main program is interrupted to run the first interrupt program, and whether a new second interrupt program to be run is present or not is continuously detected;
if the second interrupt program appears, the priority of the first interrupt program and the priority of the second interrupt program are obtained;
If the priority of the first interrupt program is higher than that of the second interrupt program, continuing to operate the first interrupt program, operating the interrupt program with the highest priority to be operated after the operation of the first interrupt program is finished, and operating the main program after the operation of all interrupt programs is finished;
If the priority of the first interrupt program is lower than that of the second interrupt program, the first interrupt program is interrupted to operate the second interrupt program, the interrupt program with the highest priority to be operated is operated after the operation of the second interrupt program is finished, and the main program is operated after the operation of all interrupt programs is finished.
In one embodiment, the obtaining the read-write result fed back by the storage chip based on the interrupt program, and determining the detection result of the storage chip based on the read-write result includes:
setting a detection strategy, wherein the detection strategy is used for determining data to be stored of an address in the memory chip;
running the read-write interrupt program, and writing data into the memory chip according to the detection strategy;
Running the read-write interrupt program, reading the data of the memory chip, and feeding back a read-write result;
And judging the detection result of the storage chip according to the detection strategy and the read-write result.
In one embodiment, the method further comprises:
configuring a communication interrupt program; the priority of the communication interrupt program is lower than that of the read-write interrupt program;
And when the communication interrupt program is operated, the internal module of the storage chip performs information interaction, or the storage chip performs information interaction with an external terminal.
In one embodiment, the method further comprises:
and acquiring a detection strategy transmitted by the external terminal, and configuring a read-write interrupt program based on the detection strategy.
In a second aspect, the present application further provides a memory chip detection apparatus, the apparatus including:
The configuration module is used for configuring the main program, the interrupt program and the interrupt signal; the interrupt program comprises a read-write interrupt program;
the association module is used for associating the interrupt signal with the interrupt program;
the program running module is used for running the main program and interrupting the main program to run an interrupt program when the interrupt signal occurs;
and the detection module is used for acquiring a read-write result fed back by the memory chip based on the interrupt program and judging the detection result of the memory chip based on the read-write result.
In a third aspect, the present application also provides a computer device comprising a memory storing a computer program and a processor implementing the method according to any one of the embodiments of the first aspect when the processor executes the computer program.
The method, the device and the computer equipment for detecting the memory chip need to be configured with a main program, an interrupt program and an interrupt signal; wherein the interrupt program comprises a read-write interrupt program; secondly, associating the interrupt signal with the interrupt program; further, running the main program, and interrupting the main program to run the interrupt program when the interrupt signal occurs; and finally, acquiring a read-write result fed back by the memory chip based on the interrupt program, judging the detection result of the memory chip based on the read-write result, improving the detection accuracy of the memory chip, and meeting the requirement of the detection of the memory chip on real-time performance.
Drawings
The drawings described herein are designed to provide a further understanding of the application. The illustrative embodiments of the application and their description form part of this application and are not intended to limit the application in any way. In the drawings:
FIG. 1 is a flow chart of a method for detecting a memory chip according to an embodiment;
FIG. 2 is a timing diagram of the operation of a memory chip in one embodiment;
FIG. 3 is a block diagram of a memory chip testing device in one embodiment;
fig. 4 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these" and similar terms in this application are not intended to be limiting in number, but may be singular or plural. The terms "comprising," "including," "having," and any variations thereof, as used herein, are intended to encompass non-exclusive inclusion; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this disclosure, merely distinguish similar objects and do not represent a particular ordering for objects.
In one embodiment, as shown in fig. 1, fig. 1 is a flow chart of a method for detecting a memory chip in one embodiment, where the method for detecting a memory chip includes the following steps:
Step S101, configuring a main program, an interrupt program and an interrupt signal; the interrupt routine includes a read-write interrupt routine.
The main program is used for running other task programs except the interrupt program, and the other task programs comprise, but are not limited to, judging whether an interrupt condition is met or not, namely, whether an interrupt signal of the interrupt program is triggered or not. The interrupt program at least comprises a read-write interrupt program; the read-write interrupt program comprises a read interrupt program and a write interrupt program; a read interrupt program for reading data from a read address of the memory chip according to the control signal; a write interrupt program for writing data into a write address of the memory chip according to the control signal; the control signal comprises a high level signal and a low level signal and is used for adjusting the operation type of the current memory chip, wherein the operation type at least comprises a writing operation and a reading operation; if the control signal is a high level signal, the memory chip performs a write operation; if the control signal is a low level signal, the memory chip enters a read operation.
The interrupt signal may be a rising edge of a clock signal, or a falling edge of the clock signal, or even other signals, which are used for triggering an interrupt program; wherein the clock signal comprises a clock frequency for providing the operating frequency to the memory chip or is kept in synchronization with the internal clock signal of the memory chip, i.e. with the internal clock frequency of the memory chip.
It should be noted that, in this embodiment, the main program, the interrupt program and the interrupt signal are all related configurations of the testing machine; the testing machine is used for realizing the detection of the memory chip; the testing machine is also used for generating or synchronizing clock signals, and is responsible for generating clock signals required by the memory chip if the clock signals of the memory chip are required to be provided by the outside; if the clock signal of the memory chip is generated by the memory chip, the testing machine is responsible for synchronizing the clock signal of the memory chip.
It should be noted that, the memory chip is provided with a pad for being used as an external interface, and the external interface comprises a data path, an address path and a control path; the data path is used for writing data or reading data; an address path for writing an address corresponding to data or reading an address corresponding to data; and the control path is used for transmitting the control signal and realizing the adjustment of the operation type of the memory chip.
Step S102, the interrupt signal is associated with the interrupt program.
Preferably, if the memory chip is a write operation or a read operation, it is necessary to ensure that signals related to the write operation or the read operation remain stable near the rising edge or the falling edge of the clock signal, i.e., in a period of time before and after the rising edge or the falling edge of the clock signal; if the write operation or the read operation of the memory chip needs to be adjusted, the control signal needs to be arranged outside a period of time before and after the rising edge or the falling edge of the clock signal. For example, the rising edge of the clock signal is configured as an interrupt signal of the interrupt program, and the interrupt signal, i.e. the rising edge of the clock signal, is associated with the interrupt program, ensuring that the relevant interrupt program is triggered when the rising edge of the clock signal arrives.
Step S103, the main program is run, and the main program is interrupted to run the interrupt program when the interrupt signal occurs.
Specifically, based on the interrupt signal, when the interrupt signal occurs each time, the operation of the main program is interrupted, the operation jumps to the interrupt program, and the related tasks of the interrupt program are operated; and after the running of the interrupt program is finished, returning to the main program again, and running related tasks of the main program.
Step S104, a read-write result fed back by the memory chip based on the interrupt program is obtained, and the detection result of the memory chip is judged based on the read-write result.
The read-write result is used for judging whether the read-write performance of the memory chip accords with the expected result or not; the expected result refers to a preset read-write result.
Specifically, based on the interrupt program, the operation type of the memory chip, that is, the writing operation or the reading operation, is controlled, the corresponding reading and writing result is obtained, whether the reading and writing result accords with the expected result or not is analyzed in real time, and the detection result judgment is carried out on the memory chip.
In this embodiment, the interrupt signal is associated with the interrupt program, and based on the interrupt program, the read-write operation of the memory chip is controlled and detected to obtain the corresponding read-write result, and whether the read-write result accords with the expected result is analyzed in real time, so that the detection of the memory chip is realized, and not only is the accuracy of the detection result of the memory chip improved, but also the real-time performance of the detection of the memory chip is improved.
In one embodiment, configuring a main program, an interrupt program, and an interrupt signal includes:
Configuring a rising edge or a falling edge of a clock signal as an interrupt signal;
According to the strength of the real-time requirement, the tasks in the testing process of the memory chip are divided, the tasks with high real-time requirement are configured as interrupt programs, and the tasks with low real-time requirement are configured as main programs.
For example, the external interfaces of the memory chip, namely the data path, the address path and the control path have high real-time requirements, so that the memory chip has high real-time requirements on the control of the read-write task, and the read-write task is configured in the interrupt program to obtain the read-write interrupt program; other tasks with low real-time requirements, such as determining whether an interrupt condition is satisfied, i.e., whether an interrupt signal of an interrupt program is triggered, may be configured in the main program.
In this embodiment, according to the real-time requirement, the task with high real-time requirement is configured in the interrupt program, so that the real-time performance of the detection of the memory chip is further improved.
In one embodiment, running the main program and interrupting the main program from running the interrupt program when the interrupt signal occurs comprises the steps of:
running a main program and acquiring an interrupt program identifier when an interrupt signal occurs;
if the interrupt program identifier is a first preset identifier, the interrupt program identifier is adjusted to a second identifier, and the main program is interrupted to run the interrupt program; when the running of the interrupt program is finished, adjusting the interrupt program identification to a first preset identification, and running the main program;
if the interrupt program identifier is the second preset identifier, stopping running the main program and the interrupt program.
The interrupt program identifier is used for marking whether an interrupt program running currently exists or not; the interrupt program identifier comprises a first preset identifier and a second preset identifier; the first preset identifier is used for marking that the current interrupt-free program is running; and the second preset identifier is used for marking that the interrupt program is running currently.
For example, configuring a rising edge of a clock signal as an interrupt signal of an interrupt program, acquiring an interrupt program identifier when the rising edge of the clock signal arrives each time the interrupt signal occurs, and judging whether an interrupt program running currently exists or not based on the interrupt program identifier; if the interrupt program identifier is a first preset identifier, indicating that the current interrupt program is running, firstly configuring the current interrupt program identifier as a second preset identifier, then interrupting the main program, and running the interrupt program corresponding to the interrupt signal; when the running of the interrupt program is finished, the current interrupt program identifier needs to be reconfigured into a first preset identifier, and then the interrupt program is converted back to the main program to run related tasks of the main program. If the interrupt program identifier is a second preset identifier, indicating that the running interrupt program exists currently, and the interrupt program is not completed yet; at this time, if the interrupt reentry occurs, the system will not operate normally, i.e. the main program and the interrupt program are stopped, and the system is reset to enter an initial state and wait for reconfiguration. Wherein, interrupt reentry refers to that when the same interrupt program is not finished in the last operation, an interrupt signal arrives in advance to trigger the next interrupt program to start operation. When the interrupt signal is the falling edge of the clock signal, the interrupt signal is consistent with the implementation process, and will not be described herein.
It should be noted that, the reason why the interrupt program generates interrupt reentry may be that the frequency of the clock signal is too fast, that is, the arrival frequency of the rising edge or the falling edge of the clock signal is too fast, that is, the trigger frequency of the interrupt signal is too fast, which exceeds the frequency range supported by the memory chip; therefore, in the programming stage, the frequency of the clock signal needs to be reasonably adjusted to prevent the interrupt program from being interrupted and reentered due to the excessively fast frequency of the clock signal.
In this embodiment, based on the interrupt program identifier, the running state of the current interrupt program can be obtained in real time, which lays a foundation for improving the stability and accuracy of the detection of the memory chip.
In one embodiment, running the main program and interrupting the main program from running the interrupt program when the interrupt signal occurs includes:
Running a main program, and detecting whether an interrupt program exists currently when an interrupt signal occurs;
if the interrupt program exists, the interrupt main program runs the interrupt program, and the main program is run after the interrupt program runs.
Specifically, when an interrupt signal occurs each time, detecting whether an interrupt program needing to be operated exists currently; if the interrupt program to be operated exists, the operation of the main program is interrupted, the operation is skipped to the corresponding interrupt program, related tasks of the interrupt program are operated, and after the operation of the interrupt program is completed, the main program is returned to again, and related tasks of the main program are operated; if no interrupt program to be operated exists, continuing to operate the main program until the interrupt program to be operated is detected when a certain interrupt signal occurs, interrupting the operation of the main program, jumping to the corresponding interrupt program, and sequentially cycling.
In this embodiment, when the interrupt signal occurs each time, whether the interrupt program to be run exists currently is detected in real time, so that the running state of the main program or the interrupt program can be switched rapidly, and the real-time performance and the efficiency of the detection of the memory chip are improved.
In one embodiment, interrupting the main program to run the interrupt program and running the main program after the interrupt program is run is completed includes:
configuring a plurality of interrupt programs, and setting priority for each interrupt program;
when an interrupt signal occurs, interrupting a main program, and detecting a plurality of interrupt programs;
And acquiring priorities of a plurality of interrupt programs, sequentially operating all interrupt programs according to the current priority from high to low, and operating the main program after the operation of all interrupt programs is finished.
Specifically, when an interrupt signal occurs, the main program is interrupted to run a first interrupt program, and whether a new second interrupt program to be run is currently detected continuously;
if the second interrupt program appears, the priority of the first interrupt program and the priority of the second interrupt program are obtained;
If the priority of the first interrupt program is higher than that of the second interrupt program, continuing to operate the first interrupt program, operating the interrupt program with the highest priority to be operated after the operation of the first interrupt program is finished, and operating the main program after the operation of all interrupt programs is finished;
If the priority of the first interrupt program is lower than that of the second interrupt program, the first interrupt program is interrupted to operate the second interrupt program, the interrupt program with the highest priority to be operated is operated after the operation of the second interrupt program is finished, and the main program is operated after the operation of all interrupt programs is finished.
The interrupt program is provided with priority, and comprises a read-write interrupt program and a communication interrupt program; the read-write interrupt program comprises a read interrupt program and a write interrupt program; and the communication interrupt program is used for responding to the information interaction request. Preferably, the read-write interrupt routine has a higher priority than the communication interrupt routine.
For example, the rising edge of the clock signal is configured as an interrupt signal of the interrupt program, and when the interrupt signal triggers the first interrupt program to start running, the second interrupt program is continuously detected when the clock signal is the rising edge each time the interrupt signal occurs; if the second interrupt program exists, the priority of the first interrupt program and the priority of the second interrupt program are respectively acquired; and determining whether the priority of the first interrupt program is higher than the priority of the second interrupt program. If the priority of the first interrupt program is higher than that of the second interrupt program, continuing to operate the first interrupt program, after the operation of the first interrupt program is finished, firstly operating the interrupt program with the highest priority to be operated, then sequentially operating all other interrupt programs according to the current priority from high to low, and returning to the main program after the operation of all interrupt programs is finished; if the priority of the first interrupt program is lower than that of the second interrupt program, the first interrupt program is interrupted, the second interrupt program is operated, after the operation of the second interrupt program is finished, the interrupt program with the highest priority to be operated is operated again, all other interrupt programs are operated in sequence from high to low according to the current priority, and after the operation of all interrupt programs is finished, the main program is returned. When the corresponding priority of each interrupt program is configured, the priority of each interrupt program needs to be configured from high to low, so as to avoid that two or more interrupt programs have the same priority. When the interrupt signal is the falling edge of the clock signal, the interrupt signal is consistent with the implementation process, and will not be described herein.
By way of example, suppose that the priority of the read-write interrupt routine is higher than the priority of the communication interrupt routine; if the communication interrupt program is triggered in the running process of the read-write interrupt program and no other priority interrupt program is triggered, at this time, the read-write interrupt program is not responded to the priority of the communication interrupt program, and the read-write interrupt program is continuously run until the read-write interrupt program is run, and then the communication interrupt program is run after the running of the read-write interrupt program is finished. If the read-write interrupt program is triggered in the running process of the communication interrupt program and no other priority interrupt program is triggered, the communication interrupt program is immediately interrupted because the priority of the communication interrupt program is lower than that of the read-write interrupt program, the read-write interrupt program is started in response to the read-write interrupt program, and the communication interrupt program is started after the read-write interrupt program is started.
Before running the interrupt program, the interrupt program identifier needs to be detected when the interrupt signal occurs, that is, whether the interrupt program identifier is a first preset identifier or a second preset identifier is detected; if the interrupt program identifier is a first preset identifier, the fact that the same interrupt program is not running is indicated, at the moment, the interrupt program identifier is firstly configured to be a second preset identifier, and then the interrupt program is run based on the priority corresponding to the interrupt program; if the interrupt program identifier is a second preset identifier, the interrupt program identifier indicates that the same interrupt program is running, and the interrupt program is not completed yet; at this time, if an interrupt reentry occurs, i.e., the same interrupt program is triggered again when the last interrupt operation is not completed, the system will reset to the initial state, waiting for reconfiguration. It should be noted that, in this embodiment, the interrupt program identifier is used to detect whether the interrupt program is interrupted and reentered to cause system exception.
In this embodiment, based on a plurality of interrupt programs and the corresponding priorities of the interrupt programs, the corresponding interrupt program can be responded quickly, so that the detection of the memory chip can be completed efficiently, and a foundation is laid for improving the efficiency and instantaneity of the detection of the memory chip.
In one embodiment, obtaining a read-write result fed back by the memory chip based on the interrupt program, and determining a detection result of the memory chip based on the read-write result includes:
Setting a detection strategy, wherein the detection strategy is used for determining data to be stored of an address in a memory chip;
running a read-write interrupt program, and writing data into the memory chip according to a detection strategy;
Running a read-write interrupt program, reading data of a memory chip, and feeding back a read-write result;
And judging the detection result of the memory chip according to the detection strategy and the read-write result.
The detection strategy at least comprises a SCAN0 strategy, a SCAN1 strategy, a CKB strategy and a random strategy, and is used for determining the type of data to be stored in the address in the memory chip.
Specifically, based on a read-write interrupt program and a detection strategy, writing data into a storage unit corresponding to a preset address of a storage chip by using the write interrupt program, wherein the preset address is an address corresponding to the written data; acquiring data of a storage unit corresponding to a preset address of a storage chip by using a read interrupt program, and feeding back a read-write result; based on the difference, the detection result of the memory chip is obtained by comparing the difference of the read-write result, namely the difference of the read result and the write result. If the read result is the same as the write result, the read-write performance of the memory chip is consistent with the expected result; if the read result is different from the write result, the read-write performance of the memory chip is not in accordance with the expected result, namely, the read-write performance of the memory chip is abnormal, and the abnormal detection result is stored. The difference between the read result and the write result includes that the read data is different from the write data, that the address corresponding to the read data is different from the address corresponding to the write data, or that the address corresponding to the read data and the read data is different from the addresses corresponding to the write data and the write data, respectively.
In the embodiment, based on the read-write result, the detection result of the memory chip can be obtained efficiently and accurately, and the accuracy and reliability of the detection of the memory chip are improved.
In one embodiment, a communication interrupt routine is configured; the priority of the communication interrupt program is lower than that of the read-write interrupt program;
When the communication interrupt program is operated, the internal module of the memory chip performs information interaction, or the memory chip performs information interaction with an external terminal.
And the communication interrupt program is used for responding to the information interaction request. The external terminal at least comprises a main control computer and a storage device; wherein the storage device may be, but is not limited to, a database and a memory; the main control machine is used for sending a query request and a control request to the testing machine, wherein the query request at least comprises a request for querying the abnormal detection result of the memory chip; the control request comprises at least a request to adjust the detection strategy; and the storage device is used for storing the abnormality detection result. It should be noted that, the communication mode between the testing machine and the main control machine may be, but not limited to, a short-distance communication mode, such as an I 2 C communication mode, an SPI communication mode, and a UART communication mode; the communication mode between the main control computer and the storage device can be, but not limited to, a long-distance communication mode and a wireless communication mode.
By way of example, a communication interrupt program is run to realize information interaction between the memory chip and the external terminal; because the priority of the communication interrupt program is lower than that of the read-write interrupt program, when the external terminal sends out a request for inquiring the abnormal detection result of the memory chip, whether the running read-write interrupt program exists at present or not needs to be judged; if no running read-write interrupt program exists at present and no other interrupt programs to be run exist, triggering a communication interrupt program, running the communication interrupt program, and realizing information interaction between the memory chip and an external terminal; if the running read-write interrupt program exists currently, but no other interrupt program to be run exists, the communication interrupt program is responded after the running of the current read-write interrupt program is waited, and the information interaction between the memory chip and the external terminal is realized. When the communication interrupt program is operated to realize the information interaction of the internal modules of the memory chip, the working principle of the response communication interrupt program is consistent with that of the response communication interrupt program, and the description is omitted here.
In the embodiment, the communication interrupt program can timely and rapidly respond to the information interaction request, so that the timeliness and the efficiency of detection of the memory chip are improved.
In one embodiment, a detection policy transmitted by an external terminal is obtained, and a read-write interrupt program is configured based on the detection policy.
The detection strategy at least comprises a SCAN0 strategy, a SCAN1 strategy, a CKB strategy and a random strategy. The SCAN0 strategy comprises the following steps: step 1, initializing a memory chip address variable i, and enabling the address variable i to be 0; step 2, writing data 0 into a storage unit corresponding to the address variable i of the storage chip; step 3, reading data in the storage unit corresponding to the address variable i; step 4, the address variable i of the memory chip is automatically increased to be an address variable i+1, and the step 2 is executed until the address variable i of the memory chip is equal to 1000; based on the data, judging whether the data read in the step 3 is 0 all the time, if so, indicating that the read-write result of the memory chip accords with the expected result; otherwise, the expected result is not met. Similarly, compared with the SCAN0 strategy, the SCAN1 strategy writes 1 data into the storage unit corresponding to the storage chip address variable i; judging whether the read data is always 1, if so, indicating that the read-write result of the memory chip accords with the expected result; otherwise, the expected result is not met. Compared with the SCAN0 strategy, the CKB strategy writes data into a storage unit corresponding to the address variable i of the storage chip, the data is related to the value of the address variable i, and if the value of the address variable i is an odd number, the written data is 0; if the value of the address variable i is even, the written data is 1; based on the same address variable i, judging whether the read data is always equal to the written data, if so, indicating that the read-write result of the memory chip meets the expected result; otherwise, the expected result is not met. Compared with the SCAN0 strategy, the random strategy is completely random in the data written into the storage unit corresponding to the storage chip address variable i; based on the same address variable i, judging whether the read data is always equal to the written data, if so, indicating that the read-write result of the memory chip meets the expected result; otherwise, the expected result is not met.
Specifically, a detection strategy control instruction is sent to the testing machine, the testing machine is controlled to adjust the detection strategy, and a read-write interrupt program related to the detection strategy is configured to realize detection of the memory chip.
In this embodiment, based on the detection policy, detection of multiple read-write performances can be achieved, the detection range of the memory chip is enlarged, and the applicability of the detection of the memory chip is improved.
In a specific embodiment, the working frequency range of the memory chip is 1MHz-2MHz, and if the clock signal can be generated inside the memory chip, the frequency range of the generated clock signal is 1MHz-2MHz; if the clock signal cannot be generated inside the memory chip, the test machine is required to provide the clock signal for the memory chip, and the frequency range of the clock signal provided by the test machine is required to be 1MHz-2MHz.
In one embodiment, as shown in fig. 2, fig. 2 is a timing diagram of the operation of the memory chip in one embodiment. The clock signal is denoted as clk, the address is denoted as a, the write data is denoted as d, the read data is denoted as q, the control signal is denoted as we, and the chip select signal is denoted as cs. If the chip selection signal cs is at a high level, the memory chip is selected to start working; if the chip select signal cs is at a low level, the memory chip is not selected and does not operate. On the premise that the chip select signal cs is at a high level, if the control signal we is at a high level, the memory chip performs a write operation; if the control signal we is low, the memory chip performs a read operation. Note that the memory chip is active for the rising edge of the clock signal clk, and therefore, all signals must remain stable before and after the rising edge of the clock signal clk.
Note that, the read/write timing of the memory chip is not completely equivalent, and for example, for a write operation, the address a and the write data d are valid at the same time, that is, when the rising edge of the clock signal clk arrives, the data d is written into the memory cell corresponding to the address a. For a read operation, the read data q is one clock cycle later than the address a, for example, when the rising edge of the 6 th clock cycle arrives, the data q starts to be read from the memory cell corresponding to the address a, and the read data q is valid before the rising edge of the 7 th clock cycle and remains stable before and after the rising edge of the 7 th clock cycle.
In a specific embodiment, for different detection strategies, the address a, the write data d, the control signal we and the chip selection signal cs of the memory chip need to be adjusted accordingly according to the content of the detection strategy. To ensure that each write operation or read operation to the memory chip can be matched with the detection policy, the control tasks associated with the memory chip, address a, write data d, control signal we, and chip select signal cs need to be placed in the interrupt service with the highest priority. Illustratively, taking the CKB strategy as an example, the strategy write operation and read operation are performed at intervals, so that the control signal we needs to be reconfigured each time the interrupt signal enters the interrupt program; in addition, the CKB policy changes the address of each write data and each read data, and the content of the write data changes accordingly with the parity of the address, so that it is necessary to reconfigure the address a and the write data d.
According to the storage chip detection method, in the first aspect, the main program, the interrupt program and the priority of the interrupt program are configured, so that a foundation is laid for improving the real-time performance and the accuracy of storage chip detection; in the second aspect, the interrupt signal is associated with the interrupt program, so that the accurate and rapid control of the interrupt program is realized, and the real-time performance and the efficiency of detection of the memory chip are improved; in the third aspect, based on the detection strategy and the read-write result, not only the applicability of the detection of the memory chip is improved, but also the accuracy of the detection result of the memory chip is improved.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the same inventive concept, the embodiment of the application also provides a memory chip detection device for realizing the above related memory chip detection method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation of the embodiment of the device for detecting a memory chip provided in the following may be referred to the limitation of the method for detecting a memory chip, which is not described herein.
In one embodiment, as shown in fig. 3, fig. 3 is a block diagram of a memory chip detection device in one embodiment. A memory chip detection apparatus comprising: configuration module 301, association module 302, program execution module 303, and detection module 304, wherein:
a configuration module 301, configured to configure a main program, an interrupt program, and an interrupt signal; the interrupt program comprises a read-write interrupt program;
an association module 302, configured to associate an interrupt signal with an interrupt program;
a program running module 303, configured to run a main program, and interrupt the main program to run an interrupt program when an interrupt signal occurs;
The detection module 304 is configured to obtain a read-write result fed back by the memory chip based on the interrupt program, and determine a detection result of the memory chip based on the read-write result.
In one embodiment, configuration module 301 is also used to
Configuring a rising edge or a falling edge of a clock signal as an interrupt signal;
According to the strength of the real-time requirement, the tasks in the testing process of the memory chip are divided, the tasks with high real-time requirement are configured as interrupt programs, and the tasks with low real-time requirement are configured as main programs.
In one embodiment, program execution module 303 is also used to
Running a main program and acquiring an interrupt program identifier when an interrupt signal occurs;
if the interrupt program identifier is a first preset identifier, the interrupt program identifier is adjusted to a second identifier, and the main program is interrupted to run the interrupt program; when the running of the interrupt program is finished, adjusting the interrupt program identification to a first preset identification, and running the main program;
if the interrupt program identifier is the second preset identifier, stopping running the main program and the interrupt program.
In one embodiment, program execution module 303 is also used to
Running a main program, and detecting whether an interrupt program exists currently when an interrupt signal occurs;
if the interrupt program exists, the interrupt main program runs the interrupt program, and the main program is run after the interrupt program runs.
In one embodiment, program execution module 303 is also used to
Configuring a plurality of interrupt programs, and setting priority for each interrupt program;
when an interrupt signal occurs, interrupting a main program, and detecting a plurality of interrupt programs;
And acquiring priorities of a plurality of interrupt programs, sequentially operating all interrupt programs according to the current priority from high to low, and operating the main program after the operation of all interrupt programs is finished.
In one embodiment, program execution module 303 is also used to
When an interrupt signal occurs, the main program is interrupted to run a first interrupt program, and whether a new second interrupt program to be run is currently detected continuously;
if the second interrupt program appears, the priority of the first interrupt program and the priority of the second interrupt program are obtained;
If the priority of the first interrupt program is higher than that of the second interrupt program, continuing to operate the first interrupt program, operating the interrupt program with the highest priority to be operated after the operation of the first interrupt program is finished, and operating the main program after the operation of all interrupt programs is finished;
If the priority of the first interrupt program is lower than that of the second interrupt program, the first interrupt program is interrupted to operate the second interrupt program, the interrupt program with the highest priority to be operated is operated after the operation of the second interrupt program is finished, and the main program is operated after the operation of all interrupt programs is finished.
In one embodiment, the detection module 304 is also used to
Setting a detection strategy, wherein the detection strategy is used for determining data to be stored of an address in a memory chip;
running a read-write interrupt program, and writing data into the memory chip according to a detection strategy;
Running a read-write interrupt program, reading data of a memory chip, and feeding back a read-write result;
And judging the detection result of the memory chip according to the detection strategy and the read-write result.
In one embodiment, program execution module 303 is also used to
Configuring a communication interrupt program; the priority of the communication interrupt program is lower than that of the read-write interrupt program;
When the communication interrupt program is operated, the internal module of the memory chip performs information interaction, or the memory chip performs information interaction with an external terminal.
In one embodiment, configuration module 301 is also used to
And acquiring a detection strategy transmitted by the external terminal, and configuring a read-write interrupt program based on the detection strategy.
The above-described respective modules in the memory chip detection apparatus may be implemented in whole or in part by software, hardware, or a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a computer device is provided, which may be a terminal, and an internal structure diagram thereof may be as shown in fig. 4, and fig. 4 is an internal structure diagram of the computer device in one embodiment. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a memory chip detection method.
It will be appreciated by persons skilled in the art that the architecture shown in fig. 4 is merely a block diagram of some of the architecture relevant to the present inventive arrangements and is not limiting as to the computer device to which the present inventive arrangements are applicable, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In an embodiment, there is also provided a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the method embodiments described above when the computer program is executed.
The user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or sufficiently authorized by each party.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magneto-resistive random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (PHASE CHANGE Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in various forms such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (11)
1. A method for detecting a memory chip, the method comprising:
configuring a main program, an interrupt program and an interrupt signal; the interrupt program comprises a read-write interrupt program;
Associating the interrupt signal with the interrupt program;
running the main program, and interrupting the main program to run an interrupt program when the interrupt signal occurs;
and acquiring a read-write result fed back by the memory chip based on the interrupt program, and judging the detection result of the memory chip based on the read-write result.
2. The method of claim 1, wherein configuring the main program, the interrupt program, and the interrupt signal comprises:
Configuring a rising edge or a falling edge of a clock signal as an interrupt signal;
dividing tasks in the testing process of the memory chip according to the intensity of real-time requirements, configuring tasks with high real-time requirements as interrupt programs, and configuring tasks with low real-time requirements as main programs.
3. The method of claim 1, wherein the running the main program and interrupting the main program from running an interrupt program when the interrupt signal occurs comprises:
running the main program and acquiring an interrupt program identifier when the interrupt signal occurs;
if the interrupt program identifier is a first preset identifier, the interrupt program identifier is adjusted to a second identifier, and the main program is interrupted to run the interrupt program; when the running of the interrupt program is finished, the interrupt program identification is adjusted to be a first preset identification, and a main program is run;
and if the interrupt program identifier is a second preset identifier, stopping running the main program and the interrupt program.
4. The method of claim 1, wherein the running the main program and interrupting the main program from running an interrupt program when the interrupt signal occurs comprises:
running the main program, and detecting whether an interrupt program exists currently when the interrupt signal occurs;
If the interrupt program exists, the interrupt main program runs the interrupt program, and the main program is run after the interrupt program runs.
5. The method of claim 4, wherein the interrupting the main program to run the interrupt program and running the main program after the interrupt program is run is finished comprises:
configuring a plurality of interrupt programs, and setting priority for each interrupt program;
when the interrupt signal occurs, interrupting the main program, and detecting a plurality of interrupt programs;
And acquiring the priorities of the interrupt programs, sequentially operating all the interrupt programs according to the current priority from high to low, and operating the main program after the operation of all the interrupt programs is finished.
6. The method of claim 5, wherein the interrupting the main program to run the interrupt program and running the main program after the interrupt program is run is finished comprises:
when the interrupt signal occurs, the main program is interrupted to run the first interrupt program, and whether a new second interrupt program to be run is present or not is continuously detected;
if the second interrupt program appears, the priority of the first interrupt program and the priority of the second interrupt program are obtained;
If the priority of the first interrupt program is higher than that of the second interrupt program, continuing to operate the first interrupt program, operating the interrupt program with the highest priority to be operated after the operation of the first interrupt program is finished, and operating the main program after the operation of all interrupt programs is finished;
If the priority of the first interrupt program is lower than that of the second interrupt program, the first interrupt program is interrupted to operate the second interrupt program, the interrupt program with the highest priority to be operated is operated after the operation of the second interrupt program is finished, and the main program is operated after the operation of all interrupt programs is finished.
7. The method according to claim 1, wherein the obtaining the read-write result fed back by the memory chip based on the interrupt program, and performing the detection result determination on the memory chip based on the read-write result, includes:
setting a detection strategy, wherein the detection strategy is used for determining data to be stored of an address in the memory chip;
running the read-write interrupt program, and writing data into the memory chip according to the detection strategy;
Running the read-write interrupt program, reading the data of the memory chip, and feeding back a read-write result;
And judging the detection result of the storage chip according to the detection strategy and the read-write result.
8. The method of claim 5, wherein the method further comprises:
configuring a communication interrupt program; the priority of the communication interrupt program is lower than that of the read-write interrupt program;
And when the communication interrupt program is operated, the internal module of the storage chip performs information interaction, or the storage chip performs information interaction with an external terminal.
9. The method according to claim 1, wherein the method further comprises:
and acquiring a detection strategy transmitted by the external terminal, and configuring a read-write interrupt program based on the detection strategy.
10. A memory chip testing device, the device comprising:
The configuration module is used for configuring the main program, the interrupt program and the interrupt signal; the interrupt program comprises a read-write interrupt program;
the association module is used for associating the interrupt signal with the interrupt program;
the program running module is used for running the main program and interrupting the main program to run an interrupt program when the interrupt signal occurs;
and the detection module is used for acquiring a read-write result fed back by the memory chip based on the interrupt program and judging the detection result of the memory chip based on the read-write result.
11. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the method of any one of claims 1 to 9 when executing the computer program.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN120236643A (en) * | 2025-05-29 | 2025-07-01 | 杭州广立微电子股份有限公司 | Memory chip and semiconductor test system |
| CN120236642A (en) * | 2025-05-29 | 2025-07-01 | 杭州广立微电子股份有限公司 | Chip read/write capability testing device, method, readable storage medium and system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN120236643A (en) * | 2025-05-29 | 2025-07-01 | 杭州广立微电子股份有限公司 | Memory chip and semiconductor test system |
| CN120236642A (en) * | 2025-05-29 | 2025-07-01 | 杭州广立微电子股份有限公司 | Chip read/write capability testing device, method, readable storage medium and system |
| CN120236642B (en) * | 2025-05-29 | 2025-11-18 | 杭州广立微电子股份有限公司 | Chip read-write capability test device, method, readable storage medium and system |
| CN120236643B (en) * | 2025-05-29 | 2025-11-25 | 杭州广立微电子股份有限公司 | Memory chip and semiconductor test system |
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