CN1179008A

CN1179008A - Semiconductor device, method for producing said semiconductor and sputtering device

Info

Publication number: CN1179008A
Application number: CN 97119260
Authority: CN
Inventors: 星真一
Original assignee: Oki Electric Industry Co Ltd
Current assignee: Oki Electric Industry Co Ltd
Priority date: 1996-10-09
Filing date: 1997-09-25
Publication date: 1998-04-15

Abstract

A method of fabricating a semiconductor device comprises the steps of: (a) forming a mask layer over an upper surface of a semiconductor substrate such that the mask layer has an aperture penetrating the mask layer and having an inclined lateral wall so as to make the aperture inverted taper shaped; (b) forming a first dielectric layer at a first area over the upper surface of the semiconductor substrate within the aperture by sputtering at a first sputtering incidence direction; and (c) forming a first electrode layer at a second area over the upper surface of the semiconductor substrate within the aperture by sputtering at a second sputtering incidence direction which is different from the first sputtering incidence direction.

Description

Semiconductor device, the method for making this semiconductor device and sputter equipment

The present invention relates to a kind of have such as on GaAs substrate one based semiconductor substrate and its be formed with the semiconductor device of electric capacity, a kind of sputter equipment of making the method for this device and being applicable to this manufacture method.

Conventional capacitor well known in the prior art comprises that for example dielectric material is clipped in two MIM (metal-insulator-metal type) capacitors between the metal electrode and the Schottky capacitor that utilizes Schottky barrier electric capacity.

The capacitor C of MIM capacitor can be represented with following formula:

C＝ε ₀ε _r(S/d)

ε wherein ₀The dielectric constant of expression vacuum, ε _rThe dielectric constant of expression dielectric material, S represents the surface area of capacitor, d then represents distance between electrodes.

Make the capacitor of big electric capacity, can use high-k ε _rDielectric material, can reduce distance between electrodes d, perhaps can increase the surface area S of capacitor.Yet, owing to use the dielectric material of high-k to be limited on some material, and that can dwindle between the electrode also is restricted apart from d, and therefore, the method for selection normally increases the surface area S of capacitor.

Yet the surface area of attempting the increase capacitor will cause the increase of chip surface area, and this will directly cause the higher cost of chip.

The object of the present invention is to provide a kind of little and semiconductor device of the capacitor that electric capacity is big of surface area that has, a kind of method of making a kind of like this semiconductor device efficiently is provided, and a kind of sputter equipment that is applicable to this manufacture method is provided.

According to an aspect of the present invention, the method for making semiconductor device comprises the following step: (a) form mask layer on the upper surface of Semiconductor substrate, in order to do the hole that mask layer is had run through mask layer and be sloped sidewall, so that make the hole form inverted taper; (b), form first dielectric layer in the first area on the upper surface of interior Semiconductor substrate in the hole with the first sputter incident direction sputter; (c) with the second sputter incident direction sputter different, form first electrode layer in second area with the upper surface of interior Semiconductor substrate in the hole with the first sputter incident direction.

This method also can comprise the following step: (f) with the 3rd sputter incident direction sputter, form second dielectric layer in the 3rd zone in the hole on the upper surface of interior Semiconductor substrate; (g) flash with different with the 3rd sputter incident direction the and inject the direction sputter, form the third electrode layer in the 4th zone on the upper surface of interior Semiconductor substrate in the hole.

In addition, in the method, step (b), (c), (f) and (g) can be repeated with this order by desirable number of times.

According to a further aspect in the invention, provide a kind of semiconductor device, wherein capacitor is formed on the compound semiconductor substrate, and this capacitor comprises: first electrode layer; Be formed on the dielectric layer on first electrode layer; And be formed on the second electrode lay on the dielectric layer.

In accordance with a further aspect of the present invention, sputter equipment comprises: sputtering chamber; Place the wafer station of megacryst garden sheet on it; With and go up to place the target platform of sputter material.Wafer station and target platform are installed in the sputtering chamber.Wafer station comprises: be fixed to the fixed station in the sputtering chamber; With the clamping crystal and make it on fixed station, freely to rotate, thus make the sputter incident direction by the packaged type wafer holder of uncommon direction.

According to a further aspect of the invention, sputter equipment comprises: sputtering chamber; Place the wafer station of megacryst garden sheet on it; With a plurality of target platforms of placing sputter material on it respectively.Wafer station and target platform are installed in the sputtering chamber, and the target platform is arranged on the mutually different position of sputter incident direction with respect to megacryst garden sheet upper surface.By between one of wafer station and target platform, applying high frequency voltage, the sputter material that is placed on one of target platform is deposited on the sheet of megacryst garden, thereby sputter material is deposited on the upper surface of megacryst garden sheet.

Can more fully understand the present invention from the following detailed description and accompanying drawing, these accompanying drawings only are used to illustrate, and do not limit the present invention, wherein:

Figure 1A is the circuit diagram according to the semiconductor device of first embodiment of the invention;

Figure 1B partly illustrates the upper surface of the semiconductor device of Figure 1A;

Fig. 1 C is the cutaway view of being got along A-A ' line among Figure 1B;

Fig. 2 is the structure chart of sputter equipment used in the capacitor technology formed according to the present invention;

Fig. 3 A is the enlarged drawing of the upper surface of wafer station in Fig. 2 sputter equipment;

Fig. 3 B is vertical cutaway view Amplified image of wafer station in Fig. 2 sputter equipment;

Fig. 4 A and 4B describe the schematic diagram that how is limited the sputter incident direction by sputter incidence angle θ and sputter angle of orientation φ;

Fig. 5 is the structure chart of used another kind of sputter equipment in the capacitor technology formed according to the present invention;

Fig. 6 A-6E illustrates respectively according to the upper surface in each step of first embodiment capacitor formation technology;

Fig. 6 F-6J is respectively the cutaway view that takes off along A-A ' line shown in Fig. 6 A-6E;

Fig. 7 A is the circuit diagram according to the semiconductor device of second embodiment of the invention;

Fig. 7 B partly illustrates the upper surface of Fig. 7 A semiconductor device;

Fig. 7 C is the cutaway view of being got along A-A ' line among Fig. 7 B;

Fig. 8 A-8C illustrates respectively according to the upper surface in each step of second embodiment capacitor formation technology;

Fig. 8 D-8F is the cutaway view of being got along the A-A ' line of Fig. 8 A-8C.

Now describe with reference to the accompanying drawings preferred embodiment of the present invention,

First embodiment

Figure 1A is the circuit diagram according to the semiconductor device of first embodiment of the invention, and Figure 1B partly illustrates the upper surface of the semiconductor device of Figure 1A, and Fig. 1 C is the cutaway view of being got along A-A ' line among Figure 1B.

This semiconductor device comprises GaAs substrate 10.

Circuit shown in Figure 1A comprises N raceway groove MES transistor npn npn Tr1 and Tr2, capacitor C1 and C2 and resistor R.Capacitor C1 is as the capacitor of DC component between the grid 8b of drain electrode 6a that cuts off transistor Tr 1 and transistor Tr 2.Capacitor C2 also is provided, and it and the source electrode of transistor Tr 1 and the biasing resistor R between the earthing power supply E1 are in parallel, and are used as by-pass capacitor.

Referring to Figure 1B and 1C, transistor Tr 1 and Tr2 and capacitor C1 and C3 are formed on the GaAs substrate 10.Should be appreciated that resistor R also is formed on the GaAs substrate 10, but its figure does not illustrate in Figure 1B and Fig. 1 C.Capacitor C1 is a MIM capacitor, and the cambium layer stack structure forms between the first electrode 1a and the second electrode 2a by medium 3a is clipped in.Capacitor C2 also is a MIM capacitor, and the cambium layer stack structure forms between the first electrode 1b and the second electrode 2b by medium 3b is clipped in.

Form the contact hole 5a be connected on capacitor C1 first electrode on the intermediate interlayer dielectric film 4, be connected to contact hole 5b on capacitor C1 second electrode, be connected to contact hole 5c on the capacitor C2 first electrode 1b, be connected to contact hole 5d on the capacitor C2 second electrode 2b, be connected to contact hole 5e on the transistor Tr 1 drain electrode 6a, be connected to the contact hole 5f on the transistor Tr 1 source electrode 7a, and be connected to the contact hole 5g on the transistor Tr 2 grid 8b.The first electrode 1a of capacitor C1 and the drain electrode 6a of transistor Tr 1 are connected by metal wire 9a with 5e by contact hole 5a.The second electrode 2a of capacitor C1 is connected by metal wire 9b with 5g by contact hole 5b with the grid 8b of transistor Tr 2.The first electrode 1b of capacitor C2 is connected by metal wire 9c with 5f by contact hole 5c with the source electrode 7a of transistor Tr 1.Second of capacitor C2 connects 2b and is connected to the earthing power supply (not shown) by metal wire 9d.The cross-section structure of C2 is identical with capacitor C1's shown in Fig. 1 C.

Below, the sputter equipment that is used to form this class capacitor technology is described.

Fig. 2 illustrates the structure chart that forms the used sputter equipment of this class capacitor.

In this sputter equipment, sputter can be carried out (hereinafter being referred to as " inclination sputter ", to be different from " the vertical sputter " of common incidence angle perpendicular to sheet surface, megacryst garden) to the direction on sheet surface, megacryst garden with variable, oblique incidence.Sputter equipment 33 shown in Figure 2 comprises target 32, megacryst garden sheet gate 33 and is positioned at the wafer station 34 of cavity 31.Target 32 comprises target platform 32a, is placed with sputter material 32b on it.

Fig. 3 A is the enlarged drawing of wafer station 34 upper surfaces in Fig. 2 sputter equipment, and Fig. 3 B then is the enlarged drawing that the wafer platform is analysed and observe in Fig. 2 sputter equipment.Referring to Fig. 3 A and 3B, wafer station 34 comprise on its upper surface form hemispherical dimples 34d and be fixed to fixed station 34a on the cavity 31, the packaged type wafer holder 34b with hemispherical projections and the setting that coincide with the pit 34d of fixed station 34a and be fixed to that packaged type wafer holder 34b is flat a lip-deep wafer retainer ring 34c.Megacryst garden sheet 30 is fixed on the flat surface of packaged type wafer holder 34b by wafer retainer ring 34c.Packaged type wafer holder 34b is fixed on the fixed station 34a by steady pin 35, is to be desirable direction in order to do making the sputter incident direction with respect to megacryst garden sheet 30 upper surfaces.

Fig. 4 A and 4B are the end view and the plane graphs of megacryst garden sheet 30, are used to describe the sputter incident direction D2 with respect to megacryst garden sheet surface 30a.In Fig. 4 A and 4B, sputter incident direction D2 is defined by sputter incidence angle θ and sputter angle of orientation φ, wherein sputter incidence angle θ represents the normal D1 and the angle between the sputter incident direction D2 perpendicular to megacryst garden sheet surface 30a, and sputter angle of orientation φ then represents from the center of megacryst garden sheet 30 to the direction D3 (being called the OF direction) that is orientated plane OF and the ray cast D2 direction through being parallel to normal D to the angle (promptly being rotated counterclockwise the angle of formation from the OF direction) the upper surface gained direction D2 '.In sputter equipment shown in Figure 2, sputter incidence angle θ can spend to 90 degree from 0 and change, and sputter angle of orientation φ then can spend to 360 degree from 0 and change.

In the sputter equipment shown in Fig. 2 and Fig. 3 A and the 3B, sputter material 32b is placed on the target platform 32a, sheet 30 usefulness wafer retainer ring 34c in megacryst garden are placed in the packaged type wafer holder 34b, and packaged type clamper 34b then utilizes steady pin 35 to be fixed with predetermined angle.So in predetermined vacuum (for example 10 ^-1Hold in the palm 10 holders), provide Ar gas with predetermined flow velocity (for example 1 second centimetre to 30 seconds centimetres) to cavity 31, and between target platform 32a and packaged type wafer holder 34b, apply under the RF voltage of 13.56MHz, by inclination sputter or vertical sputter, sputter material 32b is deposited on the upper surface 30a of megacryst garden sheet 30.

Fig. 5 is the schematic diagram that is used to form the another kind survey injection device of this class capacitor.This is a kind of survey injection device that can change the sputter incident direction, so that allow the sputter of tilting.Sputter equipment shown in Figure 5 has three

targets

41,42 and 43, megacryst garden sheet gate 33 and is positioned at the wafer platform 44 of cavity 31.

Three

targets

41,42 and 43 comprise

target platform

41a, 42a and 43a and

target lock

41b, 42b and 43b respectively.Megacryst garden sheet 30 is fixed on the surface of wafer station 44 by the wafer retainer ring 44a that is arranged in the wafer station 44.Three

target platform

41a, 42a and 43a are arranged on such position, in order to do the value that makes sputter incidence angle θ and sputter angle of orientation φ have nothing in common with each other each other (referring to Fig. 4).For example target platform 41a is arranged on the position of θ=0 degree, and target platform 42a is arranged on θ=10 degree-30 degree, and on the position of φ=90 degree, target platform 43a then is arranged on θ=10 degree-30 degree, and on the position of φ=270 degree.

In the sputter equipment of Fig. 5, sputter material 41c is placed on the target platform 41a, sputter material 42c is placed on the target platform 42a, and sputter material 43c is placed on the target platform 43a, and megacryst garden sheet 30 then is placed on the wafer station 44.When for example using target 41, open target lock 41b and megacryst garden sheet gate 33, sputter material 41c is just in predetermined vacuum (for example 10 ^-1Hold in the palm 10 holders), provide Ar gas with predetermined flow velocity to cavity, and between the terminal 41d of target platform 41a and wafer station 44, apply under the RF voltage to frequency of 13.56MHz, by the upper surface of vertical sputtering deposit to megacryst garden sheet 30.

Target platform

42a and 43a positive charge to avoid, for example attract ion from sputter material, and

gate

42b and 43b then close, thereby cause the sputter material 41c of target 41 not adhere to sputter material 42c and 43c.When using target 42, target lock 42b and megacryst garden sheet gate 33 are opened,

target platform

41a and 43a positive charge,

gate

41b and 43b close, between the terminal 42d of target platform 42a and wafer station 44, apply RF voltage, and sputter makes by the surface of sputter material 42c inclination megacryst garden sheet 30 is carried out.If desired, Fig. 2 or sputter equipment shown in Figure 5 can also be to comprise a plurality of multi-cavity builds for cavity shown in Figure 2.

Fig. 6 A-6J makes the schematic diagram of capacitor with technology according to first embodiment, and wherein Fig. 6 A-6E illustrates upper surface respectively, and Fig. 6 F-6J illustrates the cutaway view of being got along A-A ' line among Fig. 6 A-6E respectively.Form in the technology at the capacitor shown in Fig. 6 A-6J, mask layer 13 (being resist figure 13) is formed on the GaAs substrate (being GaAs megacryst garden sheet 30), on this substrate 10, is formed with first metal electrode layer 11 and the following metal electrode layer 12.Form mask layer 13 with photoresist, its pattern edge is the shape of being inverted awl.Form first dielectric layer 14, second metal electrode layer 15, second dielectric layer 16 and the 3rd metal electrode layer 17 from different sputter incident directions.The OF that supposes megacryst garden sheet 30 is in the bottom of Fig. 6 A-6E, and under the situation of Fig. 6 F-6J, then above paper.

In Fig. 6 A and Fig. 6 F, on the upper surface of GaAs substrate 10, form first metal electrode layer 11 and the following metal electrode layer 12 that is electrically insulated from each other.For example, form metal film in the whole surface of GaAs substrate 10 by sputter or similar technology, then metal level is carried out photoetching composition (being etching) or on the surface of the GaAs substrate 10 that is formed with the photoresist figure, form the metal tunic, dissolve the resist figure then and form first metal electrode layer 11 and the following metal electrode layer 12 to remove it.Here used GaAs substrate 10 can be 3 inches low-doped megacryst garden sheets, for example has doping content, is 10 ¹⁴[cm ^-3], perhaps plain 3 inches megacryst garden sheets.

Then, the photoresist (not shown) of utilizing pattern edge to have inverted-cone shape is carried out photoetching composition, forms resist figure 13, as mask layer, has hole 13a on it.Hole 13a contains the zone that forms first metal electrode 11 and forms the zone of metal electrode layer 12 down.Preferably the bevel angle at mask layer 13 edges is the angle of 10 degree-40 degree facing to the upper surface (being sheet surface, megacryst garden) of substrate 10.The photoresist that forms resist figure 13 can be for example negative type photoresist (for example, brand is: FSMR).

Then, be formed with the deielectric-coating 14 that forms predetermined thickness (for example 9000-15000) on the surface of resist resist figure as the substrate 10 of mask layer 13 by vertical sputter (sputter incidence angle θ=1 degree).In Fig. 6 F, use arrow I ₁Indication sputter incident direction.Resist figure 13 is as mask, and to form this first deielectric-coating 14, latter cover part first metal electrode layer 11 and part be metal electrode layer 12 down.

Above-mentioned deielectric-coating 14 can be for example to resemble silicon nitride (SiN), tantalum oxide (Ta ₂O ₅), the ferroelectric film of BST (amorphous film that constitutes by barium, strontium, titanium and oxygen) or STO (amorphous film that constitutes by strontium, a titanium and oxygen) class.Also be formed with deielectric-coating 14a on the surface of resist figure 13.

Then, in Fig. 6 B and Fig. 6 G, spend to the inclination sputter formation metal level 15 of 30 degree and φ=90 degree by sputter angle θ=10.In Fig. 6 G, the sputter incident direction is by arrow I ₂Indication.This second metal electrode layer 15 is formed in the 13a of hole as mask with resist figure 13.The very big part surface of second metal electrode layer 15 and first dielectric layer 14 (except that layer 14 part of contiguous first metal electrode layer 11) and the part exposed surface overlaid of time metal electrode layer 12, but not with the exposed surface overlaid of first metal electrode layer 11.Therefore, second metal electrode layer 15 contacts with following metal electrode layer 12, but with 11 electric insulations of first metal electrode layer.

The first metal layer 11, following metal electrode layer 12 and second metal electrode layer 15 can be formed by for example titanium (Ti) and platinum (Pt) (" Ti/Pt " metal hereinafter referred to as) double layer of metal.The thickness of Ti layer is 500, and formation thickness is 1000 Pt layer on the Ti layer.Pt also plays the effect of plate condenser electrode, and prevents to mix with the deielectric-coating crystal when directly forming deielectric-coating thereon by sputter.When forming above-mentioned Ti/Pt metal, can utilize as Fig. 2 or the sputter equipment with multi-cavity specification shown in Figure 5 and carry out sputter.It should be noted that metal electrode layer 15a, be formed on equally on the surface of dielectric layer 14a.

Then, in Fig. 6 C and Fig. 6 H, form second dielectric layer 16 by vertical sputter.In Fig. 6 H, sputter incident direction arrow I ₃Indication.This second dielectric layer 16 is formed in the 13a of hole.The exposed surface overlaid of the very big part surface of second dielectric layer 16 and second metal level 15 (except that layer 15 part of contiguous lower electrode layer 12) and first dielectric layer 14.The dielectric material of supposing this second dielectric layer 16 is identical with first dielectric layer 14, and has identical film thickness.Should be noted that dielectric layer 16a equally also is formed on the surface of metal level 15a.

Then, by the inclination sputter formation metal electrode layer 17 of sputter angle θ=10 degree to 30 degree and φ=270 degree.In Fig. 6, sputter incident direction arrow I ₄Indication.The 3rd metal electrode layer 17 is formed in the 13a of hole.The exposed surface overlaid of the very big part surface of the 3rd metal electrode layer 17 and second dielectric layer 16 and first metal electrode layer 11, but not with the exposed surface overlaid of the following metal electrode layer 12 and second metal electrode layer.Therefore, the 3rd metal level 17 contacts with first metal electrode layer 11, but with 12 electric insulations of following metal electrode layer.Suppose that the 3rd metal electrode layer 17 is identical with the metal of second metal electrode 15, and have identical thickness.Should be noted that metal electrode layer 17a equally also is formed on the surface of dielectric layer 16a.

Then, in Fig. 6 D and Fig. 6 I, peel off resist figure 13 by dissolving.So remove resist figure 13 lip-

deep metal level

15a and 17a and

dielectric layer

14a and 16a together, and retain the capacitor that has first metal electrode layer 11, descends the stepped construction of metal electrode layer 12, first dielectric layer 14, second metal electrode layer 15, second dielectric layer 16 and the 3rd metal electrode layer 17.When this capacitor is used as the capacitor C1 of Fig. 1, first metal electrode layer 11 and the 3rd metal electrode layer 17 form the first electrode 1a, the following metal electrode layer 12 and second metal electrode layer 15 form the second electrode 2a, and first dielectric layer 14 and second dielectric layer 16 then form medium 3a.

Then, in Fig. 6 E and Fig. 6 J, on whole surface, form wall dielectric film 18 by plasma CVD or similar approach.Wall dielectric film 18 can be, for example silicon nitride (SiN) film.In this wall dielectric film 18, form the contact hole 19a that is connected to first metal electrode layer 11 and be connected to the contact hole 19b of metal electrode layer 12 down, and connect connecting line by these contact holes 19a and 19b.When this capacitor was used as the capacitor C1 of Fig. 1, contact hole 19a was corresponding to contact hole 5a, and contact hole 19b is corresponding to contact hole 5b.

Therefore,, have the stepped construction of the 3rd metal electrode layer and second dielectric layer, increased the effective surface area S of capacitor by making capacitor according to first embodiment.Specifically, capacitor effective surface area S increases by 2 times nearly with respect to the figure used area.Thereby for the identical capacitor in figure used area, its electric capacity has also increased nearly 2 times.

In addition, in capacitor forms technology, utilize resist figure 13 as mask and change the sputter incidence angle and form each layer, just first dielectric layer 14, second metal electrode layer 15, second dielectric layer 16 and the 3rd metal electrode layer 17 are formed successively by sputter like this.Therefore, needn't be as using engraving method, carry out sputter, photoetching composition, corrosion quarter and resist and remove all steps and form each layer, thereby, make work simplification, and can make capacitor effectively.

Have again,, can easily carry out oblique sputter with any desired sputter incident angle lapping by utilizing Fig. 2 or sputter equipment shown in Figure 5.

In above-mentioned first embodiment, described capacitor situation, yet it is two-layer to should be appreciated that the number of plies is not limited to 2 layers.When making the n layer capacitor, the effective surface area of capacitor can improve about n doubly with respect to the figure used area, and therefore, the electric capacity of this capacitor is n times of the electric capacity under the regular situation.

And, by be communicated with the metal electrode that is formed on all contact holes in the wall dielectric film with metal wire, capacitor is connected to external circuit (transistor Tr 1 among Fig. 1, Tr2), yet, first metal electrode layer 11 and following metal electrode layer 12 also can be connected to external circuit, in this case, can omit the wiring step that forms behind the wall dielectric film.

Can also form conduction region by certain applications ion implantation or the growth technology that requires to form first metal electrode layer 11 and following metal electrode layer 12 on the surface of GaAs Semiconductor substrate 10, this conduction region is used as first metal electrode layer and lower electrode layer.

Second embodiment

Fig. 7 A is the semiconductor device circuit figure of second embodiment of the invention, and Fig. 7 B partly illustrates the upper surface of the semiconductor device of Fig. 7 A, and Fig. 7 C then is the cutaway view of being got along the A-A ' line of Fig. 7 B.

This semiconductor device by using GaAs substrate 60.In addition, Fig. 7 A is identical with Figure 1A.

In Fig. 7 B and 7C, transistor Tr 1, Tr2 and capacitor C1, C2 all form on GaAs substrate 60.Resistor R also is formed on the GaAs substrate 60, but among the figure its figure is not shown.Capacitor C1 is the MIM capacitor that forms between the first electrode 51a and the second electrode 52a by medium 53a is clipped in.Capacitor C2 is the MIM capacitor that forms between the first electrode 51b and the second electrode 52b by medium 53b is clipped in.

The first electrode 51a of capacitor C1 is connected on the drain electrode 6a of transistor Tr 1, and the second electrode 52a of capacitor C1 is connected on the grid 8b of transistor Tr 2.The first electrode 51b of capacitor C2 is connected on the source electrode 7a of transistor Tr 1, and the second electrode 52b of capacitor C2 is connected on the earthing power supply E1 (not shown).The cross-section structure of capacitor C2 is identical with capacitor C1's shown in Fig. 7 C.

In capacitor C1, apply earthing potential to the first electrode 51a, apply negative potential to the second electrode 52a, make transistor Tr ₁The edge gate effects disappear, and avoid the deterioration of transistor output.

Below, with the making of describing according to the capacitor of second embodiment.In this manufacture craft, as first embodiment, use sputter equipment as the Fig. 2 or the sputter of tilting shown in Figure 5.

Fig. 8 A-8F illustrates the schematic diagram of making capacitor technology according to second embodiment, and wherein Fig. 8 A-8C illustrates the upper surface of figure, and Fig. 8-8F then illustrates the A-A ' section that line is got along Fig. 8 A-8C respectively.In the capacitor fabrication technology that Fig. 8 describes, utilize pattern edge to have and be inverted the photoresist formation mask layer 63 (being resist figure 63) of boring.Utilize different sputter angles to stack first dielectric layer, second metal electrode layer, second dielectric layer, the 3rd metal electrode layer and the 3rd dielectric layer on GaAs substrate 60 (GaAs wafer) upper strata that is formed with first metal electrode layer that is connected to the 1 drain electrode 6a of transistor Tr among Fig. 7 A.After removing the resist figure, be connected to the 4th metal electrode layer of Fig. 7 transistor Tr 2 grid 8a on stacked.Suppose that the OF of wafer is positioned at the bottom of Fig. 8 A-8C, and be in the top of Fig. 8 D-8F with paper.

In Fig. 8 A and Fig. 8 D, go up formation first metal electrode layer 61 at GaAs substrate 60 (GaAs megacryst garden sheet) by sputter, photoetching composition and corrosion step or photoetching composition, sputter and strip step.So form this first metal electrode layer 61, it is connected on the drain electrode 6a of transistor Tr 1 of (being covered in) Fig. 7 A.GaAs substrate 60 can be, for example be basically the same as those in the first embodiment.

Then, carry out photoetching composition by the photoresist that utilizes pattern edge to have back taper and form resist figure 63 (mask layer) with hole 63a.This hole 63a partly comprises first metal electrode 61.Preferably the bevel angle at resist figure 63 edges is that 10 degree are to 40 degree with respect to sheet surface, megacryst garden.Above-mentioned photoresist can be for example with first embodiment in use the same.

Then, (sputter incidence angle θ=0 degree) forms the deielectric-coating (for example 9000-15000) of predetermined thickness on the substrate surface that is formed with resist figure 63 by vertical sputter, thereby forms first dielectric layer 64 that is covered in first metal electrode layer 61 in the 63a of hole.This dielectric layer can be, for example with first embodiment in use the same.

Then, spend to 30 degree scopes 10 by sputter incidence angle θ, sputter angle of orientation φ is that the inclination sputters of 90 degree form metal levels, thereby forms second metal electrode layer 65 in the 63a of hole.The very big part surface of this second metal electrode layer 65 and first dielectric layer 64 directly overlapping (removing the part of the layer 64 of contiguous first metal electrode layer 61), but not with the exposed surface overlaid of first metal electrode layer 61.Therefore, second metal electrode layer 65 and first metal electrode layer, 61 electric insulations.

First metal electrode layer 61 and second metal electrode layer 65 can be that for example first embodiment is such, are formed by the Ti/Pt metal.The Ti film that forms and the thickness of Pt film are respectively 500 and 1000.

Then, form deielectric-coating, thereby in the 63a of hole, form second dielectric layer 66 by vertical sputter.The exposed surface overlaid of the most surfaces of this second dielectric layer 66 and second metal level 65 and first dielectric layer 64.

Then, spend to 30 degree scopes 10 by sputter incidence angle θ, sputter angle of orientation φ is that the inclination sputters of 270 degree form metal levels.The 3rd metal electrode layer 67 is formed in the 63a of hole.The exposed surface overlaid of the very big part surface of the 3rd metal electrode layer 67 and second dielectric layer 66 and first metal electrode layer 61, but not with the exposed surface overlaid of second metal electrode layer.Also form deielectric-coating, thereby in the 63a of hole, form the 3rd dielectric layer 68 by vertical sputter.

Then, in Fig. 8 B and Fig. 8 E, peel off resist figure 63, form another resist figure 69 with hole 69a by dissolving.This resist figure 69 is used to form the 4th metal electrode layer 70 (describing below), and the 4th metal electrode layer 70 is connected with the grid 8b of transistor Tr 2.Therefore hole 69a contains the zone that arrives transistor Tr 2 grid 8b.Hole 69a also comprises the exposed surface area of second metal electrode layer 65, but does not comprise the exposed surface area of first metal electrode layer 61 and the 3rd metal electrode layer 67.

Then, form metal level, so that in the 69a of hole, form the 4th metal electrode layer 70 by vertical sputter or vapour deposition.The very big part of the exposed surface of the 4th metal electrode 70 and the 3rd dielectric layer 68 and the exposed surface of second metal electrode layer 67 are overlapping, but not with the exposed surface overlaid of first metal electrode layer 61 and the 3rd metal electrode layer.The 4th metal electrode layer 70 also with the exposed surface overlaid (being connected) of transistor Tr 2 grid 8b.

Then, in Fig. 8 C and Fig. 8 F, peel off resist figure 69 by dissolving.Like this, just formed capacitor with the stepped construction that includes first metal electrode 61, first dielectric layer 64, second metal electrode layer 65, second dielectric layer 66, the 3rd metal electrode layer 67, the 3rd dielectric layer 68 and the 4th metal electrode 70.When this capacitor was used as capacitor C1, the odd number metal electrode layer constituted the first electrode 51a, and the even number metal electrode layer constitutes the second metal electrode 52a, and first-Di, three dielectric layers then constitute dielectric layer 53a.

Therefore, according to second embodiment, have the stepped construction of the 4th metal electrode layer and the 3rd dielectric layer by making capacitor, the effective surface area S of capacitor is increased.Specifically, capacitor effective surface area S can increase by 3 times effectively with respect to the figure used area of capacitor.Therefore for identical figure used area, the electric capacity of capacitor can increase by 3 times nearly.

In addition, utilize resist figure 63 as mask by forming in the technology at capacitor, change the sputter incidence angle and form each layer, just form first dielectric layer 64, second metal electrode layer 65, second dielectric layer 66 and the 3rd metal electrode layer 67 successively by sputter like this.Therefore, needn't carry out sputter, photoetching composition, corrode and remove resist as using engraving method, forming each layer, thereby, technology is simplified.

And, by arranging, make first metal electrode 61 and the 4th metal electrode 70 be connected to external circuit (transistor Tr 1, Tr2 in Fig. 7), can omit the wiring step behind the formation wall dielectric film.

In capacitor C1, by earthing potential being applied to the first electrode 51a, negative potential is applied to the second electrode 52a, make transistor Tr ₁The edge gate effects disappear, and avoid the deterioration of transistor output.

In above-mentioned second embodiment, the lamination number of capacitor is 3, yet, should be appreciated that the lamination number is not limited to 3.

In addition, as first embodiment, can after forming, the wall dielectric film carry out with being connected also of external circuit.

Can also form conduction region by certain applications ion implantation or the growth technology that requires to form first metal electrode layer 61 on the surface of GaAs Semiconductor substrate 60, this conduction region is used as first metal electrode layer.

Claims

1, a kind of method of making semiconductor device comprises the following step:

(a) on the upper surface of Semiconductor substrate, form mask layer, in order to do the hole that described mask layer is had run through described mask layer and be sloped sidewall, so that make described hole have back taper;

(b) pass through with the first sputter incident direction sputter, the first area on the described upper surface of the described Semiconductor substrate in described hole forms first dielectric layer; And

(c) pass through with the second sputter incident direction sputter different with the described first sputter incident direction, the second area on the described upper surface of the described Semiconductor substrate in described hole forms first electrode layer.

2, the method for claim 1 is characterized in that, also is included in described step (a) forms metal electrode layer before on the described upper surface of described Semiconductor substrate step (d).

3, method as claimed in claim 2 is characterized in that, described step (d) utilizes etching to carry out.

4, the method for claim 1 is characterized in that, also is included in described step (a) forms conduction region before in the described upper surface of described Semiconductor substrate step (e).

5, method as claimed in claim 4 is characterized in that, described step (e) utilizes ion implantation to carry out.

6, method as claimed in claim 4 is characterized in that, described step (e) utilizes epitaxial growth method to carry out.

7, the method for claim 1 is characterized in that, also comprises the following step:

(f) pass through with the 3rd sputter incident direction sputter, the zone of the 3rd on the described upper surface of the described Semiconductor substrate in described hole forms second dielectric layer; With

(g) inject the direction sputter by flashing with different with described first to the 3rd sputter incident direction the, the zone of the 4th on the described upper surface of the described Semiconductor substrate in described hole forms the third electrode layer.

8, method as claimed in claim 7 is characterized in that, described step (b), (c), (f) and (g) repeated with desirable number of times in this order.

9, method as claimed in claim 7 is characterized in that, the described first and the 3rd sputter incident direction is perpendicular to the described upper surface of described Semiconductor substrate.

10, method as claimed in claim 7, it is characterized in that, the described second sputter incident direction and perpendicular to the incidence angle between the normal of the described upper surface of described Semiconductor substrate at 10 degree to the scopes of 30 degree, described the flashes inject incidence angle between direction and the described normal at 10 degree to the scopes of 30 degree, to inject direction opposite each other with respect to described normal and the described second sputter incident direction and described the flashes.

11, a kind of semiconductor device that on compound semiconductor substrate, forms capacitor, described capacitor comprises:

First electrode layer;

Be formed on the dielectric layer on described first electrode layer; With

Be formed on second dielectric layer on the described dielectric layer.

12, semiconductor device as claimed in claim 11 is characterized in that, described first electrode layer, described dielectric layer and described the second electrode lay and described dielectric layer are positioned at over each other with this in proper order.

13, semiconductor device as claimed in claim 10 is characterized in that, described capacitor has the effect of eliminating DC component.

14, semiconductor device as claimed in claim 10 is characterized in that, also comprises the first transistor and transistor seconds, and each transistor is formed on the described Semiconductor substrate;

Wherein, an end of described electrode layer is electrically connected on the described the first transistor, and an end of described the second electrode lay then is electrically connected on the described transistor seconds.

15, semiconductor device as claimed in claim 14 is characterized in that, a described end of described first electrode layer is electrically connected on the source electrode of described the first transistor, and a described end of described the second electrode lay then is electrically connected to the grid of described transistor seconds.

16, semiconductor device as claimed in claim 15 is characterized in that, earthing potential is put on described first electrode layer, and negative potential is put on the described the second electrode lay.

17, semiconductor device as claimed in claim 10 is characterized in that,

Described compound semiconductor is the GaAs substrate; And

Described dielectric layer is then selected from silicon nitride film, tantalum-oxide film, BST and STO group.

18, semiconductor device as claimed in claim 10 is characterized in that, described electrode layer is the lamination that includes titanium layer and platinum layer.

19, a kind of sputter equipment comprises:

Sputtering chamber;

Place the wafer station of megacryst garden sheet on it; And

Place the target platform of sputter material on it;

Described wafer station and described target platform are installed in the described sputtering chamber;

Wherein, described wafer station comprises:

Be fixed to the fixed station on the described sputtering chamber; With

The described megacryst of clamping garden sheet also makes it to rotate freely on described fixed station, thereby makes the packaged type wafer holder of sputter incident direction by institute's required direction.

20 sputter equipments as claimed in claim 19 is characterized in that described fixed station is included in the hemispherical dimples on its upper surface;

Described packaged type wafer holder has the hemispherical projections of coincideing with described pit.

21, a kind of sputter equipment comprises:

Sputtering chamber;

Place the wafer station of megacryst garden sheet on it; With

A plurality of target platforms of sputter material are set respectively on it;

Described wafer station and described target platform are installed in the described sputtering chamber; Described target platform is arranged on the mutually different position of sputter incident direction with respect to described megacryst garden sheet upper surface;

Wherein, be placed on sputter material on one of described target platform by between one of described wafer station and described target platform, being applied with high frequency voltage, and be deposited on the sheet of described megacryst garden, thereby described sputter material is deposited on the described upper surface of described megacryst garden sheet.

22, a kind of multi-cavity type sputter equipment comprises the described sputtering chamber of a plurality of claims 19.

23, a kind of multi-cavity type sputter equipment comprises the described sputtering chamber of a plurality of claims 21.