CN117872903A - A slope control circuit and control method based on LIN bus signal control - Google Patents

Abstract

The invention relates to a slope control circuit and a slope control method based on LIN bus signal control, and belongs to the technical field of LIN bus signal control. The slope control circuit based on LIN bus signal control comprises a voltage acquisition circuit, a feedback control circuit and a load circuit; the load circuit is connected with the input end of the voltage acquisition circuit through an LIN pin; the output end of the voltage acquisition circuit is connected with the input end of the feedback control circuit, the output end of the feedback control circuit is connected with the LIN pin, and the voltage acquisition circuit comprises a sample hold circuit S/H; according to the invention, through the sampling and holding circuit S/H and the cooperation of the voltage acquisition capacitor, the voltage change of the voltage on the LIN bus in the acquisition period can be taken out, and accurate response can be made based on the LIN signal change outside the LIN chip; the closed-loop feedback control circuit is used, so that the rising edge and the falling edge of the LIN bus voltage can be kept constant; in addition, the circuit of the invention is simple and has low cost.

Description

A slope control circuit and control method based on LIN bus signal control

Technical Field

The invention belongs to the technical field of LIN bus signal control, and in particular relates to a slope control circuit based on LIN bus signal control and a control method thereof.

Background technique

LIN (Local Interconnect Network) bus is a low-cost serial communication protocol based on UART/SCI (Universal Asynchronous Receiver-Transmitter/Serial Communication Interface). Compared with CAN bus, LIN bus protocol is relatively simple, and the requirements for single-chip microcomputer are not high, and basic windows can be implemented. As an auxiliary bus of CAN bus, LIN bus is widely used in the field of body control such as doors, windows, lights and central locking.

Usually, a LIN chip is mounted on the LIN bus to monitor changes in LIN bus signals. The LIN pin port of the LIN chip draws current from the LIN bus to generate changes in the LIN bus voltage.

Currently, most LIN bus voltage control circuits on the market are designed based on the principle of open-loop control, which is essentially an estimated control and cannot accurately respond to the NMOS tube gate voltage based on the changes in the LIN signal outside the LIN chip, resulting in unstable rates of the voltage rise and fall of the LIN bus.

Summary of the invention

The object of the present invention is to provide a slope control circuit and method based on LIN bus signal control, which can accurately respond to changes in LIN signals outside the LIN chip and keep the rates of the rising and falling edges of the LIN bus voltage constant.

To achieve the above-mentioned purpose, the present invention provides a slope control circuit based on LIN bus signal control, comprising a voltage acquisition circuit, a feedback control circuit, and a load circuit. The load circuit is connected to the input end of the voltage acquisition circuit through a LIN pin. The voltage acquisition circuit is used to acquire the voltage when the LIN bus voltage drops or rises. The output end of the voltage acquisition circuit is connected to the input end of the feedback control circuit, and the output end of the feedback control circuit is connected to the LIN pin. The feedback control circuit is used to control the LIN bus voltage to maintain a constant rate when it drops or rises.

As a further solution of the present invention: when the LIN bus voltage drops, the voltage acquisition circuit includes a sampling and holding circuit S/HI, a sampling and holding circuit S/HII, a voltage follower VFI, and a voltage follower VFII; the positive input end of the voltage follower VFI is connected to one end of the sampling and holding circuit S/HI, and the other end of the sampling and holding circuit S/HI is connected to the LIN pin; the sampling and holding circuit S/HI is connected in parallel with the sampling and holding circuit S/HII, and the output end of the sampling and holding circuit S/HII is connected to the positive input end of the voltage follower VFII; the output end of the voltage follower VFI is connected to one end of the switch _S1 ; the output end of the voltage follower VFII is connected to one end of the switch _S2 ; the other end of the switch _S1 is respectively connected to the upper plate of the voltage acquisition capacitor _C1 and one end of the switch _S4 ; the lower plate of the voltage acquisition capacitor _C1 is respectively connected to one end of the switch _S3 and the other end of the switch _S2 , and the other end of the switch _S3 is grounded; the other end of the switch _S4 is connected to the positive input end of the operational amplifier OPAI in the feedback control circuit;

The feedback control circuit includes an operational amplifier OPAI, a negative input terminal of the operational amplifier OPAI is connected to a reference voltage Ref_voltageI, an output terminal of the operational amplifier OPAI is connected to a variable current source _I1 , an output terminal of the variable current source _I1 is respectively connected to an upper plate of a capacitor _C2 and an output terminal of a micro-current source _I2 , a lower plate of the capacitor _C2 is grounded, an output terminal of the micro-current source _I2 is respectively connected to an upper plate of a capacitor _C3 and a gate of an NMOS tube MI through a resistor _R1 , a lower plate of the capacitor _C3 is grounded, and a source of the NMOS tube MI is grounded.

As a further solution of the present invention: the gate voltage of the NMOS tube MI is GND, and the LIN bus voltage is the highest.

As a further solution of the present invention: the variable current source I ₁ and the micro current source I ₂ are very small current sources, which ensure that the voltage on the capacitor C ₃ is constantly rising.

As a further solution of the present invention: when the LIN bus voltage rises, the voltage acquisition circuit includes a sampling and holding circuit S/HIII, a sampling and holding circuit S/HIV, a voltage follower VFIII, and a voltage follower VFIV; the positive input end of the voltage follower VFIII is connected to one end of the sampling and holding circuit S/HIII, and the other end of the sampling and holding circuit S/HIII is connected to the LIN pin; the sampling and holding circuit S/HIII is connected in parallel with the sampling and holding circuit S/HIV, and the output end of the sampling and holding circuit S/HIV is connected to the positive input end of the voltage follower VFIV; the output end of the voltage follower VFIII is connected to one end of the switch _S5 ; the output end of the voltage follower VFIV is connected to one end of the switch _S6 ; the other end of the switch _S5 is respectively connected to the upper plate of the voltage acquisition capacitor _C4 and one end of the switch _S7 ; the lower plate of the voltage acquisition capacitor _C4 is respectively connected to one end of the switch _S8 and the other end of the switch _S6 , and the other end of the switch _S8 is grounded; the other end of the switch _S7 is connected to the positive input end of the operational amplifier OPAII in the feedback control circuit;

The feedback control circuit includes an operational amplifier OPAII, the output end of the operational amplifier OPAII is connected to a variable current source _I3 , the variable current source _I3 is connected in parallel with a micro-current source _I4 and a capacitor _C5 , and then connected in series with a resistor _R2 , the other end of the resistor _R2 is connected to the ground through a capacitor _C6 , and is connected to the gate of the NMOS tube MII, the source of the NMOS tube MII is grounded, and the drain of the NMOS tube MII is connected between the LIN pin and the voltage collection circuit; the lower plate of the capacitor _C5 is grounded.

As a further solution of the present invention: the gate voltage of the NMOS tube MII is VDD, and the LIN bus voltage is the lowest.

As a further solution of the present invention: the variable current source I ₃ and the micro current source I ₄ are very small current sources, which ensure that the voltage on the capacitor C ₆ is always pulled down.

As a further solution of the present invention: the load circuit comprises a load resistor R _load , the load resistor R _load and the load capacitor C _load are connected in series and then grounded, and the LIN pin is connected between the load resistor R _load and the load capacitor C _load .

A slope control method based on LIN bus signal control comprises the following steps:

Step 1: The voltage collection circuit controls the voltage collection capacitor by closing and closing different switches to collect the voltage on the upper plate and the lower plate respectively, thereby obtaining the voltage difference of the LIN bus voltage;

Step 2: The feedback control circuit compares the voltage difference with the reference voltage, and controls the pull-down current capability of the NMOS tube according to the comparison result;

Step 3: Repeat Step 1 and Step 2 multiple times. The beat is determined by the internal clock of the chip. The number of acquisitions depends on the clock frequency of the LIN chip. If the clock frequency is high, more acquisitions can be achieved.

Compared with the prior art, the present invention has the following beneficial effects: the present invention can obtain the voltage change on the LIN bus within the acquisition period through the sampling and holding circuit S/H and in conjunction with the voltage acquisition capacitor, and can make an accurate response based on the LIN signal change outside the LIN chip. If the acquisition period is short, it can be approximately considered that the LIN bus voltage is differentially operated; the use of a closed-loop feedback control circuit can keep the rates of the rising and falling edges of the LIN bus voltage constant; in addition, the circuit of the present invention is simple and low in cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a slope control circuit based on LIN bus signal control according to the present invention.

FIG. 2 is a circuit diagram of the present invention when the LIN bus voltage drops.

FIG3 is a circuit diagram of the present invention when the LIN bus voltage rises.

FIG. 4 is a flow chart of a slope control method based on LIN bus signal control according to the present invention.

In the figure: 1. Voltage acquisition circuit, 2. Load circuit, 3. Feedback control circuit.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

As shown in FIG1 , a slope control circuit based on LIN bus signal control includes a voltage acquisition circuit 1, a feedback control circuit 2, and a load circuit 3. The load circuit 2 is connected to the voltage acquisition circuit 1 through a LIN pin. The voltage acquisition circuit 1 is used to acquire the voltage when the LIN bus voltage drops or rises. The output end of the voltage acquisition circuit 1 is connected to the input end of the feedback control circuit 2, and the output end of the feedback control circuit 2 is connected to the LIN pin. The feedback control circuit 2 is used to control the LIN bus voltage to maintain a constant rate when it drops or rises.

As shown in Figure 2, the circuit diagram when the LIN bus voltage drops, the default premise is that the last time the LIN bus voltage was pulled to the highest, the gate voltage of the NMOS tube MI was correspondingly pulled to the lowest, that is, GND. On this basis, if the LIN bus voltage drops, the gate voltage of the NMOS tube MI needs to be gradually increased.

The voltage acquisition circuit 1 includes a sampling and holding circuit S/HI, a sampling and holding circuit S/HII, a voltage follower VFI, and a voltage follower VFII; the positive input end of the voltage follower VFI is connected to one end of the sampling and holding circuit S/HI, and the other end of the sampling and holding circuit S/HI is connected to the LIN pin; the sampling and holding circuit S/HI is connected in parallel with the sampling and holding circuit S/HII, and the output end of the sampling and holding circuit S/HII is connected to the positive input end of the voltage follower VFII; the output end of the voltage follower VFI is connected to one end of the switch _S1 ; the output end of the voltage follower VFII is connected to one end of the switch _S2 ; the other end of the switch _S1 is respectively connected to the upper plate of the voltage acquisition capacitor _C1 and one end of the switch _S4 ; the lower plate of the voltage acquisition capacitor _C1 is respectively connected to one end of the switch _S3 and the other end of the switch _S2 , and the other end of the switch _S3 is grounded; the other end of the switch _S4 is connected to the positive input end of the operational amplifier OPAI in the feedback control circuit;

The feedback control circuit 3 includes an operational amplifier OPAI, a negative input terminal of the operational amplifier OPAI is connected to a reference voltage Ref_voltageI, an output terminal of the operational amplifier OPAI is connected to a variable current source _I1 , an output terminal of the variable current source _I1 is respectively connected to an upper plate of a capacitor _C2 and an output terminal of a micro-current source _I2 , a lower plate of the capacitor _C2 is grounded, an output terminal of the micro-current source _I2 is respectively connected to an upper plate of a capacitor _C3 and a gate of an NMOS tube MI through a resistor _R1 , a lower plate of the capacitor _C3 is grounded, and a source of the NMOS tube MI is grounded.

The control method when the LIN bus voltage drops includes the following steps:

The digital logic controls the closing and opening of the switch S ₁ , the switch S ₂ , the switch S ₃ , and the switch S ₄ .

Step 1: Switches S ₁ and S ₃ are closed, switches S ₂ and S ₄ are opened, and the upper plate of the voltage collection capacitor C ₁ collects the LIN bus voltage U ₁ ;

Step 2: Switches S ₁ and S ₂ are closed, switches S ₃ and S ₄ are opened, and the lower plate of the voltage collection capacitor C ₁ collects the LIN bus voltage U ₂ ;

Step 3: Switches S ₁ and S ₂ are opened, and switches S ₃ and S ₄ are closed. The upper plate of the voltage acquisition capacitor C ₁ is the LIN bus voltage difference ΔU ₁ acquired twice, where ΔU ₁ =U ₁ -U ₂ , and the voltage difference ΔU ₁ is read in.

Step 4: The voltage difference _ΔU1 is compared with the reference voltage Ref_voltageI. If it is higher than the reference voltage Ref_voltageI, the charging current of the variable current source _I1 is reduced; if it is lower than the reference voltage Ref_voltageI, the current of the variable current source _I1 is increased, thereby controlling the pull-down current capability of the NMOS tube MI pull-down tube.

Through such feedback control, a constant rate of voltage drop of the LIN bus is achieved.

During the process of LIN bus voltage dropping, this process will be repeated many times. The beat is given by the internal clock of the chip, and the number of acquisitions depends on the clock frequency of the LIN chip. If the clock frequency is high, more acquisitions can be achieved.

The variable current source I ₁ and the micro current source I ₂ in FIG. 2 are very small current sources, which ensure that the voltage on the capacitor C ₃ keeps rising.

As shown in FIG3 , the circuit diagram when the LIN bus voltage rises, the default condition is that the gate voltage of the NMOS tube MII is VDD, VDD is the highest voltage in the chip, and the LIN bus voltage is the lowest.

The voltage acquisition circuit 1 includes a sampling and holding circuit S/HIII, a sampling and holding circuit S/HIV, a voltage follower VFIII, and a voltage follower VFIV; the positive input end of the voltage follower VFIII is connected to one end of the sampling and holding circuit S/HIII, and the other end of the sampling and holding circuit S/HIII is connected to the LIN pin; the sampling and holding circuit S/HIII is connected in parallel with the sampling and holding circuit S/HIV, and the output end of the sampling and holding circuit S/HIV is connected to the positive input end of the voltage follower VFIV; the output end of the voltage follower VFIII is connected to one end of the switch _S5 ; the output end of the voltage follower VFIV is connected to one end of the switch _S6 ; the other end of the switch _S5 is respectively connected to the upper plate of the voltage acquisition capacitor _C4 and one end of the switch _S7 ; the lower plate of the voltage acquisition capacitor _C4 is respectively connected to one end of the switch _S8 and the other end of the switch _S6 , and the other end of the switch _S8 is grounded; the other end of the switch _S7 is connected to the positive input end of the operational amplifier OPAII in the feedback control circuit 3;

The feedback control circuit 3 includes an operational amplifier OPAII, the output end of the operational amplifier OPAII is connected to a variable current source _I3 , the variable current source _I3 is connected in parallel with a micro current source _I4 and a capacitor _C5 , and then connected in series with a resistor _R2 , the other end of the resistor _R2 is connected to the ground through a capacitor _C6 , and the other end is connected to the gate of the NMOS tube MII, the source of the NMOS tube MII is grounded, and the drain of the NMOS tube MII is connected between the LIN pin and the voltage collection circuit; the lower plate of the capacitor _C5 is grounded;

The load circuit 2 is located outside the LIN chip, as shown in FIG. 2 or FIG. 3 , and includes a load resistor R _load , which is connected in series with _{a load capacitor C load and} then grounded. The LIN pin is connected between the load resistor R _load and the load capacitor C _load .

When the LIN bus voltage rises, the default condition is that the gate of the NMOS tube MII is to VDD, and VDD is the highest voltage in the chip. The control method includes the following steps:

Digital logic controls the closing and opening of switches S ₅ , S ₆ , S ₇ , and S ₈ .

Step 1: Switch S ₆ is closed, switches S ₅ , S ₇ , and S ₈ are opened, and the lower plate of the voltage collection capacitor C ₄ collects the LIN bus voltage u ₁ ;

Step 2: Switches S ₅ and S ₆ are closed, switches S ₇ and S ₈ are opened, and the upper plate of the voltage collection capacitor C ₄ collects the LIN bus voltage u ₂ ;

Step 3: Switches S ₇ and S ₈ are closed, switches S ₅ and S ₆ are opened, and the upper plate _of the voltage collection capacitor C ₄ is the LIN line voltage difference Δu ₁ collected twice, that is, Δu ₁ =u ₁ -u ₂ . The voltage difference Δu ₁ is read in and compared with the reference voltage Ref_voltageII. If it exceeds the reference voltage, the pull-down current of the variable current source is reduced; if it is lower than the reference voltage, the current of the variable current source I ₃ is increased, thereby controlling the pull-down current capability of the NMOS tube MII pull-down tube.

Through such feedback control, a constant rate of rise of the LIN bus line voltage is achieved.

During the rising process of LIN bus voltage, this process will be repeated many times. The beat is given by the internal clock of the chip. The number of acquisitions depends on the clock frequency of the LIN chip. If the clock frequency is high, more acquisitions can be achieved.

The variable current source I ₃ and the micro current source I ₄ are very small current sources, which ensure that the voltage on the capacitor C ₆ is always pulled down.

The present invention uses a sampling and holding circuit S/H and cooperates with a voltage acquisition capacitor to obtain the voltage change on the LIN bus within a collection period, and can make an accurate response based on the LIN signal change outside the LIN chip. If the collection period is short, it can be approximately considered that a differential operation is performed on the LIN bus voltage; a closed-loop feedback control circuit is used to keep the rates of the rising and falling edges of the LIN bus voltage constant; in addition, the circuit of the present invention is simple and low in cost.

Claims (9)

1. The slope control circuit based on LIN bus signal control is characterized by comprising a voltage acquisition circuit (1), a feedback control circuit (3) and a load circuit (2); the load circuit (2) is connected with the input end of the voltage acquisition circuit (1) through an LIN pin, and the voltage acquisition circuit (1) is used for acquiring the voltage when the LIN bus voltage drops or the LIN bus voltage rises; the output end of the voltage acquisition circuit (1) is connected with the input end of the feedback control circuit (3), the output end of the feedback control circuit (3) is connected with the LIN pin, and the feedback control circuit (3) is used for controlling the LIN bus voltage to drop or rise and keeping constant speed.

2. Slope control circuit based on LIN bus signal control according to claim 1, characterized in that the voltage acquisition circuit (1) comprises a sample-and-hold circuit S/HI, a sample-and-hold circuit S/HII, a voltage follower VFI, a voltage follower VFII when the LIN bus voltage drops; the positive input end of the voltage follower VFI is connected with one end of the sampling and holding circuit S/HI, and the other end of the sampling and holding circuit S/HI is connected with the LIN pin; the sampling hold circuit S/HI is connected in parallel with the sampling hold circuit S/HII, and the output end of the sampling hold circuit S/HII is connected with the voltage follower VFIIThe positive input end is connected; output end of voltage follower VFI and switch S ₁ Is connected with one end of the connecting rod; output end of voltage follower VFII and switch S ₂ Is connected with one end of the connecting rod; switch S ₁ The other end of (C) is respectively connected with the voltage acquisition capacitor C ₁ Upper pole plate of (S) switch (S) ₄ Is connected with one end of the connecting rod; voltage acquisition capacitor C ₁ The lower polar plate of (C) is respectively connected with a switch S ₃ One end of switch S ₂ Is connected to the other end of switch S ₃ The other end of the first electrode is grounded; switch S ₄ The other end of the feedback control circuit (3) is connected with the positive input end of the operational amplifier OPAI;

the feedback control circuit (3) comprises an operational amplifier OPAI, the negative input end of the operational amplifier OPAI is connected with a reference voltage Ref_voltage I, the output end of the operational amplifier OPAI and a variable current source I ₁ Connected to a variable current source I ₁ Respectively with the capacitor C ₂ Upper plate of (C), micro current source I ₂ Is connected with the output end of the capacitor C ₂ The lower polar plate of (2) is grounded, and the micro current source I ₂ Through resistor R ₁ Respectively with the capacitor C ₃ The upper polar plate of the NMOS tube MI is connected with the grid electrode of the NMOS tube MI, and the capacitor C ₃ The lower electrode plate of the NMOS tube MI is grounded, and the source electrode of the NMOS tube MI is grounded.

3. The slope control circuit according to claim 1 or 2, wherein the gate voltage of the NMOS MI is GND and the LIN bus voltage is highest.

4. Slope control circuit based on LIN bus signal control according to claim 1 or 2, characterized in that the variable current source I ₁ Micro current source I ₂ Is a very small current source, ensures the capacitance C ₃ The upper voltage is always rising.

5. Slope control circuit based on LIN bus signal control according to claim 1, characterized in that the voltage acquisition circuit (1) comprises a sample-and-hold circuit S/HIII, a sample-and-hold circuit S/HIV when the LIN bus voltage risesA voltage follower VFIII, a voltage follower VFIV; the positive input end of the voltage follower VFIII is connected with one end of the sampling and holding circuit S/HIII, and the other end of the sampling and holding circuit S/HIII is connected with the LIN pin; the sampling and holding circuit S/HIII is connected with the sampling and holding circuit S/HIV in parallel, and the output end of the sampling and holding circuit S/HIV is connected with the positive input end of the voltage follower VFIV; output end of voltage follower VFIII and switch S ₅ Is connected with one end of the connecting rod; output end of voltage follower VFIV and switch S ₆ Is connected with one end of the connecting rod; switch S ₅ The other end of (C) is respectively connected with the voltage acquisition capacitor C ₄ Upper pole plate of (S) switch (S) ₇ Is connected with one end of the connecting rod; voltage acquisition capacitor C ₄ The lower polar plate of (C) is respectively connected with a switch S ₈ One end of switch S ₆ Is connected to the other end of switch S ₈ The other end of the first electrode is grounded; switch S ₇ The other end of the feedback control circuit (3) is connected with the positive input end of an operational amplifier OPAII;

the feedback control circuit (3) comprises an operational amplifier OPAII, an output end of the operational amplifier OPAII and a variable current source I ₃ Connected to a variable current source I ₃ And micro current source I ₄ Capacitance C ₅ Parallel series resistor R ₂ Resistance R ₂ One way through the other end of the capacitor C ₆ One path of the NMOS transistor MII is grounded, the source electrode of the NMOS transistor MII is grounded, and the drain electrode of the NMOS transistor MII is connected between the LIN pin and the voltage acquisition circuit; capacitor C ₅ The lower electrode plate of the capacitor is grounded.

6. The slope control circuit of claim 5, wherein the gate voltage of the NMOS transistor MII is VDD and the LIN bus voltage is the lowest.

7. A slope control circuit based on LIN bus signal control according to claim 5 or 6, characterized in that the variable current source I ₃ Micro current source I ₄ Is a very small current source, ensures the capacitance C ₆ The upper voltage is pulled down all the time.

8. Slope control circuit based on LIN bus signal control according to claim 1, characterized in that the load circuit (2) comprises a load resistor R _load Load resistor R _load And load capacitance C _load After being connected in series, the LIN pin is connected with a load resistor R _load And load capacitance C _load Between them.

9. The control method of a slope control circuit based on LIN bus signal control according to claim 1, comprising the steps of:

step1: the voltage acquisition circuit respectively acquires the voltages on the upper polar plate and the lower polar plate through closing and closing control voltage acquisition capacitors of different switches, so that the voltage difference of LIN bus voltage is obtained;

step2: the feedback control circuit compares the voltage difference in Step1 with a reference voltage, and controls the pull-down current capability of the NMOS tube according to the comparison result;

step3: step1 and Step2 are repeated for a plurality of times, the beat is determined by an on-chip clock, and the acquisition times are based on the frequency of the LIN on-chip clock.