CN117856782A - Burst mode data clock recovery module, burst mode data clock recovery method and optical line terminal - Google Patents

Abstract

The application provides a burst mode data clock recovery module, comprising: the data sampling submodule is configured to sample the received data according to the clock signal and output a sampling result to the phase judgment submodule; the phase judgment sub-module is configured to determine a phase judgment result of the clock signal according to the sampling result; the filter circuit is configured to filter the phase determination result by adopting a bandwidth corresponding to the phase determination result according to the phase determination result output by the phase determination sub-module; the clock adjustment submodule is configured to adjust a clock signal according to the filtered phase information and send the adjusted clock signal to the data sampling submodule, so that the data sampling submodule samples received data according to the adjusted clock signal. The application also provides a burst mode data clock recovery method and an optical line terminal.

Description

Burst mode data clock recovery module, method and optical line terminal

Technical Field

The embodiments of the present application relate to a passive optical network (Full name in English: Passive Optical Network, English abbreviation: PON) system transmission technology, and more particularly to a burst mode data clock recovery module, method and optical line terminal (Full name in English: Optical Line Terminal, English abbreviation: OLT).

Background technique

In recent years, with the rapid development of the access market and the rapid development of full-service operations around the world, the existing PON technical standards are facing new upgrade requirements in terms of bandwidth requirements, service support capabilities, and performance improvement of access node equipment and supporting equipment. The existing data clock recovery (CDR) circuit can no longer meet the demand for fast data locking.

The burst mode clock and data recovery (BCDR) technology is widely used in the OLT end of the PON transmission field. In the PON transmission protocol, one OLT connects to multiple ONUs, which requires the OLT to quickly recover burst data from different ONUs and improve the transmission rate of effective data.

In existing BCDR solutions, in application scenarios below 10G, since the channel attenuation is small and the equalization requirement is not high, a simple preamble code, such as 0101 code pattern, can be used to achieve data recovery. However, in application scenarios above 10G, due to the large channel attenuation, the 0101 code pattern cannot guarantee the normal transmission of the recovered data, and a pseudo-random binary sequence (full name: Pseudo-Random Binary Sequence, English abbreviation: prbs) code pattern is required as a preamble code for clock recovery and equalization training. However, the use of a fixed code pattern to achieve fast data locking is prone to compatibility and increased electromagnetic radiation problems.

Summary of the invention

Embodiments of the present application provide a burst mode data clock recovery module, method, and optical line terminal.

In a first aspect, the embodiment of the present application provides a burst mode data clock recovery module, including: a data sampling submodule, a phase determination submodule, a filtering circuit and a clock adjustment submodule, wherein

The data sampling submodule is configured to sample the received data according to the clock signal and output the sampling result to the phase determination submodule;

The phase determination submodule is configured to determine a phase determination result of the clock signal according to the sampling result, and output the phase determination result to the filtering circuit, wherein the phase determination result includes phase information of whether there is an offset phase;

The filtering circuit is configured to filter the phase determination result according to the phase determination result output by the phase determination submodule using a bandwidth corresponding to the phase determination result, and output the filtered phase information to the clock adjustment submodule;

The clock adjustment submodule is configured to adjust the clock signal according to the filtered phase information, and send the adjusted clock signal to the data sampling submodule, so that the data sampling submodule samples the received data according to the adjusted clock signal.

In some embodiments, the filtering circuit further includes a first fixed offset submodule, a first control submodule, a selection submodule, and a first digital filter, and the phase determination result includes phase information of the presence of an offset phase; and

In response to the existence of an offset phase, the first control submodule is configured to control the first fixed offset submodule to transmit a preset fixed offset to the first digital filter according to a phase determination result of the phase determination submodule, the first digital filter is configured to filter the phase determination result according to the fixed offset, and the selection submodule is configured to output the phase information filtered by the first digital filter to the clock adjustment submodule.

In some embodiments, the filtering circuit also includes a second digital filter, and the phase determination result also includes phase information in which there is no offset phase; and in response to the absence of an offset phase, the first control submodule is configured to output the phase determination result of the phase determination submodule to the second digital filter, the first digital filter is configured to transmit the phase information filtered by the first digital filter to the second digital filter, the second digital filter is configured to use the filtered phase information output by the first digital filter as an initial value, filter the phase determination result according to the initial value, and the selection submodule is configured to output the phase information filtered by the second digital filter to the clock adjustment submodule.

In some embodiments, the bandwidth of the first digital filter is greater than the bandwidth of the second digital filter.

In some embodiments, the filtering circuit includes a second fixed offset submodule, a second control submodule and a third digital filter, the third filter has an initial bandwidth parameter, and the phase determination result also includes phase information of the presence of an offset phase; and in response to the presence of an offset phase, the second control submodule is configured to control the second fixed offset submodule to transmit a preset fixed offset to the third digital filter according to the phase determination result of the phase determination submodule, and the third digital filter is configured to filter the phase determination result according to the initial bandwidth parameter and the fixed offset, and output the filtered phase information to the clock adjustment submodule.

In some embodiments, the phase determination result also includes phase information in which there is no offset phase. In response to the absence of an offset phase, the second control submodule is configured to adjust the bandwidth parameter of the third filter, and the third digital filter is configured to use the filtered phase information output by the third digital filter as an initial value, filter the phase determination result according to the initial value and according to the adjusted bandwidth parameter, and output the filtered phase information to the clock adjustment submodule.

In some embodiments, the second control submodule is configured to adjust a bandwidth parameter of the third digital filter so that the bandwidth parameter is smaller than an initial bandwidth parameter.

In some embodiments, the phase determination submodule is configured to detect edge information of the received sampling result and a clock signal to determine phase information of the clock signal.

In a second aspect, an embodiment of the present application provides an optical line terminal OLT, wherein the OLT includes a burst mode data clock recovery module according to any one of claims 1 to 8.

In a third aspect, an embodiment of the present application provides a burst mode data clock recovery method, comprising:

Sample the received data according to the clock signal and output the sampling result;

Determine a phase determination result of the clock signal according to the sampling result, and output the phase determination result, wherein the phase determination result includes phase information of whether there is an offset phase;

According to the phase determination result, filtering the phase determination result using a bandwidth corresponding to the phase determination result, and outputting filtered phase information; and

The clock signal is adjusted according to the filtered phase information, and the adjusted clock signal is output to sample received data according to the adjusted clock signal.

The burst mode data clock recovery module, method and optical line terminal provided in the embodiments of the present application are configured to sample received data according to a clock signal through a data sampling submodule, the phase determination submodule is configured to determine a phase determination result of the clock signal according to the sampling result, the filtering circuit is configured to filter the phase determination result according to the phase determination result output by the phase determination submodule using a bandwidth corresponding to the phase determination result, the clock adjustment submodule is configured to adjust the clock signal according to the filtered phase information, and send the adjusted clock signal to the data sampling submodule, so that the data sampling submodule samples the received data according to the adjusted clock signal, and can quickly realize clock recovery and data locking in application scenarios with a rate above 10G, avoiding dependence on data code type.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a burst mode data clock recovery module provided in an embodiment of the present application;

FIG2 is a schematic diagram of the structure of a filter circuit of a burst mode data clock recovery module provided in an embodiment of the present application;

3 is a schematic diagram of the structure of another filter circuit of a burst mode data clock recovery module provided in an embodiment of the present application;

FIG4 is a flow chart of a burst mode data clock recovery method provided in an embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the technical solution of the present application, the burst mode data clock recovery module, method and optical line terminal provided by the present application are described in detail below with reference to the accompanying drawings.

Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make this application thorough and complete and to enable those skilled in the art to fully understand the scope of this application.

In the absence of conflict, the embodiments of the present application and the features therein may be combined with each other.

As used herein, the term "and/or" includes any and all combinations of at least one of the associated listed items.

The terms used herein are only used to describe specific embodiments and are not intended to limit the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and/or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and/or components is specified, but the presence or addition of at least one other feature, whole, step, operation, element, component and/or its group is not excluded.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.

Generally, burst mode data clock recovery is a type of data clock recovery CDR. Existing CDR circuits are usually based on oversampling solutions to achieve fast CDR recovery, but the problem is that the sampling rate is high, the power consumption is large, and it is only suitable for low-speed scenarios. There is also a problem of slow boundary jump, which affects the CDR locking time.

FIG1 is a schematic diagram of the structure of a burst mode data clock recovery module according to an embodiment of the present application.

In the first aspect, referring to FIG. 1 , an embodiment of the present application provides a burst mode data clock recovery module, the burst mode data clock recovery module comprising: a data sampling submodule 1 , a phase determination submodule 2 , a filtering circuit 3 and a clock adjustment submodule 4 .

The data sampling submodule 1 is configured to sample received data according to a clock signal and output the sampling result to the phase determination submodule 2 .

The phase determination submodule 2 is configured to determine a phase determination result of the clock signal according to the sampling result, and output the phase determination result to the filter circuit 3, wherein the phase determination result includes phase information of whether there is an offset phase.

The filter circuit 3 is configured to filter the phase determination result output by the phase determination submodule 2 using a bandwidth corresponding to the phase determination result, and output the filtered phase information to the clock adjustment submodule 4 .

The clock adjustment submodule 4 is configured to adjust the clock signal according to the filtered phase information, and send the adjusted clock signal to the data sampling submodule 1, so that the data sampling submodule 1 samples the received data according to the adjusted clock signal.

The burst mode data clock recovery module provided in this embodiment is configured to sample the received data according to the clock signal through the data sampling submodule 1, the phase determination submodule 2 is configured to determine the phase determination result of the clock signal according to the sampling result, the filtering circuit 3 is configured to filter the phase determination result according to the phase determination result output by the phase determination submodule 2 using a bandwidth corresponding to the phase determination result, the clock adjustment submodule 4 is configured to adjust the clock signal according to the filtered phase information, and send the adjusted clock signal to the data sampling submodule 1, so that the data sampling submodule 1 samples the received data according to the adjusted clock signal, and can quickly realize clock recovery and data locking in application scenarios with a rate of 10G or above, avoiding dependence on data pattern.

In some embodiments, the clock adjustment submodule 4 can be implemented by a phase interpolator (PI) circuit. The PI circuit modifies the phase of the clock so that the clock can be sampled in the middle of the input data, that is, the best sampling point or locking position. For example, the PI circuit can be a four-phase clock.

In some embodiments, the phase determination submodule 2 is configured to detect edge information of the received sampling result and the clock signal to determine whether the clock signal has phase information of an offset phase.

FIG2 is a schematic diagram of the structure of the filter circuit of the burst mode data clock recovery module of an embodiment of the present application. Referring to FIG2 , in some embodiments, the filter circuit 3 may include a first fixed offset submodule 301 , a first control submodule 302 , a selection submodule 303 and a first digital filter 304 .

The phase determination result includes phase information of a phase offset.

In response to the first control submodule 302 determining that the phase determination result of the phase determination submodule 2 has an offset phase, the first control submodule 302 is configured to control the first fixed offset submodule 301 to transmit a preset fixed offset to the first digital filter 304 according to the phase determination result of the phase determination submodule 2, the first digital filter 304 is configured to filter the phase determination result according to the fixed offset, and the selection submodule 303 is configured to output the phase information filtered by the first digital filter 304 to the clock adjustment submodule 4.

Through the filter circuit 3 of this embodiment, a fixed phase offset is generated by the clock signal in the clock adjustment submodule 4, so as to ensure that the CDR lock process jumps out of the slower locking area. For example, when the adjustment accuracy of the clock adjustment submodule is 128 steps, when there is no input signal, the first fixed offset control submodule 301 is used to move the clock control signal by 1 step per beat, so as to achieve a fixed phase offset of the input clock.

In some embodiments, the filtering circuit 3 may further include a second digital filter 305, and the phase determination result also includes phase information that there is no offset phase; and in response to the first control submodule 302 judging that the phase determination result of the phase determination submodule 2 does not have an offset phase, the first control submodule 302 is configured to output the phase determination result of the phase determination submodule 2 to the second digital filter 305, the first digital filter 304 is configured to transmit the phase information filtered by the first digital filter to the second digital filter 305, the second digital filter 305 is configured to use the phase information filtered by the first digital filter as an initial value, and filter the phase determination result according to the initial value, and the selection submodule 303 is configured to output the phase information filtered by the second digital filter 305 to the clock adjustment submodule 4.

It should be noted that the first control submodule 302 and the selection submodule 303 can be implemented together or separately, and can be implemented based on external signal control, internal counting control, or signal detection control, which is not limited in this embodiment.

The bandwidth of the first digital filter 304 is greater than the bandwidth of the second digital filter 305. Specifically, the depth of the first digital filter 304 and the second digital filter 305 can be adjusted to implement bandwidth configuration and adjustment.

This ensures that the CDR can achieve fast locking when locking and good performance when recovering data. In addition, by adding a small offset to the filter circuit, the problem of slow locking time due to slow boundary jump in traditional CDR circuits is solved.

FIG3 is a schematic diagram of the structure of the filter circuit of the burst mode data clock recovery module according to an embodiment of the present application. Referring to FIG3 , in some embodiments, the filter circuit 3 may include: a second fixed offset submodule 306 , a second control submodule 307 and a third digital filter 308 .

The third digital filter 308 has an initial bandwidth parameter, and the phase determination result also includes phase information of the presence of an offset phase; and in response to the second control submodule 307 determining that the phase determination result of the phase determination submodule 2 has an offset phase, the second control submodule 307 is configured to control the second fixed offset submodule 306 to transmit a preset fixed offset to the third digital filter 308 according to the phase determination result of the phase determination submodule 2, and the third digital filter 308 is configured to filter the phase determination result according to the initial bandwidth parameter and the fixed offset, and output the filtered phase information to the clock adjustment submodule 4.

Through the filter circuit 3 of this embodiment, a fixed phase offset is generated by the clock signal in the clock adjustment submodule 4, so as to ensure that the CDR lock process jumps out of the slower locking area. For example, when the adjustment accuracy of the clock adjustment submodule is 128 steps, when there is no input signal, the second fixed offset control submodule 306 is used to move the clock control signal by 1 step per beat, so as to achieve a fixed phase offset of the input clock.

In some embodiments, the phase determination result also includes phase information that there is no offset phase. In response to the second control submodule 307 determining that the phase determination result of the phase determination submodule 2 does not have an offset phase, the second control submodule 307 is configured to adjust the bandwidth parameter of the third digital filter 308, and the third digital filter 308 is configured to use the filtered phase information output by the third digital filter as an initial value, filter the phase determination result according to the initial value and according to the adjusted bandwidth parameter, and output the filtered phase information to the clock adjustment submodule 4.

In some embodiments, the second control submodule 307 is configured to adjust a bandwidth parameter of the third digital filter 308 so that the bandwidth parameter is smaller than an initial bandwidth parameter.

Specifically, the depth of the third digital filter 308 may be adjusted to implement bandwidth configuration and adjustment.

It should be noted that the second control submodule 307 can be implemented based on external signal control, internal counting control, or signal detection control, which is not limited in this embodiment.

This ensures that the CDR can achieve fast locking when locking and good performance when recovering data. In addition, by adding a small offset in the filter circuit, the problem of slow locking time due to slow boundary jump in traditional CDR circuits is solved.

In a second aspect, an embodiment of the present application provides an optical line terminal OLT, wherein the OLT includes a burst mode data clock recovery module as described above.

FIG. 4 is a flow chart of a burst mode data clock recovery method according to an embodiment of the present application.

In a third aspect, referring to FIG. 4 , an embodiment of the present application provides a burst mode data clock recovery method, including:

Step 1, sampling the received data according to the clock signal and outputting the sampling result;

Step 2, determining a phase determination result of the clock signal according to the sampling result, and outputting the phase determination result, wherein the phase determination result includes phase information of whether there is a phase offset;

Step 3, according to the phase determination result, filtering the phase determination result using a bandwidth corresponding to the phase determination result, and outputting filtered phase information; and

Step 4: adjust the clock signal according to the filtered phase information, and output the adjusted clock signal to sample the received data according to the adjusted clock signal.

The burst mode data clock recovery method provided in this embodiment samples the received data according to the clock signal and outputs the sampling result; determines the phase determination result of the clock signal according to the sampling result, and outputs the phase determination result, wherein the phase determination result includes phase information of whether there is an offset phase; filters the phase determination result according to the phase determination result using a bandwidth corresponding to the phase determination result, and outputs the filtered phase information; and adjusts the clock signal according to the filtered phase information, and outputs the adjusted clock signal to sample the received data according to the adjusted clock signal. In application scenarios above 10G, clock recovery and data locking can be quickly realized, avoiding dependence on data pattern.

The definition of the burst mode data clock recovery module is also applicable to the method in this embodiment and will not be described in detail here.

It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules/units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and/or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and/or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present application as set forth in the appended claims.

Claims (10)

1. A burst mode data clock recovery module, comprising: a data sampling submodule, a phase determination submodule, a filtering circuit and a clock adjustment submodule, wherein: The data sampling submodule is configured to sample the received data according to the clock signal and output the sampling result to the phase determination submodule; The phase determination submodule is configured to determine a phase determination result of the clock signal according to the sampling result, and output the phase determination result to the filtering circuit, wherein the phase determination result includes phase information of whether there is an offset phase; The filtering circuit is configured to filter the phase determination result according to the phase determination result output by the phase determination submodule using a bandwidth corresponding to the phase determination result, and output the filtered phase information to the clock adjustment submodule; The clock adjustment submodule is configured to adjust the clock signal according to the filtered phase information, and send the adjusted clock signal to the data sampling submodule, so that the data sampling submodule samples the received data according to the adjusted clock signal. 2. The burst mode data clock recovery module according to claim 1, wherein: The filtering circuit further includes a first fixed offset submodule, a first control submodule, a selection submodule and a first digital filter, and the phase determination result includes phase information of an offset phase; and In response to the existence of an offset phase, the first control submodule is configured to control the first fixed offset submodule to transmit a preset fixed offset to the first digital filter according to a phase determination result of the phase determination submodule, the first digital filter is configured to filter the phase determination result according to the fixed offset, and the selection submodule is configured to output the phase information filtered by the first digital filter to the clock adjustment submodule. 3. The burst mode data clock recovery module according to claim 2, wherein: The filtering circuit further includes a second digital filter, and the phase determination result further includes phase information that does not have an offset phase; and In response to the absence of an offset phase, the first control submodule is configured to output the phase determination result of the phase determination submodule to the second digital filter, the first digital filter is configured to transmit the phase information filtered by the first digital filter to the second digital filter, the second digital filter is configured to use the filtered phase information output by the first digital filter as an initial value and filter the phase determination result according to the initial value, and the selection submodule is configured to output the phase information filtered by the second digital filter to the clock adjustment submodule. 4. The burst mode data clock recovery module according to claim 3, wherein: The bandwidth of the first digital filter is greater than the bandwidth of the second digital filter. 5. The burst mode data clock recovery module according to claim 1, wherein: The filtering circuit includes a second fixed offset submodule, a second control submodule and a third digital filter, the third filter has an initial bandwidth parameter, and the phase determination result also includes phase information of an offset phase; and In response to the existence of an offset phase, the second control submodule is configured to control the second fixed offset submodule to transmit a preset fixed offset to the third digital filter according to the phase determination result of the phase determination submodule, and the third digital filter is configured to filter the phase determination result according to an initial bandwidth parameter and the fixed offset, and output the filtered phase information to the clock adjustment submodule. 6. The burst mode data clock recovery module according to claim 5, wherein: The phase determination result also includes phase information in which there is no offset phase. In response to the absence of an offset phase, the second control submodule is configured to adjust a bandwidth parameter of the third filter, and the third digital filter is configured to use the filtered phase information output by the third digital filter as an initial value, filter the phase determination result according to the initial value and according to the adjusted bandwidth parameter, and output the filtered phase information to the clock adjustment submodule. 7. The burst mode data clock recovery module according to claim 6, wherein: The second control submodule is configured to adjust a bandwidth parameter of the third digital filter so that the bandwidth parameter is smaller than an initial bandwidth parameter. 8. The burst mode data clock recovery module according to claim 1, wherein: The phase determination submodule is configured to detect edge information of the received sampling result and the clock signal to determine whether the clock signal has phase information of a shifted phase. 9. An optical line terminal (OLT), wherein the OLT comprises a burst mode data clock recovery module according to any one of claims 1 to 8. 10. A burst mode data clock recovery method, comprising: Sample the received data according to the clock signal and output the sampling result; Determine a phase determination result of the clock signal according to the sampling result, and output the phase determination result, wherein the phase determination result includes phase information of whether there is an offset phase; According to the phase determination result, filtering the phase determination result using a bandwidth corresponding to the phase determination result, and outputting filtered phase information; and The clock signal is adjusted according to the filtered phase information, and the adjusted clock signal is output to sample received data according to the adjusted clock signal.