CN117832228A

CN117832228A - Array substrate and touch display device

Info

Publication number: CN117832228A
Application number: CN202410009994.7A
Authority: CN
Inventors: 郑翠翠; 邹佳滨; 栗峰; 文娜; 金健; 桑琦; 闫岩; 马禹; 王静; 郭晖; 陈维涛; 董懿嘉
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2024-01-02
Filing date: 2024-01-02
Publication date: 2024-04-05

Abstract

An array substrate and a touch display device. The array substrate includes a plurality of first sub-pixels, the plurality of first sub-pixels include compensation sub-pixels and reference sub-pixels, the compensation sub-pixels include a first pixel electrode and a first common electrode, the first common electrode includes two parts separated by a spacer, the spacer is projected on the array substrate within the first pixel electrode's projection on the array substrate; the reference sub-pixel includes a second pixel electrode and a second common electrode, both of which are reused as touch electrodes; the first pixel electrode and the first common electrode have a first overlapping area when projected on the array substrate; the second pixel electrode and the second common electrode have a second overlapping area when projected on the array substrate, the absolute value of the difference between the first overlapping area and the second overlapping area is less than or equal to 4% of the smaller area between the first overlapping area and the second overlapping area, and problems such as dark lines can be improved.

Description

Array substrate and touch display device

Technical Field

The disclosure relates to the field of display technologies, and in particular, to an array substrate and a touch display device.

Background

Touch screens are visible everywhere around us. The touch screen has the advantages of space saving, portability, good man-machine interaction and the like. Among various touch screens, capacitive touch screens are widely used because of their strong sensitivity and the ability to realize multi-touch. In order to reduce the thickness of the touch device, in-cell (In cell) touch structures are receiving attention, and the In-cell touch structures include two types of self-capacitance touch and mutual-capacitance touch.

Currently, touch screens have the problem of locally displaying dark lines.

Disclosure of Invention

The embodiment of the disclosure provides an array substrate and a touch display device, which can solve the problem of local display dark lines of the conventional touch display device.

In one aspect, an embodiment of the present disclosure provides an array substrate. The array substrate comprises a display area, wherein the display area comprises a plurality of first sub-pixels, the first sub-pixels are configured to emit light rays of a first color, and the first color is one of three primary colors;

the plurality of first sub-pixels comprise compensation sub-pixels and reference sub-pixels, the compensation sub-pixels comprise first pixel electrodes and first common electrodes which are oppositely arranged, the first common electrodes comprise two parts separated by a spacing zone, and the orthographic projection of the spacing zone on the plane of the array substrate is positioned in the orthographic projection of the first pixel electrodes on the plane of the array substrate; the reference sub-pixel comprises a second pixel electrode and a second common electrode which are oppositely arranged, and the first common electrode and the second common electrode are multiplexed into a touch electrode;

The front projection of the first pixel electrode on the plane of the array substrate and the front projection of the first common electrode on the plane of the array substrate have a first overlapping area, and the first overlapping area has a first overlapping area; and a second overlapping area exists between the orthographic projection of the second pixel electrode on the plane of the array substrate and the orthographic projection of the second common electrode on the plane of the array substrate, the second overlapping area has a second overlapping area, and the absolute value of the difference between the first overlapping area and the second overlapping area is smaller than or equal to 4% of the smaller area of the first overlapping area and the second overlapping area.

In an exemplary embodiment, a first storage capacitance is provided between the first pixel electrode and the first common electrode, a second storage capacitance is provided between the second pixel electrode and the second common electrode, and an absolute value of a difference between the first storage capacitance and the second storage capacitance is less than or equal to 4% of a smaller capacitance of the first storage capacitance and the second storage capacitance.

In an exemplary embodiment, the first pixel electrode includes a compensation portion, where a front projection of the compensation portion on a plane of the array substrate and a front projection of the first common electrode on the plane of the array substrate overlap at least partially, and the compensation portion is configured to compensate for a difference between the first storage capacitor and the second storage capacitor.

In an exemplary embodiment, an area of an overlapping portion between the orthographic projection of the compensation portion on the plane of the array substrate and the orthographic projection of the first common electrode on the plane of the array substrate is denoted as S, where S satisfies equation (1):

S＝Cd/εδ (1)

wherein C is the absolute value of the difference between the first storage capacitor and the second storage capacitor; δ=1/4pi_k, where ε is the dielectric constant of the medium between the first pixel electrode and the first common electrode, K is the electrostatic force constant, and d is the distance between the first pixel electrode and the first common electrode along the thickness direction of the array substrate.

In an exemplary embodiment, in a plane perpendicular to the array substrate, the display area includes a substrate, and a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially located at one side of the substrate;

the first pixel electrode and the second pixel electrode are both positioned on the third conductive layer, and the first common electrode and the second common electrode are both positioned on the fourth conductive layer.

In an exemplary embodiment, the display area further includes a plurality of data lines and at least one touch signal line on one side of the substrate; the plurality of data lines and the at least one touch signal line are all arranged at intervals along a first direction and extend along a second direction, wherein the first direction and the second direction are crossed.

In an exemplary embodiment, the at least one touch signal line and the plurality of data lines are located on the same conductive layer.

In an exemplary embodiment, the at least one touch signal line is located on the second conductive layer.

In an exemplary embodiment, a line width of the touch signal line is greater than a line width of the data line.

In an exemplary embodiment, the display region further includes a second insulating layer between the second conductive layer and the third conductive layer, and a third insulating layer between the third conductive layer and the fourth conductive layer in a plane perpendicular to the array substrate; the third insulating layer is provided with at least one via hole;

the at least one touch signal line is located on the second conductive layer, the at least one via hole exposes a part of the surface of the at least one touch signal line, which is far away from one side of the substrate, and the first common electrode is connected with the at least one touch signal line through the at least one via hole.

In an exemplary embodiment, the plurality of data lines includes a first data line, a second data line, and a third data line sequentially arranged along the first direction; a first interval along the first direction is arranged between the first data line and the second data line, a second interval along the first direction is arranged between the second data line and the third data line, and the first interval is larger than the second interval;

The at least one touch signal line is located between the first data line and the second data line.

In an exemplary embodiment, the orthographic projection of the first pixel electrode on the plane of the array substrate is located between the orthographic projection of the first data line on the plane of the array substrate and the orthographic projection of the second data line on the plane of the array substrate.

In an exemplary embodiment, the compensation sub-pixel further includes at least one transistor including a first pole, a second pole, a gate electrode, and an active layer; the grid electrode is positioned on the first conductive layer; the first pole and the second pole are both located in the second conductive layer, and the active layer is located between the first conductive layer and the second conductive layer.

In an exemplary embodiment, the first electrode and the data line are integrally formed as a single structure.

On the other hand, an embodiment of the disclosure provides a touch display device, including the array substrate described in any one of the embodiments.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.

Fig. 1 is a schematic structural diagram of a touch display device according to an embodiment of the disclosure;

FIG. 2 is a schematic front view of an array substrate according to an embodiment of the disclosure;

FIG. 3 is a schematic top view of a portion of an array substrate according to an embodiment of the disclosure;

FIG. 4 is a schematic partial top view of an array substrate according to an embodiment of the disclosure after forming a first conductive layer pattern;

FIG. 5 is a schematic partial top view of an array substrate according to an embodiment of the disclosure after forming a semiconductor layer pattern;

FIG. 6 is a schematic partial top view of an array substrate according to an embodiment of the disclosure after forming a second conductive layer pattern;

FIG. 7 is a schematic partial top view of an array substrate according to an embodiment of the disclosure after forming a second insulating layer pattern;

FIG. 8 is a schematic partial top view of an array substrate according to an embodiment of the disclosure after forming a third conductive layer pattern;

FIG. 9 is a schematic partial top view of an array substrate according to an embodiment of the disclosure after forming a third insulating layer pattern;

Fig. 10 is a schematic partial top view of an array substrate according to an embodiment of the disclosure after forming a fourth conductive layer pattern.

Reference numerals:

100-touch area, 101-touch sensing block, 102-touch signal line, 103-touch control circuit, 104-spacer;

AA-display area, BB-frame area, B1-first frame area, B2-second frame area, DL-data line, DL-1-first data line, DL-2-second data line, DL-3-third data line, GL-gate line, GL-1-gate protrusion;

10-first electrode, 111-first pixel electrode, 112-second pixel electrode, 113-compensation section, 20-second electrode, 201-gap, 211-first common electrode, 212-second common electrode, 30-transistor, 301-first electrode, 302-second electrode, 302-1-first region, 302-2-second region, 302-3-third region, 303-gate, 304-active layer, 40-substrate.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. Embodiments may be implemented in a number of different forms. One of ordinary skill in the art will readily recognize the fact that the patterns and matters may be changed into one or more forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.

In the drawings, the size of one or more constituent elements, thicknesses of layers or regions may be exaggerated for clarity. Accordingly, one aspect of the present disclosure is not necessarily limited to this dimension, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Further, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or numerical values shown in the drawings, and the like.

The ordinal terms such as "first," "second," "third," and the like in the present disclosure are provided to avoid intermixing of constituent elements, and are not intended to be limiting in number. The term "plurality" in this disclosure includes two as well as more than two numbers.

In the present disclosure, for convenience, terms such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe positional relationships of the constituent elements with reference to the drawings, only for convenience in describing the present specification and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The meaning of the above terms in the present disclosure can be understood by one of ordinary skill in the art as appropriate.

In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Thus, in this disclosure, the "source electrode" and the "drain electrode" may be interchanged.

In this disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having one or more functions, and the like.

In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and thus, may include a state in which the angle is-5 ° or more and 5 ° or less. Further, "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus may include a state in which an angle is 85 ° or more and 95 ° or less.

In this disclosure, "film" and "layer" may be interchanged. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The term "about" in this disclosure refers to values that are not strictly limited to the limits, but are allowed to fall within the limits of the process and measurement errors.

An embodiment of the disclosure provides an array substrate, including a display area, where the display area includes a plurality of first sub-pixels configured to emit light of a first color, where the first color is one of three primary colors;

According to the array substrate provided by the embodiment of the disclosure, the relation between the first overlapping area and the second overlapping area is limited, so that the capacitance difference between the first storage capacitor and the second storage capacitor is indirectly limited, the display difference of sub-pixels with the same color caused by multiplexing the common electrode into the touch electrode can be avoided, the problems of dark lines and the like can be avoided, and the display quality can be improved.

Fig. 1 is a schematic structural diagram of a touch display device according to an embodiment of the disclosure. The touch display device shown in fig. 1 may be an in-cell touch display device using a self-capacitance touch technology. As shown in fig. 1, in the in-cell touch display device, the touch display device may include a plurality of touch sensing blocks (as self-capacitance electrodes) 101 arranged in an array, and touch signal lines 102 electrically connected to the touch sensing blocks 101, respectively. The black dots in fig. 1 are schematic electrical connections. The touch control circuit 103 is located at one side of the touch area 100 of the touch display device. The touch signal line 102 may electrically connect the touch sensing block 101 to the touch control circuit 103. When performing a touch, a touching object (e.g., a human finger) touches the touch area 100 of the touch display device, the capacitance of the touched touch sensing block 101 changes, and the touch control circuit 103 is configured to determine the touch position by detecting the change in self capacitance of the touch sensing block 101.

Fig. 2 is a schematic front view of an array substrate according to an embodiment of the disclosure. The touch display device may include an array substrate. As shown in fig. 2, the array substrate may include a display area AA and a bezel area BB located at least one side of the display area AA. The bezel area BB may include a first bezel area B1 located at one side of the display area AA and a second bezel area B2 located at the remaining side of the display area AA. For example, the first frame region B1 may include a lower frame of the array substrate, and the second frame region B2 may include an upper frame, a left frame, and a right frame of the array substrate. For example, the touch control circuit 103 may be located in the second frame area B2. The touch area 100 may be located in the display area AA, and for example, a boundary of the orthographic projection of the touch area 100 on the plane of the array substrate coincides with a boundary of the orthographic projection of the display area AA on the plane of the array substrate.

In an exemplary embodiment, as shown in fig. 2, the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on the substrate. The plurality of gate lines GL may extend in a first direction X and be sequentially arranged in a second direction Y different from the first direction X. The plurality of data lines DL may extend in the second direction Y and be sequentially arranged in the first direction X. Wherein the first direction X and the second direction Y may intersect, for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located at different film layers, for example, the plurality of data lines DL may be located at a side of the plurality of gate lines GL remote from the substrate.

In an exemplary embodiment, as shown in fig. 2, a plurality of data lines DL and a plurality of gate lines GL may cross to form a plurality of sub-pixel regions. The region defined by the adjacent data lines DL and the adjacent gate lines GL crossing each other may be a sub-pixel region. One sub-pixel may be disposed in correspondence with the sub-pixel region. The sub-pixel region may include an open region and a non-open region surrounding the open region. The non-opening region may be a region shielded by a black matrix of a counter substrate of the array substrate, and the opening region may be a region not shielded by a black matrix of the counter substrate. Adjacent gate lines GL and data lines DL may be both located in the non-opening region. The array substrate of the embodiment of the disclosure may be used to implement a display function, and the opening area of each sub-pixel area may be configured to display. The non-open area may surround the open area and is not shown. However, the embodiments of the present disclosure are not limited in this regard. In some examples, the array substrate may be used to implement other functions.

In an exemplary embodiment, the display area AA may include a plurality of pixel units disposed on a substrate. The at least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel sequentially arranged along the first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be sequentially arranged in the order of the blue sub-pixel, the red sub-pixel, and the green sub-pixel. As shown in fig. 2, at least one subpixel may include: the first electrode 10 and the second electrode (not shown in fig. 2) and the front projections of the first electrode 10 and the second electrode of the sub-pixel in the plane of the substrate may be partially overlapping. The second electrodes of the plurality of sub-pixels of the display area AA may be of unitary construction. By way of example, the second electrode may be located on a side of the first electrode 10 remote from the substrate. The sub-pixel may also include a transistor 30. The transistor 30 may be adjacent to the crossing position of the data line DL and the gate line GL. Transistor 30 may include a gate, a first pole, and a second pole. The gate electrode may be electrically connected to the gate line GL, a first electrode of the transistor 30 may be electrically connected to the data line DL, and a second electrode may be electrically connected to the first electrode 10 of one sub-pixel. The transistor 30 may be configured to supply a data signal transmitted by the data line DL to the first electrode 10 of the sub-pixel under the control of the gate line GL. Illustratively, in the embodiments of the present disclosure, the first electrode 10 may be a pixel electrode of a sub-pixel, and the second electrode may be a common electrode of the sub-pixel.

In an exemplary embodiment, the second bezel area B2 may include at least a gate driving circuit (e.g., including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected with the plurality of gate lines GL in the display area AA. The gate driving circuit may further include a transistor. The structure of the transistor located in the second frame region B2 may be the same as or different from the structure of the transistor located in the display region AA.

Fig. 3 is a schematic partial top view of an array substrate according to an embodiment of the disclosure. As shown in fig. 3, only four sub-pixels are illustrated as an example, and the four sub-pixels may be a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a first sub-pixel P1 sequentially arranged along the first direction X, respectively. For example, the first subpixel P1 may be a blue subpixel, the second subpixel P2 may be a red subpixel, and the third subpixel P3 may be a green subpixel.

As shown in fig. 3, the array substrate may include a plurality of touch sensing blocks 101 arranged at intervals, and the touch sensing blocks 101 may include a plurality of touch electrodes. For example, the array substrate may include 22×36 touch sensing blocks. In the first direction X, a spacer 104 exists between two adjacent touch sensing blocks 101. For example, the spacer 104 may be located at the first subpixel P1. In the embodiment of the present disclosure, the second electrode of the sub-pixel may be multiplexed as a touch electrode, and a plurality of touch electrodes located in the same touch sensing block 101 may be an integral structure connected to each other. In the display stage of the touch display device, the array substrate can provide a common electrode signal for the second electrode through the touch signal line 102, so that the whole touch display device realizes a display function, and in the touch stage of the touch display device, the array substrate can receive a touch signal detected by the second electrode through the touch signal line 102, so that the whole touch display device realizes a touch function. In some examples, each touch sensing block may include a plurality of second electrodes multiplexed as touch electrodes.

The structure of the array substrate is described below by way of an example of a preparation process of the array substrate. The "patterning process" in the embodiments of the present disclosure includes processes of coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metallic materials, inorganic materials, or transparent conductive materials, and processes of coating organic materials, mask exposure, development, etc. for organic materials. The deposition process may be any one or more of sputtering, vapor deposition, and chemical vapor deposition, the coating process may be any one or more of spraying, spin coating, and ink jet printing, and the etching process may be any one or more of dry etching and wet etching, which is not limited in this disclosure. "film" refers to a thin film of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if the "thin film" does not require a patterning process throughout the fabrication process. If the patterning process is required during the whole manufacturing process, the "thin film" is called a "thin film" before the patterning process, and the "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The term "a and B co-layer structures" as used in this disclosure means that a and B are formed by the same patterning process.

The preparation process of the array substrate may include the following steps (11) to (17):

(11) A first conductive layer pattern is formed. Forming the first conductive layer pattern may include: a first conductive film is deposited on one side of the substrate 40, and the first conductive film is patterned through a patterning process to form a first conductive layer pattern on one side of the substrate 40. The first conductive layer may include a plurality of gate lines GL as shown in fig. 4.

As shown in fig. 4, the gate line GL may be a line shape in which a main body portion extends along the first direction X, and the gate line GL of each row of the sub-pixels may be disposed at a lower side of the row of the sub-pixels (a side of the row of the sub-pixels away from the next row of the sub-pixels, the rows of the sub-pixels being arranged along the second direction Y). The gate line GL is configured to be connected to a transistor in the sub-pixel, and may supply a gate driving signal to the transistor.

In an exemplary embodiment, the gate lines GL may be designed for an equal line width or for a non-equal line width. In the embodiment of the disclosure, the direction of the line width of the gate line GL refers to the direction in the plane of the array substrate and perpendicular to the extending direction of the gate line GL, that is, the second direction Y.

In an exemplary embodiment, the gate line GL may be provided with at least one gate protrusion GL-1. The first end of the gate protrusion GL-1 may be connected to the gate line GL, and the second end of the gate protrusion GL-1 may extend along the second direction Y. The orthographic projection of the gate protrusion GL-1 on the plane of the substrate 40 may be rectangular.

In an exemplary embodiment, at least a portion of the gate protrusion GL-1 may serve as the gate 303 of the transistor. By way of example, all of the gate protrusion GL-1 may be used as the gate electrode 303.

In an exemplary embodiment, the substrate 40 may provide support for film layers in the array substrate other than the substrate 40. By way of example, the substrate 40 may be a transparent base. For example, the substrate 40 may be a rigid base or a flexible base. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass, quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers. However, the embodiments of the present disclosure are not limited in this regard.

In an exemplary embodiment, the material of the first conductive layer may be a metallic material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the material of the first conductive layer may be an alloy material of a metal material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), for example, aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), molybdenum nickel titanium alloy (motiti). The first conductive layer may be a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti or Mo/Nb/Cu or MoNiTi/Cu or MoNb/Cu/MoNiTi or MoNiTi/Cu/MoNiTi, or the like.

(12) A semiconductor layer pattern is formed. Forming the semiconductor layer pattern may include: a first insulating film and a semiconductor film are sequentially deposited on a side of the substrate 40 on which the foregoing patterns are formed, and the semiconductor film is patterned by a patterning process to form a first insulating layer covering the first conductive layer pattern, and a semiconductor layer pattern on a side of the first insulating layer remote from the substrate. The semiconductor layer pattern may include at least an active layer 304 of a transistor, as shown in fig. 5.

In an exemplary embodiment, there may be at least partial overlap between the front projection of the active layer 304 on the plane of the array substrate and the front projection of the gate 303 on the plane of the array substrate, and, for example, the front projection of the active layer 304 on the plane of the array substrate and the front projection of the gate 303 on the plane of the array substrate may overlap. The gate electrode 303 can prevent light from being emitted to the active layer from a side close to the substrate, so that damage to the active layer caused by the light can be avoided, and the service performance of the transistor can be improved.

In an exemplary embodiment, the material of the active layer 304 may include a metal oxide semiconductor material. The metal oxide semiconductor material may include one or more metal oxide materials such as Indium Gallium Zinc Oxide (IGZO), zinc oxynitride (ZnON), indium Zinc Tin Oxide (IZTO), indium Gallium Tin Oxide (IGTO), indium Gallium Zinc Tin Oxide (IGZTO), indium gallium zinc Y oxide (IGZYO, Y represents doped tin), etc., however, the present disclosure is not limited to metal oxide semiconductor materials.

In an exemplary embodiment, the material of the first insulating layer may be an inorganic material. Inorganic materials such as silicon oxynitride (SiO) _x N _y ) Or silicon nitride (SiN) _x ) Or silicon oxide (SiO) _x ) And the like. The first insulating layer may be a single layer or a plurality of layers or a composite layer.

(13) And forming a second conductive layer pattern. Forming the second conductive layer pattern may include: a second conductive film is deposited on the side of the substrate 40 where the aforementioned pattern is formed, and the second conductive film is patterned by a patterning process to form a second conductive layer pattern on the side of the semiconductor layer remote from the substrate 40. The second conductive layer may include at least a plurality of data lines DL, a plurality of touch signal lines 102, and a first pole 301 and a second pole 302 of the transistor 30, as shown in fig. 6. By way of example, the first pole 301 may be a source electrode of a transistor and the second pole 302 may be a drain electrode of a transistor. Alternatively, the first pole 301 may be the drain electrode of the transistor and the second pole 302 may be the source electrode of the transistor.

In an exemplary embodiment, the plurality of data lines DL may include a first data line DL-1, a second data line DL-2, and a third data line DL-3 sequentially arranged along the first direction X. As shown in fig. 6, a first space W1 along the first direction X is provided between the first data line DL-1 and the second data line DL-2, and a second space W2 along the first direction X is provided between the second data line DL-2 and the third data line DL-3, wherein the first space W1 is larger than the second space W2. In the embodiment of the disclosure, the first interval W1 is the minimum distance between the first data line DL-1 and the second data line DL-2 along the first direction X, and the second interval W2 is the maximum distance between the second data line DL-2 and the third data line DL-3 along the first direction X. For example, the line widths of the first, second, and third data lines DL-1, DL-2, and DL-3 may be the same. In the embodiment of the present disclosure, the line width direction of the data line DL is the first direction X.

In an exemplary embodiment, as shown in FIG. 6, the touch signal line 102 may be located between the first data line DL-1 and the second data line DL-2, and the front projection of the touch signal line 102 on the plane of the array substrate and the front projection of the first data line DL-1 on the plane of the array substrate and the front projection of the second data line DL-2 on the plane of the array substrate do not overlap. For example, the line width of the touch signal line 102 may be greater than the line width of the first data line DL-1.

In an exemplary embodiment, the orthographic projection of the first pole 301 on the plane of the substrate 40 may be located within the orthographic projection of the active layer 304 on the plane of the substrate 40. The first electrode 301 and the data line DL of each sub-pixel may be an integral structure connected to each other. In an example, an overlapping area exists between the orthographic projection of the data line DL on the plane of the array substrate and the orthographic projection of the active layer 304 on the plane of the array substrate, and the overlapping area on the data line DL, that is, the first pole 301 of the transistor 30, and taking a part of the data line as the first pole of the transistor can improve the reasonability of the step line in the display area of the array substrate.

In an exemplary embodiment, the second pole 302 of each sub-pixel may be separately provided. There may be at least a partial overlap of the orthographic projection of the second pole 302 and the orthographic projection of the active layer 304 in the plane of the substrate. The active layer 304 between the first pole 301 and the second pole 302 may form a conductive channel region. The transistor 30 may include a gate 303, an active layer 304, a first pole 301, and a second pole 302.

In an exemplary embodiment, as shown in FIG. 6, the second pole 302 may include a first region 302-1, a second region 302-2, and a third region 302-3 connected. The second region 302-2 is located between the first region 302-1 and the third region 302-3, and the first region 302-1 is closer to the first data line DL-1 than the third region 302-3. As shown in fig. 6, the first region 302-1 may include a first end and a second end disposed opposite to each other in the second direction Y, the second end of the first region 302-1 extending in the second direction Y, and the first region 302-1 may have a rectangular shape. The second region 302-2 may include a first end and a second end disposed opposite to each other along the first direction X, the first end of the second region 302-2 is connected to the second end of the first region 302-1, the second end of the second region 302-2 extends along the first direction X, and the second region 302-2 may have a rectangular shape. The third region 302-3 may include a first end and a second end disposed opposite in the second direction Y, and the second end of the second region 302-2 is connected to a middle portion of the third region 302-3, and the middle portion of the third region 302-3 may be a middle point of the third region 302-3 in the second direction Y, for example. The third region 302-3 may be trapezoidal. For example, the front projection of the first region 302-1 on the plane of the substrate and the front projection of the second region 302-2 on the plane of the substrate may overlap with the front projection of the active layer 304 on the plane of the substrate, and the front projection of the third region 302-3 on the plane of the substrate may not overlap with the front projection of the active layer 304 on the plane of the substrate.

(14) A second insulating layer pattern is formed. Forming the second insulating layer pattern may include: a second insulating film is deposited on the side of the substrate 40 where the aforementioned patterns are formed, and the second insulating film is patterned by a patterning process to form a second insulating layer pattern on the side of the second conductive layer pattern remote from the substrate 40, and the second insulating layer pattern may include a plurality of first via holes K1 as shown in fig. 7.

The second insulating film within the first via K1 is etched away and exposes a portion of the surface of the second electrode 302 on a side away from the substrate 40, the first via K1 being configured such that a subsequently formed first electrode is connected to the second electrode 302 via the via. The orthographic projection of the first via K1 on the plane of the substrate may be located within the orthographic projection of the second pole 302 on the plane of the substrate. For example, the orthographic projection of the first via K1 on the plane of the substrate may be located within the orthographic projection of the third region 302-3 on the plane of the substrate.

In an exemplary embodiment, the first via K1 may be a circular hole, an elliptical hole, a rectangular hole, a hexagonal hole, or the like.

(15) And forming a third conductive layer pattern. Forming the third conductive layer pattern may include: a third conductive film is deposited on the side of the substrate 40 where the aforementioned patterns are formed, and is patterned by a patterning process to form a third conductive layer pattern on the side of the second insulating layer pattern remote from the substrate 40, and the third conductive layer pattern may include at least a plurality of first electrodes 10, as shown in fig. 8.

As shown in fig. 8, the front projection of the first electrode 10 on the plane of the substrate 40 does not overlap with the front projection of the data line DL on the plane of the substrate 40. The first electrode 10 may include a first pixel electrode 111 and a second pixel electrode 112. The first pixel electrode 111 and the second pixel electrode 112 may be located at different first sub-pixels P1, and in the embodiment of the present disclosure, the first sub-pixel P1 is taken as an example of a blue sub-pixel. The first pixel electrode 111 has a first storage capacitance with a second electrode opposite thereto, and the second pixel electrode 112 has a second storage capacitance with a second electrode opposite thereto. As described above, in the first direction X, a spacer is present between two adjacent touch sensing blocks, and the front projection of the first pixel electrode 111 on the plane of the substrate 40 and the front projection of the spacer on the plane of the substrate 40 at least partially overlap. There is no overlap between the orthographic projection of the second pixel electrode 112 on the plane of the substrate 40 and the orthographic projection of the spacer on the plane of the substrate 40. The area of the orthographic projection of the first pixel electrode 111 on the plane of the substrate 40 may be larger than the area of the orthographic projection of the second pixel electrode 112 on the plane of the substrate 40.

As shown in fig. 8, the first pixel electrode 111 may include a compensation portion 113, where the front projection of the compensation portion 113 on the plane of the array substrate may at least partially overlap with the front projection of the subsequently formed spacer on the plane of the array substrate, and the front projection of the compensation portion 113 on the plane of the array substrate and the front projection of the subsequently formed second electrode on the plane of the array substrate at least partially overlap. The compensation part 113 is configured to compensate for a capacitance difference between the first storage capacitance and the second storage capacitance.

The area S of the overlapping portion between the orthographic projection of the compensation portion 113 on the plane of the array substrate and the orthographic projection of the subsequently formed second electrode on the plane of the array substrate may be calculated by the following equation:

S＝Cd/εδ

wherein C is an absolute value of a difference between the first storage capacitor and the second storage capacitor, δ=1/4 pi K, wherein ε is a dielectric constant of a medium between the first pixel electrode and the second electrode, K is an electrostatic force constant, and d is a distance between the first pixel electrode and the second electrode along a thickness direction of the array substrate.

In an exemplary embodiment, the first pixel electrode 111 has a first storage capacitance between the second electrode opposite thereto, and the second pixel electrode 112 has a second storage capacitance between the second electrode opposite thereto, and an absolute value of a difference between the first storage capacitance and the second storage capacitance is less than or equal to 4% of a smaller capacitance of the first storage capacitance and the second storage capacitance.

In an exemplary embodiment, the front projection of the first pixel electrode 111 on the plane of the substrate 40 and the front projection of the second electrode on the plane of the substrate 40 have a first overlapping area, the front projection of the second pixel electrode 112 on the plane of the substrate 40 and the front projection of the second electrode on the plane of the substrate 40 have a second overlapping area, and the second overlapping area has a second overlapping area, and an absolute value of a difference between the first overlapping area and the second overlapping area is less than or equal to 4% of a smaller area of the first overlapping area and the second overlapping area.

(16) And forming a third insulating layer pattern. Forming the third insulating layer pattern may include: a third insulating film is deposited on the side of the substrate 40 where the aforementioned patterns are formed, and the third insulating film is patterned by a patterning process to form a third insulating layer pattern on the side of the third conductive layer pattern away from the substrate 40, and the third insulating layer pattern may include at least a plurality of second vias K2, as shown in fig. 9. The second insulating film and the third insulating film in the second via K2 are etched away, and a portion of the surface of the touch signal line 102 on the side far away from the substrate 40 is exposed, and the second via K2 is configured such that a subsequently formed second electrode (touch electrode) is connected to the touch signal line 102 through the via. As shown in fig. 9, the front projection of the second via K2 on the plane of the substrate 40 and the front projection of the touch signal line 102 on the plane of the substrate 40 at least partially overlap, and for example, the front projection of the second via K2 on the plane of the substrate 40 may be located within the front projection of the touch signal line 102 on the plane of the substrate 40. By way of example, the second via K2 may be a circular hole, an elliptical hole, a rectangular hole, a hexagonal hole, or the like.

In an exemplary embodiment, the material of the third insulating film may be an organic material. The organic material may be any one or more of epoxy resin, phenolic resin, urea resin, melamine formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, etc.

(17) And forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: a fourth conductive film is deposited on the side of the substrate 40 where the aforementioned patterns are formed, and is patterned by a patterning process to form a fourth conductive layer pattern on the side of the third insulating layer pattern remote from the substrate 40, which may include at least a plurality of second electrodes 20, as shown in fig. 10. The plurality of second electrodes 20 may include a first common electrode 211 and a second common electrode 212.

As shown in fig. 10, the second electrode 20 may have a plurality of slits 201, and the plurality of slits 201 may be arranged at intervals in the first direction X and extend in the second direction Y. The array substrate may include a plurality of touch sensing blocks 101 arranged at intervals, and the touch sensing blocks 101 may include a plurality of touch electrodes. In the first direction X, a spacer 104 exists between two adjacent touch sensing blocks 101. For example, the spacer 104 may be located at the first subpixel P1. The first common electrode 211 includes two portions separated by a spacer 104. In the embodiment of the present disclosure, the sub-pixel where the first common electrode 211 is located may be referred to as a compensation sub-pixel. The sub-pixel where the second common electrode 212 is located may be referred to as a reference sub-pixel, and the compensation sub-pixel and the reference sub-pixel belong to the first sub-pixel. The compensation sub-pixel may include a first pixel electrode 111 and a first common electrode 211 disposed opposite to each other, and the reference sub-pixel may include a second pixel electrode 112 and a second common electrode 212 disposed opposite to each other, and both the first common electrode 211 and the second common electrode 212 are multiplexed as touch electrodes.

In the embodiment of the present disclosure, the second electrodes of all the sub-pixels may be multiplexed as touch electrodes, and the plurality of touch electrodes located in the same touch sensing block 101 may be an integral structure connected to each other. In the display stage of the touch display device, the array substrate may provide a common electrode signal to the second electrode 20 through the touch signal line 102, so that the entire touch display device realizes a display function, and in the touch stage of the touch display device, the array substrate may receive a touch signal detected by the second electrode 20 by using the touch signal line 102, so that the entire touch display device realizes a touch function.

As shown in fig. 10, the first pixel electrode 111 may include a compensation portion 113, where an orthographic projection of the compensation portion 113 on a plane of the array substrate may at least partially overlap with an orthographic projection of the spacer 104 on the plane of the array substrate, and an orthographic projection of the compensation portion 113 on the plane of the array substrate and an orthographic projection of the first common electrode 211 on the plane of the array substrate at least partially overlap. The compensation part 113 is configured to compensate for a capacitance difference between the first storage capacitance and the second storage capacitance.

In an exemplary embodiment, the material of the fourth conductive layer may be a transparent conductive oxide material, and the transparent conductive oxide material may include Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The fourth conductive layer may be a single layer structure, or a multi-layer composite structure such as ITO/Al/ITO, for example.

In the array substrate, because the second electrode is multiplexed into the touch electrode, the plurality of touch electrodes are combined into the touch sensing block, and a reserved interval is needed between the adjacent touch sensing blocks, the part of the second electrode at the interval can be removed, so that a sub-pixel where the second electrode of the removed part is located, and storage capacitance difference exists between the sub-pixel and other sub-pixels displaying the same color light, and the display device has the problem of displaying dark lines due to the storage capacitance difference.

As can be seen from the structure and the preparation process of the array substrate according to the foregoing embodiments, the array substrate according to the exemplary embodiment of the present disclosure may compensate for the overlapping area between the first pixel electrode and the first common electrode opposite thereto by providing the compensation portion on the first pixel electrode, and thus may compensate for the storage capacitance between the first pixel electrode and the first common electrode opposite thereto, so that the problem of displaying dark lines in the existing array substrate may be solved.

The embodiment of the disclosure also provides a touch display device. The touch display device includes the array substrate according to any of the foregoing embodiments. The touch display device may be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, navigator and any other product or component with touch display function. The embodiments of the present disclosure are not limited in this regard.

Although the embodiments of the present invention are described above, the embodiments are only used for facilitating understanding of the present invention, and are not intended to limit the present invention. It should be noted that the above-described examples or implementations are merely exemplary and not limiting. Accordingly, the present disclosure is not limited to what has been particularly shown and described herein. Various modifications, substitutions, or omissions may be made in the form and details of the implementations without departing from the scope of the disclosure.

Claims

1. An array substrate is characterized by comprising a display area, wherein the display area comprises a plurality of first sub-pixels, the first sub-pixels are configured to emit light rays of a first color, and the first color is one of three primary colors;

2. The array substrate of claim 1, wherein a first storage capacitance is provided between the first pixel electrode and the first common electrode, a second storage capacitance is provided between the second pixel electrode and the second common electrode, and an absolute value of a difference between the first storage capacitance and the second storage capacitance is less than or equal to 4% of a smaller capacitance of the first storage capacitance and the second storage capacitance.

3. The array substrate of claim 2, wherein the first pixel electrode includes a compensation portion having a front projection on a plane of the array substrate at least partially overlapping with a front projection of the first common electrode on the plane of the array substrate, the compensation portion configured to compensate for a difference between the first storage capacitor and the second storage capacitor.

4. The array substrate of claim 3, wherein an area where the orthographic projection of the compensation portion on the plane of the array substrate and the orthographic projection of the first common electrode on the plane of the array substrate overlap is denoted as S, and S satisfies equation (1):

S＝Cd/εδ (1)

5. The array substrate of any one of claims 1 to 4, wherein the display region includes a substrate and first, second, third and fourth conductive layers sequentially located at one side of the substrate in a plane perpendicular to the array substrate;

6. The array substrate of claim 5, wherein the display area further comprises a plurality of data lines and at least one touch signal line on one side of the substrate; the plurality of data lines and the at least one touch signal line are all arranged at intervals along a first direction and extend along a second direction, wherein the first direction and the second direction are crossed.

7. The array substrate of claim 6, wherein the at least one touch signal line and the plurality of data lines are located on the same conductive layer.

8. The array substrate of claim 7, wherein the at least one touch signal line is located in the second conductive layer.

9. The array substrate of claim 6, wherein a line width of the touch signal line is greater than a line width of the data line.

10. The array substrate of claim 6, wherein the display region further comprises a second insulating layer between the second conductive layer and the third conductive layer, and a third insulating layer between the third conductive layer and the fourth conductive layer in a plane perpendicular to the array substrate; the third insulating layer is provided with at least one via hole;

11. The array substrate of claim 6, wherein the plurality of data lines includes a first data line, a second data line, and a third data line sequentially arranged along the first direction; a first interval along the first direction is arranged between the first data line and the second data line, a second interval along the first direction is arranged between the second data line and the third data line, and the first interval is larger than the second interval;

12. The array substrate of claim 11, wherein the orthographic projection of the first pixel electrode on the plane of the array substrate is located between the orthographic projection of the first data line on the plane of the array substrate and the orthographic projection of the second data line on the plane of the array substrate.

13. The array substrate of claim 6, wherein the compensation sub-pixel further comprises at least one transistor, the at least one transistor comprising a first pole, a second pole, a gate electrode, and an active layer; the grid electrode is positioned on the first conductive layer; the first pole and the second pole are both located in the second conductive layer, and the active layer is located between the first conductive layer and the second conductive layer.

14. The array substrate of claim 13, wherein the first pole and the data line are an integral structure connected to each other.

15. A touch display device comprising the array substrate according to any one of claims 1 to 14.