CN117832162A - Semiconductor structure preparation method and semiconductor structure - Google Patents
Semiconductor structure preparation method and semiconductor structure Download PDFInfo
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- CN117832162A CN117832162A CN202211179279.5A CN202211179279A CN117832162A CN 117832162 A CN117832162 A CN 117832162A CN 202211179279 A CN202211179279 A CN 202211179279A CN 117832162 A CN117832162 A CN 117832162A
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- H10B12/00—Dynamic random access memory [DRAM] devices
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Abstract
The present disclosure relates to a semiconductor structure manufacturing method and a semiconductor structure, the semiconductor structure manufacturing method including: providing a substrate; forming a target bit line pillar on the substrate; forming a first dielectric layer, wherein the first dielectric layer covers the surface of the target bit line stand column and the surface of the substrate; forming a solid target phase-changeable layer on the side wall of the first dielectric layer, wherein the target phase-changeable layer is used for sublimating and forming a target gap under the treatment of a preset heating sublimation process; forming a second dielectric layer, wherein the second dielectric layer covers the side wall of the target phase-changeable layer; and forming a target conductive plug between the side walls of the adjacent second dielectric layers. The target gap formed by the preparation method of the semiconductor structure can better reduce the parasitic capacitance of the device and improve the overall performance of the memory.
Description
Technical Field
The disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same.
Background
The Memory is a Memory unit for storing programs and various data information, and is classified into a ROM (Read-Only Memory) and a RAM (Random Access Memory ) according to the type of use of the Memory, and is classified into an SRAM (Static RAM) and a DRAM (Dynamic RAM) according to the operating principle of the Memory unit, and the DRAM has advantages of high integration, low power consumption, low price, and the like as compared with the SRAM, so that it is widely used in a large-capacity Memory.
However, in the manufacturing process of the memory, as the process nodes are continuously reduced, the memory has problems of increased power consumption and parasitic capacitance, and thus, a process method for manufacturing the memory is needed to improve the overall performance of the memory.
Disclosure of Invention
Based on the above, the present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure, which can effectively reduce power consumption of a memory, reduce parasitic capacitance of the memory, and increase operation speed thereof, so as to improve overall performance of the memory.
According to various embodiments of the present disclosure, there is provided in one aspect a semiconductor structure manufacturing method, including: providing a substrate; forming a target bit line pillar on a substrate; forming a first dielectric layer, wherein the first dielectric layer covers the surface of the target bit line upright post and the surface of the substrate; forming a solid target phase-changeable layer on the side wall of the first dielectric layer, wherein the target phase-changeable layer is used for sublimating and forming a target gap under the treatment of a preset heating sublimation process; forming a second dielectric layer, wherein the second dielectric layer covers the side wall of the target phase-changeable layer; and forming a target conductive plug between the side walls of the adjacent second dielectric layers.
In the method for manufacturing a semiconductor structure in the above embodiment, after forming the target bit line pillar in the substrate, forming the first dielectric layer on the outer surface of the target bit line pillar, then forming the solid target phase-changeable layer on the sidewall of the first dielectric layer, and forming the target gap at the position where the solid target phase-changeable layer is located by sublimating when the preset temperature-raising sublimation process is performed. In the manufacturing process of the memory in the prior art, in order to form the target gap, a sacrificial layer is formed at the position of the target gap in advance, and an etching selection ratio is arranged between the sacrificial layer and the dielectric layer contacted with the sacrificial layer, so that the adjacent dielectric layers are not damaged as much as possible when the sacrificial layer is etched to form the gap, but the specific value of the etching selection ratio can influence the etching effect, the incomplete removal of the sacrificial layer or the damage of the dielectric layer is easily caused, so that the device is invalid, and when the surface area of the sacrificial layer is too small and the longitudinal depth is too deep, the long processing time for removing the sacrificial layer is caused, and the efficiency of semiconductor preparation is reduced. The preparation method of the semiconductor structure adopts the solid target phase-changeable layer, can completely sublimate and form a target gap under the preset heating sublimation process, does not need to utilize chemical reactions such as etching to remove the target phase-changeable layer, and can avoid the chemical reactions of the first dielectric layer and the second dielectric layer in the preset heating sublimation process, thereby avoiding the problem that the adjacent first dielectric layer and the adjacent second dielectric layer are damaged when the gap is formed by the chemical reactions in the prior art, namely avoiding the occurrence of the failure condition of a device; in addition, a solid target phase-changeable layer is sublimated under a preset heating sublimation process to form a target gap, so that the problem of overlong processing time caused by removing the sacrificial layer by etching is solved, and the residue of the target phase-changeable layer material at the bottom of the target gap is avoided. Therefore, the target gap formed by the semiconductor structure preparation method can reduce parasitic capacitance of the device better and improve the overall performance of the memory.
According to some embodiments of the present disclosure, the target phase-changeable layer comprises a first phase-changeable layer, and the target gap comprises a first sub-gap; forming a solid target phase-changeable layer on the side wall of the first dielectric layer, including: forming an initial sacrificial layer on the side wall of the first dielectric layer; converting the initial sacrificial layer into a solid first phase-changeable layer by adopting a preset material conversion process, wherein the solid first phase-changeable layer is used for sublimating and forming a first sub-gap under the treatment of a preset heating sublimation process; forming an intermediate sacrificial layer on the side wall of the solid first phase-changeable layer, wherein the material of the intermediate sacrificial layer is the same as that of the initial sacrificial layer; the intermediate sacrificial layer and the solid first phase-changeable layer form a target phase-changeable layer.
According to some embodiments of the present disclosure, after forming the target conductive plug, treating the solid first phase-changeable layer with a preset temperature-rising sublimation process to sublimate and form a first sub-gap; or before forming the second dielectric layer, treating the solid first phase-changeable layer by adopting a preset heating sublimation process to sublimate the solid first phase-changeable layer and form a first sub-gap.
According to some embodiments of the present disclosure, the target gap includes a second sub-gap; the method for preparing the semiconductor structure further comprises the following steps: after forming the target conductive plug and the first sub-gap, converting the intermediate sacrificial layer into a solid second phase-changeable layer by adopting a preset material conversion process; and processing the solid second phase-changeable layer by adopting a preset heating sublimation process to sublimate the solid second phase-changeable layer and form a second sub-gap.
According to some embodiments of the present disclosure, after forming the target conductive plug and the first sub-gap, forming a capping layer that covers a top surface of the first dielectric layer, a top surface of the second dielectric layer, a top surface of the target conductive plug, and a top portion of the target gap; or after forming the second sub-gap, forming a cover layer, wherein the cover layer covers the top surface of the first dielectric layer, the top surface of the second dielectric layer, the top surface of the target conductive plug and the top of the target gap.
According to some embodiments of the present disclosure, the preset elevated temperature sublimation process includes a preset inert gas atmosphere, and the temperature range is 90 ℃ -250 ℃; the material of the target phase-changeable layer comprises ammonium hexafluorosilicate.
According to some embodiments of the present disclosure, the preset material conversion process includes a preset inert gas atmosphere, and the temperature range is: the flow rate of hydrofluoric acid is 10sccm-150sccm, and the flow rate of ammonia is 10sccm-150sccm at 25-45 ℃.
According to some embodiments of the present disclosure, a second dielectric layer is formed, the second dielectric layer covering sidewalls of the target phase-changeable layer; and forming a target conductive plug between sidewalls of adjacent second dielectric layers, comprising: forming a second dielectric material layer, wherein the second dielectric material layer covers the surface of the first dielectric layer and the surface of the target phase-changeable layer; forming a third dielectric material layer on the surface of the second dielectric material layer; etching back the second dielectric material layer and the third dielectric material layer to expose the top surface of the first dielectric layer and the surface of part of the substrate, wherein the second dielectric material layer reserved on the side wall of the target bit line upright post and the surface of the first dielectric layer forms the second dielectric layer, and the third dielectric material layer reserved on the second dielectric layer forms the third dielectric layer; and forming a conductive plug upright post between the adjacent third dielectric layers, wherein the conductive plug upright post and the third dielectric layers on the side walls of the conductive plug upright post form a target conductive plug.
According to some embodiments of the present disclosure, the gaps between adjacent third dielectric layers form an initial conductive plug trench; forming a conductive plug pillar between adjacent third dielectric layers, further comprising: etching the bottom of the initial conductive plug groove to form a target conductive plug groove, wherein the minimum width of the bottom of the target conductive plug groove is larger than the maximum distance between the side walls of the adjacent third dielectric layers; and forming a conductive plug upright post in the target conductive plug groove.
According to some embodiments of the present disclosure, forming a conductive plug stud within a target conductive plug trench includes: depositing a conductive plug material layer, wherein the conductive plug material layer at least fills the target conductive plug groove; and etching back the conductive plug material layer, wherein the conductive plug material layer reserved in the target conductive plug groove forms a conductive plug upright post, and the top surface of the conductive plug upright post is lower than the top surface of the target bit line upright post.
According to some embodiments of the present disclosure, forming a target bit line pillar on top of a substrate includes: forming a plurality of discrete bit line contact layers on a substrate, wherein the bit line contact layers are in contact connection with the substrate below the bit line contact layers, the bottom surface of the bit line contact layers is lower than the top surface of the substrate, a barrier layer, a bit line conducting layer and a bit line protecting layer are sequentially formed on the top of the bit line contact layers, and the stacked bit line contact layers, the barrier layer, the bit line conducting layer and the bit line protecting layer form a target bit line upright post; or forming a plurality of discrete etching stop layers on the substrate, wherein the etching stop layers are in contact connection with the substrate below the etching stop layers, a blocking layer, a bit line conducting layer and a bit line protecting layer are sequentially formed on the top of the etching stop layers, and the stacked etching stop layers, blocking layers, bit line conducting layers and bit line protecting layers form target bit line stand columns.
According to some embodiments of the present disclosure, another aspect of the present disclosure provides a semiconductor structure including a substrate, a target bit line pillar, a first dielectric layer, a target phase-changeable layer, a second dielectric layer, and a target conductive plug; the target bit line upright post is positioned on the substrate; the first dielectric layer covers the surface of the target bit line upright post and the surface of the substrate; the target phase-changeable layer is positioned on the side wall of the first dielectric layer and is used for sublimating and forming a target gap under the treatment of a preset heating sublimation process; the second dielectric layer covers the side wall of the target phase-changeable layer; the target conductive plugs are positioned between the side walls of the adjacent second dielectric layers.
In the semiconductor structure in the above embodiment, the outer surface of the target bit line pillar is covered with the first dielectric layer, the second dielectric layer at least partially surrounds the first dielectric layer, the target phase-changeable layer is arranged between the first dielectric layer and the second dielectric layer, when the preset heating sublimation process is executed, the target phase-changeable layer can be completely sublimated to form the target gap, and the parasitic capacitance of the device can be reduced due to the existence of the target gap.
According to some embodiments of the present disclosure, the target gap includes a first sub-gap; the target phase-changeable layer comprises a first phase-changeable layer and an intermediate sacrificial layer which are sequentially overlapped from inside to outside; the first phase-changeable layer surrounds the first dielectric layer; the intermediate sacrificial layer is positioned between the second dielectric layer and the first phase-changeable layer; the first phase-changeable layer is used for sublimating and forming a first sub-gap under the preset heating sublimation process treatment.
According to some embodiments of the present disclosure, the target gap further comprises a second sub-gap; the middle sacrificial layer is converted into a solid second phase-changeable layer under the treatment of a preset material conversion process; the second phase-changeable layer is used for sublimating and forming a second sub-gap under the preset heating sublimation process treatment.
According to some embodiments of the present disclosure, a target conductive plug includes:
the third dielectric layer covers the side wall of the second dielectric layer;
and the conductive plug upright posts are positioned between the side walls of the adjacent third dielectric layers and in target conductive plug grooves, and the target conductive plug grooves are formed in the substrate below the space defined by the side walls of the adjacent third dielectric layers.
According to some embodiments of the present disclosure, the bottom surface of the conductive plug stud is lower than the highest top surface of the substrate; and the top surface of the conductive plug pillar is lower than the top surface of the target bit line pillar.
According to some embodiments of the present disclosure, the minimum width of the bottom of the conductive plug pillar is greater than the maximum spacing between the sidewalls of adjacent third dielectric layers.
According to some embodiments of the present disclosure, a semiconductor structure includes a target gap between a first dielectric layer and a second dielectric layer, and the target gap is formed by a target phase-changeable layer.
According to some embodiments of the present disclosure, the semiconductor structure further includes a capping layer covering a top surface of the first dielectric layer, a top surface of the second dielectric layer, a top surface of the target conductive plug, and a top portion of the target gap.
According to some embodiments of the present disclosure, the target bit line pillar includes a bit line contact layer, a barrier layer, a bit line conductive layer, and a bit line protection layer, which are sequentially stacked, a bottom surface of the bit line contact layer being lower than a top surface of the substrate; or the target bit line column comprises an etching stop layer, a blocking layer, a bit line conducting layer and a bit line protecting layer which are sequentially laminated.
According to some embodiments of the present disclosure, the preset elevated temperature sublimation process includes a preset inert gas atmosphere, and the temperature range is 90 ℃ -250 ℃; the material of the target phase-changeable layer comprises ammonium hexafluorosilicate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a cross-sectional view of a semiconductor structure according to one embodiment of the present disclosure;
fig. 2 shows a cross-sectional view of a semiconductor structure provided in accordance with another embodiment of the present disclosure;
fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
fig. 4-21 are schematic cross-sectional views of structures obtained at various steps in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.
FIG. 22 is a schematic cross-sectional view of a semiconductor structure according to one embodiment of the present disclosure;
fig. 23-26 are schematic cross-sectional views of semiconductor structures provided for further embodiments of the present disclosure;
fig. 27 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present disclosure.
Reference numerals illustrate:
100. a substrate; 101. an active region; 102. a first isolation layer; 103. a target bit line column; 104. a bit line contact layer; 105. a second isolation layer; 106. an etch stop layer; 107. a barrier layer; 108. a bit line conductive layer; 109. a bit line protection layer; 110. a first dielectric layer; 111. an initial sacrificial material layer; 112. an initial sacrificial layer; 113. a first phase-changeable layer; 114. an intermediate sacrificial material layer; 115. an intermediate sacrificial layer; 116. a target phase-changeable layer; 117. a second dielectric material layer; 118. a third dielectric material layer; 119. a second dielectric layer; 120. a third dielectric layer; 121. a target conductive plug trench; 122. a conductive plug material layer; 123. a conductive plug pillar; 124. a first sub-gap; 125. a second phase-changeable layer; 126. a second sub-gap; 127. a target gap; 128. a cover layer; 129. a target conductive plug.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. Note that the mutual insulation between the two described in the embodiments of the present disclosure includes, but is not limited to, the presence of one or more of an insulating material, an insulating breath, a gap, etc. between the two.
Referring to fig. 1 and 2, the memory is a memory unit for storing programs and various data information, and can be divided into a ROM and a RAM according to the type of use of the memory, and the RAM is divided into an SRAM and a DRAM according to the working principle of the memory unit, and the DRAM has advantages of high integration, low power consumption, low price, and the like compared with the SRAM, so that the memory is commonly used in a large-capacity memory. In one embodiment, the basic memory cell in a DRAM is composed of two elements, a transistor and a capacitor, the transistor being used to charge or discharge the capacitor, the charging or discharging being accomplished through a word line and a bit line. In the prior art manufacturing process for the memory, a method of forming a gap between dielectric layers near the side wall of the bit line pillar is adopted to reduce the parasitic capacitance of the device. However, the existing method generally adopts to deposit the sacrificial layer at the position where the gap is formed in advance, then remove the sacrificial layer by wet etching to form the gap, and set the etching selectivity before etching, but the final etching effect is easily affected by the method of setting the etching selectivity because the exposed surface area of the sacrificial layer on the chip is too small. Referring to fig. 1, if the etching selectivity is too large or the selectivity is not good, the dielectric layer may be damaged, referring to fig. 2, if the etching selectivity is too small, the sacrificial layer is removed incompletely, and the sacrificial layer material may remain at the bottom of the gap, which may cause the failure of the semiconductor device.
Therefore, the embodiment of the disclosure provides a semiconductor structure preparation method and a semiconductor structure, so as to better reduce parasitic capacitance of a device and reduce power consumption to improve the overall performance of a memory.
As an example, referring to fig. 3, the present disclosure provides a semiconductor structure manufacturing method, including:
step S2: providing a substrate;
step S4: forming a target bit line column on the top of the substrate;
step S6: forming a first dielectric layer, wherein the first dielectric layer covers the surface of the target bit line upright post and the surface of the substrate;
step S8: forming a solid target phase-changeable layer on the side wall of the first dielectric layer, wherein the target phase-changeable layer is used for sublimating and forming a target gap under the treatment of a preset heating sublimation process;
step S10: forming a second dielectric layer, wherein the second dielectric layer covers the side wall of the target phase-changeable layer; and forming a target conductive plug between the side walls of the adjacent second dielectric layers.
In step S2 and step S4, referring to step S2 in fig. 3, step S4 in fig. 3, and fig. 4, a plurality of active regions 101 are arranged in the substrate 100 at intervals, and a first isolation layer 102 is further included between adjacent active regions 101 in the substrate 100, where the first isolation layer 102 is used for isolating the active regions 101, and a material of the first isolation layer 102 is an insulating material, and specifically, a material of the first isolation layer 102 may be silicon dioxide; the first isolation layer 102 may be formed by HDP-CVD (High Density Plasma-Chemical Vapor Deposition, high density plasma chemical vapor deposition) or the like.
As an example, the substrate 100 may be formed using a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 100 may have a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, and also for example, the substrate 100 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art may select the type of substrate 100 based on the type of transistor formed on the substrate 100, and thus the type of substrate 100 should not limit the scope of the present disclosure.
In step S6, referring to step S6 and fig. 5 in fig. 3, the first dielectric layer 110 covers the surface of the target bit line pillar 103 and the surface of the substrate 100, the surface of the target bit line pillar 103 includes the top surface and the sidewall of the target bit line pillar 103, specifically, the material of the first dielectric layer 110 may be silicon nitride, the first dielectric layer 110 may be formed by one or more of ALD (Atomic Layer Deposition ), LPCVD (Low Pressure Chemical Vapor Depositio, low pressure chemical vapor deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition ), and the atomic layer deposition may make the thickness of the obtained first dielectric layer 110 more uniform.
In step S8, referring to step S8, fig. 14 and fig. 15 in fig. 3, the target phase-changeable layer 116 can be sublimated under the preset temperature-raising sublimation process, the first dielectric layer 110 and the second dielectric layer 119 adjacent to the target phase-changeable layer 116 will not react chemically during sublimation to cause damage, and the target phase-changeable layer 116 can be completely removed during the preset temperature-raising sublimation process, so that no residue is caused at the bottom of the gap formed subsequently, and the parasitic capacitance of the device can be reduced better by the gap formed subsequently.
In step S10, referring to step S10, fig. 12 and fig. 14 in fig. 3, the material of the second dielectric layer 119 may be silicon nitride, the method for forming the second dielectric layer 119 may include one or more of ALD, LPCVD, PECVD, etc., the material of the target conductive plug 129 may include one or more of polysilicon, metal silicide, etc., and the top surface of the target conductive plug 129 is lower than the top surface of the target bit line pillar 103, so that the subsequently formed capping layer 128 (referring to fig. 18 and fig. 19) is more firm and is not prone to generate leakage at the corner.
In the method for manufacturing the semiconductor structure in the above embodiment, referring to fig. 14 and 17, after forming the target bit line pillar 103 in the substrate 100, forming the first dielectric layer 110 on the surface of the target bit line pillar 103 and the surface of the substrate, then forming the solid target phase-changeable layer 116 on the sidewall of the first dielectric layer 110, and forming the target gap 127 around the target phase-changeable layer 116 after forming the solid target phase-changeable layer 116 by using the solid target phase-changeable layer 116 to form the target conductive plug 129 at the position between the sidewalls of the adjacent second dielectric layers 119 when performing the preset temperature-raising sublimation process, the method for forming the target gap 127 does not cause damage to the first dielectric layer 110 contacting the target gap 127 or the second dielectric layer 119 formed later, and the target phase-changeable layer 116 can be completely sublimated in the preset temperature-raising sublimation process and does not remain at the bottom of the target gap 127. In the conventional memory manufacturing process, in order to form the target gap 127, a sacrificial layer is formed in advance at the position of the target gap 127, and an etching selection ratio is set between the sacrificial layer and the dielectric layer in contact with the sacrificial layer, so that the adjacent dielectric layers are not damaged as much as possible when the sacrificial layer is etched to form the gap, but a specific value of the etching selection ratio influences the etching effect, the incomplete removal of the sacrificial layer or the damage of the dielectric layer is easily caused, so that the device is invalid, and when the surface area of the sacrificial layer is too small and the longitudinal depth is too deep, the process time for removing the sacrificial layer is too long, and the efficiency of semiconductor preparation is reduced. The preparation method of the semiconductor structure adopts the solid target phase-changeable layer 116, which can be completely sublimated and form the target gap 127 under the preset temperature-rising sublimation process, chemical reactions such as etching are not needed to remove the target phase-changeable layer 116, and the first dielectric layer 110 and the second dielectric layer 119 can not generate chemical reactions in the preset temperature-rising sublimation process, so that the problem that the adjacent first dielectric layer 110 and the adjacent second dielectric layer 119 are damaged when gaps are formed by chemical reactions in the prior art is avoided, namely the occurrence of failure of a device is avoided; in addition, the target gap 127 is formed by adopting a method of sublimating the solid target phase-changeable layer 116 under a preset heating sublimation process, so that the problem of too long process time caused by etching to remove the sacrificial layer is solved, and the residue of the material of the target phase-changeable layer 116 is not caused at the bottom of the target gap 127. Therefore, the target gap 127 formed by the semiconductor structure preparation method can reduce parasitic capacitance of the device better and improve the overall performance of the memory.
As an example, forming the target bit line pillars on top of the substrate in step S4 includes the steps of:
step S41: forming a plurality of discrete bit line contact layers on the top of the substrate, wherein the bit line contact layers are in contact connection with the substrate below the bit line contact layers (such as an active region right below the bit line contact layers), and the bottom surfaces of the bit line contact layers are lower than the top surfaces of the substrate;
step S42: a barrier layer, a bit line conducting layer and a bit line protecting layer are sequentially formed on the top of the bit line contact layer, and the stacked bit line contact layer, the barrier layer, the bit line conducting layer and the bit line protecting layer form a target bit line stand column.
As an example, forming the target bit line pillars on top of the substrate in step S4 may further include the steps of:
step S41': forming a plurality of discrete etching stop layers on the substrate, wherein the etching stop layers are in contact connection with the substrate below the etching stop layers;
step S42': and forming a barrier layer, a bit line conducting layer and a bit line protecting layer on the top of the etching stop layer in sequence, wherein the stacked etching stop layer, the barrier layer, the bit line conducting layer and the bit line protecting layer form a target bit line stand column.
In step S41, referring to fig. 4, the target bit line pillar 103 includes a bit line contact layer 104, where the material of the bit line contact layer 104 is a conductive material, for example, polysilicon or SiGe, and the bottom surface of the bit line contact layer 104 is lower than the top surface of the substrate 100, so that the target bit line pillar 103 can better contact the active region 101, and further reduce the parasitic capacitance.
In step S42, referring to fig. 4, the target bit line pillar 103 includes a barrier layer 107, a bit line conductive layer 108 and a bit line protection layer 109, where the barrier layer 107 may be made of metal nitride, such as titanium nitride (TiN) or tantalum nitride (TaN), and the bit line conductive layer 108 may be made of low-resistance material such as Tungsten (tunesten) or Ruthenium (Ruthenium) to reduce resistance and increase the operation speed of the device. The preparation method of each portion of the target bit line pillar 103 belongs to common general knowledge of a person skilled in the art, and is not described herein.
In step S41 'and step S42', the target bit line pillar 103 includes an etch stop layer 106, a barrier layer 107, a bit line conductive layer 108, and a bit line protection layer 109, and the material of the etch stop layer 106 may be silicon nitride.
As an example, with continued reference to fig. 4, the substrate 100 may further include a second isolation layer 105, the second isolation layer 105 filling the region between the discrete bit line contact layers 104 for isolating the plurality of bit line contact layers 104; the material of the second isolation layer 105 may be silicon oxide or silicon nitride, etc.
As an example, referring to fig. 4, shallow trenches may be formed in the substrate 100 adjacent to the bit line contact layer 104, and the shallow trenches can enlarge the contact area between the target bit line pillars 103 and the substrate 100, thereby further reducing the parasitic capacitance of the device.
As an example, the target phase-changeable layer includes a first phase-changeable layer, and the target gap includes a first sub-gap; in step S6, a solid target phase-changeable layer is formed on a sidewall of the first dielectric layer, including the following steps:
step S61: forming an initial sacrificial layer on the side wall of the first dielectric layer;
step S62: converting the initial sacrificial layer into a solid first phase-changeable layer by adopting a preset material conversion process, wherein the solid first phase-changeable layer is used for sublimating and forming a first sub-gap under the treatment of a preset heating sublimation process;
step S63: forming an intermediate sacrificial layer on the side wall of the solid first phase-changeable layer, wherein the material of the intermediate sacrificial layer is the same as that of the initial sacrificial layer; the intermediate sacrificial layer and the solid first phase-changeable layer form a target phase-changeable layer.
In step S61, referring to fig. 6, the initial sacrificial layer 112 may be prepared by an ALD method, which enables the initial sacrificial layer 112 to have good thickness uniformity, and the material of the initial sacrificial layer 112 may be silicon oxide.
As an example, referring to fig. 5, in step S61, before forming the initial sacrificial layer 112 on the sidewall of the first dielectric layer 110, the method further includes: an initial sacrificial material layer 111 is formed on the outer surface of the first dielectric layer 110, the initial sacrificial material layer 111 is etched back, the top surface of the first dielectric layer 110 and a portion of the surface of the substrate 100 are exposed, and the initial sacrificial material layer 111 remaining on the sidewall of the target bit line pillar 103 (or the first dielectric layer 110) forms an initial sacrificial layer 112.
By way of example, the specific method employed in the etchback process in embodiments of the present disclosure may be a CMP (Chemical Mechanical Polishing, chemical mechanical polishing technique) process, an etching process, or the like.
In step S62, referring to fig. 7, the solid first phase-changeable layer 113 can be completely sublimated under the preset temperature-raising sublimation process, i.e. the first phase-changeable layer 113 is physically changed from the solid state to the gaseous state, the structure of the dielectric layer adjacent to the solid state is not damaged, and the solid first phase-changeable layer 113 is not remained at the bottom of the gap after the preset temperature-raising sublimation process is completed, thereby reducing the parasitic capacitance of the device. In addition, the process time can be shortened by adopting a preset heating sublimation process, and the semiconductor preparation efficiency can be improved.
In step S63, referring to fig. 9, the intermediate sacrificial layer 115 and the solid first phase-changeable layer 113 form the target phase-changeable layer 116, and the target phase-changeable layer 116 can form a gap under the preset heating sublimation process, so as to reduce parasitic capacitance of the device, reduce power consumption, and increase operation speed of the memory.
As an example, referring to fig. 8, before forming the intermediate sacrificial layer 115 on the sidewall of the solid first phase-changeable layer 113 in step S63, the method further includes: an intermediate sacrificial material layer 114 is formed on the outer surface of the solid first phase-changeable layer 113, the intermediate sacrificial material layer 114 is etched back, the top surface of the first dielectric layer 110 and a portion of the surface of the substrate 100 are exposed, and the intermediate sacrificial material layer 114 remaining on the sidewall of the target bit line pillar 103 (or the first phase-changeable layer 113) forms an intermediate sacrificial layer 115.
By way of example, the formation of the intermediate sacrificial material layer 114 may be formed using low temperature deposition ALD silicon oxide at a temperature of 25 c to 75 c, wherein the temperature is preferably 25 c to 60 c, in a temperature range that allows the formed ammonium hexafluorosilicate to remain solid and the intermediate sacrificial material layer 114, such as silicon oxide, encapsulates the ammonium hexafluorosilicate.
As an example, after forming the target conductive plug in step S10, the method further includes the steps of:
step S105: treating the solid first phase-changeable layer by adopting a preset heating sublimation process to sublimate the solid first phase-changeable layer and form a first sub-gap;
in other embodiments, before the second dielectric layer is formed in step S10, the solid first phase-changeable layer may be further processed by using a preset temperature-raising sublimation process, so as to sublimate and form the first sub-gap.
In step S105, referring to fig. 14 and 15, after forming the target conductive plug 129, the solid first phase-changeable layer 113 is processed by a preset temperature-raising sublimation process to sublimate and form the first sub-gap 124, and the process of forming the first sub-gap 124 does not damage the adjacent first dielectric layer 110, intermediate sacrificial layer 115 and second dielectric layer 119, and only the first phase-changeable layer 113 is physically changed from the solid state to the gaseous state; in other embodiments, referring to fig. 20 and 21, after forming the target phase-changeable layer 116 and before forming the second dielectric layer 119, a preset temperature-raising sublimation process may be further used to sublimate the solid first phase-changeable layer 113 to form the first sub-gap 124, and after forming the first sub-gap 124, the subsequent steps of forming the second dielectric layer 119 and other structures are the same as those in the embodiments of the disclosure.
As an example, the target gap includes a second sub-gap; after forming the target conductive plug and the first sub-gap in step S105, the method further includes the following steps:
step S106: converting the intermediate sacrificial layer into a solid second phase-changeable layer by adopting a preset material conversion process;
step S107: and processing the solid second phase-changeable layer by adopting a preset heating sublimation process to sublimate the solid second phase-changeable layer and form a second sub-gap.
In step S106, referring to fig. 16, the solid second phase-changeable layer 125 is made of the same material as the solid first phase-changeable layer, and the solid second phase-changeable layer 125 can be completely sublimated to form a gap under the preset heating sublimation process, so as to further increase the gap space, reduce parasitic capacitance, and improve the overall performance of the memory.
In step S107, referring to fig. 17, the solid second phase-changeable layer 125 is completely sublimated under the preset temperature-raising sublimation process, and a second sub-gap 126 is formed at the position where the solid second phase-changeable layer 125 is located, wherein the second sub-gap 126 and the first sub-gap 124 together form a target gap 127, and a physical change rather than a chemical change such as wet etching is adopted in the forming process of the target gap 127, so that the first dielectric layer 110 and the second dielectric layer 119 adjacent to the gap are prevented from being damaged, other materials remain at the bottom of the gap after the target gap 127 is formed, that is, the problem of device failure is avoided, parasitic capacitance is also reduced, the power consumption of the device is reduced, and the overall performance of the memory device is further improved.
As an example, after forming the target conductive plug, the first sub-gap, and the second sub-gap in step S107, the method further includes the steps of:
step S108: forming a covering layer, wherein the covering layer covers the top surface of the first dielectric layer, the top surface of the second dielectric layer, the top surface of the target conductive plug and the top of the target gap;
in other embodiments, after forming the target conductive plug and the first sub-gap, a capping layer may be formed, where the capping layer covers the top surface of the first dielectric layer, the top surface of the second dielectric layer, the top surface of the target conductive plug, and the top of the target gap.
In step 108, referring to fig. 18, after forming the target conductive plug 129, the first sub-gap 124 and the second sub-gap 126, a capping layer 128 is formed on the top of the structure, and the capping layer 128 is formed more firmly on the top of the device and is not prone to leakage at the corners because the target conductive plug 129 is not level with the top of the target bit line pillar 103; in other embodiments, referring to fig. 19, after forming the target conductive plug 129 and the first sub-gap 124, the capping layer 128 may be formed, where the target gap 127 in the device can also reduce the parasitic capacitance of the device.
As an example, the preset temperature-rising sublimation process includes a preset inert gas atmosphere, and the temperature ranges from 90 ℃ to 250 ℃, preferably from 110 ℃ to 210 ℃, specifically, the temperature of the preset inert gas atmosphere may be 90 ℃, 100 ℃, 150 ℃, 200 ℃, 220 ℃, 250 ℃, or the like; the material of the target phase-changeable layer 116 includes ammonium hexafluorosilicate.
As an example, referring to fig. 14, 16 and 17, the combination of the material used for the target phase-changeable layer, the temperature range used for the preset temperature-rising sublimation process and the gas atmosphere does not cause chemical or physical changes to the other structures except the first phase-changeable layer 113 and the second phase-changeable layer 125, and only the first phase-changeable layer 113 and the second phase-changeable layer 125 are completely changed from solid to gas when the preset temperature-rising sublimation process is performed, so that the first sub-gap 124 and the second sub-gap 126 are formed respectively. Therefore, the adoption of the preset heating sublimation process can protect the adjacent dielectric layers of the target gap 127 from being damaged, and avoid the failure of the device.
As an example, the preset material conversion process includes a preset inert gas atmosphere, and the temperature range is: 25-45 deg.c, with 30-40 deg.c being preferred. Specifically, the temperature of the preset inert gas atmosphere may be 25 ℃, 28 ℃,30 ℃, 35 ℃, 40 ℃, 45 ℃ or the like; the flow rate of the hydrofluoric acid is 10sccm to 150sccm, specifically, the flow rate of the hydrofluoric acid may be 10sccm, 30sccm, 50sccm, 70sccm, 100sccm, 150sccm, or the like; the flow rate of the ammonia gas is 10sccm to 150sccm, specifically, the flow rate of the ammonia gas may be 10sccm, 30sccm, 50sccm, 70sccm, 100sccm, 150sccm, or the like.
As an example, the initial sacrificial layer 112 is completely converted into the first phase-changeable layer 113 and the intermediate sacrificial layer 115 is completely converted into the second phase-changeable layer 125 in a temperature range of a predetermined material conversion process, and the physical states of the first phase-changeable layer 113 and the second phase-changeable layer 125 remain unchanged in the solid state.
As an example, in step S10, a second dielectric layer is formed, which covers the sidewalls of the target phase-changeable layer; and forming a target conductive plug between the side walls of the adjacent second dielectric layers, comprising the following steps:
step S101: forming a second dielectric material layer by adopting a deposition process; the second dielectric material layer covers the surface of the first dielectric layer and the surface of the target phase-changeable layer;
step S102: forming a third dielectric material layer on the surface of the second dielectric material layer;
step S103: etching back the second dielectric material layer and the third dielectric material layer to expose the top surface of the first dielectric layer and the surface of part of the substrate, wherein the second dielectric material layer reserved on the side wall of the target bit line upright post and the surface of the first dielectric layer forms the second dielectric layer, and the third dielectric material layer reserved on the second dielectric layer forms the third dielectric layer;
Step S104: and forming a conductive plug upright post between the adjacent third dielectric layers, wherein the conductive plug upright post and the third dielectric layers on the side walls of the conductive plug upright post form a target conductive plug.
In step S101, referring to fig. 10, a second dielectric material layer 117 is deposited on the surface of the first dielectric layer and the surface of the target phase-changeable layer, where the deposition method may be one or more of LPCVD, PECVD, ALD, etc.
In step S102, referring to fig. 11, the deposition method of the third dielectric material layer 118 may be one or more of LPCVD, PECVD, ALD, etc.
In step S103, referring to fig. 12, the second dielectric material layer 117 and the third dielectric material layer 118 are etched back, wherein the portions of the second dielectric material layer 117 and the third dielectric material layer 118 located on the top surface of the target bit line pillar 103 and the portion of the third dielectric material layer 118 located between the sidewall portions of the second dielectric material layer 117 and on the top surface of the substrate 100 are removed, so as to form a second dielectric layer 119 and a third dielectric layer 120, i.e., the second dielectric material layer remaining on the sidewall of the target bit line pillar and the surface of the first dielectric layer forms the second dielectric layer 119, and the third dielectric material layer remaining on the sidewall of the second dielectric layer 119 forms the third dielectric layer 120. Wherein the top surfaces of the second dielectric layer 119 and the third dielectric layer 120 are flush with the top surface of the target bit line pillar 103. The second dielectric layer 119 and the third dielectric layer 120 are located on the sidewalls of the target bit line pillar 103, and can protect the target bit line pillar 103 and define a structure of a conductive plug pillar 123 (see fig. 14) that is formed later.
As an example, the gaps between adjacent third dielectric layers form an initial conductive plug trench; before forming the conductive plug pillars between the adjacent third dielectric layers in step S104, the method further includes the following steps:
step S1041: etching the bottom of the initial conductive plug groove by adopting an etching process (such as a wet etching process) to form a target conductive plug groove, wherein the minimum width of the bottom of the target conductive plug groove is larger than the maximum distance between the side walls of the adjacent third dielectric layers;
step S1042: and forming a conductive plug upright post in the target conductive plug groove.
In step S1041, referring to fig. 12, the minimum width of the bottom of the target conductive plug trench 121 is larger than the maximum spacing between the sidewalls of the adjacent third dielectric layer 120, which can increase the contact area between the active region 101 and the target conductive plug 129 (referring to fig. 14), thereby improving the performance of the memory.
As an example, forming a conductive plug pillar in the target conductive plug trench in step S1042 includes the steps of:
step S10421: depositing a conductive plug material layer, wherein the conductive plug material layer at least fills the target conductive plug groove;
step S10422: and etching back the conductive plug material layer, wherein the conductive plug material layer reserved in the target conductive plug groove forms a conductive plug upright post, and the top surface of the conductive plug upright post is lower than the top surface of the target bit line upright post.
In step S10421, referring to fig. 13, the conductive plug material layer 122 is filled with at least the target conductive plug trench 121 (referring to fig. 12), and the conductive plug material layer 122 may be higher than the target conductive plug trench 121 and cover the top surface of the device structure.
In step S10422, referring to fig. 14, the top surface of the conductive plug pillar 123 is lower than the top surface of the target bit line pillar 103, so that the subsequently formed cap layer 128 (referring to fig. 18) is more firm and reduces the leakage at the corner.
As an example, referring to fig. 22, another aspect of the present disclosure provides a semiconductor structure including a substrate 100, a target bit line pillar 103, a first dielectric layer 110, a second dielectric layer 119, and a target conductive plug 129; the substrate 100 includes an active region 101 therein; the target bit line pillars 103 are located on the substrate 100, e.g., on top of the substrate 100 and electrically connected to the active regions 101 thereunder; the first dielectric layer 110 covers the surface of the target bit line pillars 103 and the surface of the substrate 100; the second dielectric layer 119 surrounds the first dielectric layer 110, and has a target phase-changeable layer 116 between the second dielectric layer 119 and the first dielectric layer 110, where the target phase-changeable layer 116 is used for sublimating and forming a target gap 127 (see fig. 25) under a preset heating sublimation process; the target conductive plugs 129 are located between the sidewalls of the adjacent second dielectric layer 119 and are electrically connected to the active region 101 thereunder.
As an example, referring to fig. 23, the semiconductor structure further includes a first isolation layer 102, a second isolation layer 105, and an etch stop layer 106. A first isolation layer 102 is further included between adjacent active regions 101 in the substrate 100, where the first isolation layer 102 is used to isolate the active regions 101, and a material of the first isolation layer 102 is an insulating material, specifically, a material of the first isolation layer 102 may be silicon dioxide; the substrate 100 surface may further form a second isolation layer 105, the second isolation layer 105 filling the region between the discrete bit line contact layers 104 for isolating the plurality of bit line contact layers 104; the material of the second isolation layer 105 may be silicon oxide or silicon nitride, etc.; the material of the etch stop layer 106 may be silicon nitride.
In the semiconductor structure in the above embodiment, the outer surface of the target bit line pillar 103 is covered with the first dielectric layer 110, the second dielectric layer 119 surrounds the first dielectric layer 110, the target phase-changeable layer 116 is formed between the first dielectric layer 110 and the second dielectric layer 119, when the preset temperature-raising sublimation process is performed, the target phase-changeable layer 116 can be completely sublimated to form the target gap 127, the parasitic capacitance of the device can be reduced due to the existence of the target gap 127, the conventional technology generally adopts a method for forming a sacrificial layer and etching to form the gap, therefore, the method needs to set an etching selection ratio, the setting of the etching selection ratio is poor, the problems of over-etching or insufficient etching are easily caused, and the like, and due to the requirement of the narrow and deep target gap 127, the process time required by the method for forming the gap by adopting chemical reactions such as etching is overlong, the target phase-changeable layer 116 between the first dielectric layer 110 and the second dielectric layer 119 is used for forming the target gap 127, the target gap 127 can be completely sublimated and formed when the preset temperature-raising sublimation process is performed, namely, the formation of the target gap 127 is not required to use the chemical reaction process, the adjacent layer 127 is not required to be formed, the whole power consumption is not damaged, the whole performance of the device is reduced, the parasitic capacitance of the device is better is reduced, and the performance of the device is reduced, and the parasitic capacitance is better is reduced, and the performance of the device is prepared, and the device is reduced.
As an example, referring to fig. 22 and 23, the target gap 127 includes a first sub-gap 124; the target phase-changeable layer 116 includes a first phase-changeable layer and an intermediate sacrificial layer 115 stacked in order from inside to outside; the first phase-changeable layer surrounds the first dielectric layer 110; the intermediate sacrificial layer 115 is located between the second dielectric layer 119 and the first phase-changeable layer; the first phase-changeable layer is used for sublimating and forming a first sub-gap 124 under the preset temperature-rising sublimation process, that is, the first phase-changeable layer is physically changed from a solid state to a gaseous state, the structure of a dielectric layer adjacent to the first phase-changeable layer is not damaged in the process, and the solid first phase-changeable layer is not remained at the bottom of the gap after the preset temperature-rising sublimation process is completed, so that the parasitic capacitance of the device is reduced. In addition, the process time can be shortened by adopting a preset heating sublimation process, and the semiconductor preparation efficiency can be improved.
As an example, referring to fig. 24 and 25, the target gap 127 further includes a second sub-gap 126; the intermediate sacrificial layer 115 is converted into a solid second phase-changeable layer 125 under a predetermined material conversion process; the second phase-changeable layer 125 is used for sublimating and forming a second sub-gap 126 under the preset heating sublimation process treatment, so as to further increase the gap space, reduce the parasitic capacitance and improve the overall performance of the memory.
As an example, referring to fig. 23, the target conductive plug 129 includes a conductive plug pillar 123 and a third dielectric layer 120, and the conductive plug pillar 123 is located between the adjacent second dielectric layers 119 and is electrically connected to the active region 101 thereunder; the third dielectric layer 120 is located between the second dielectric layer 119 and the conductive plug pillar 123, and may protect the target bit line pillar 103. In other words, the third dielectric layer covers the sidewall of the second dielectric layer; the conductive plug pillars are located between sidewalls of adjacent third dielectric layers and in the target conductive plug trench 121, the target conductive plug trench 121 is formed in the substrate below a space defined by the sidewalls of adjacent third dielectric layers, and a minimum width of a bottom of the target conductive plug trench is greater than a maximum spacing between the sidewalls of adjacent third dielectric layers.
As an example, the bottom surface of the conductive plug pillar 123 is lower than the highest top surface of the substrate 100 to increase the contact area between the active region 101 and the conductive plug pillar 123, improving the performance of the memory; and the top surface of the conductive plug pillar 123 is lower than the top surface of the target bit line pillar 103, so that the capping layer 128 (see fig. 26 and 27) is formed more firmly on the top of the device, and is not prone to leakage at the corners.
As an example, the minimum width of the bottom of the conductive plug pillar 123 is greater than the maximum spacing between the sidewalls of adjacent second dielectric layers 119 to further reduce parasitic capacitance and improve device performance.
As an example, referring to fig. 23 to 25, the target bit line pillar 103 includes a bit line contact layer 104, a barrier layer 107, a bit line conductive layer 108, and a bit line protection layer 109, which are sequentially stacked; the bit line contact layer 104 is in contact connection with the active region 101 below the bit line contact layer; the bottom surface of the bit line contact layer 104 is lower than the top surface of the substrate 100, so as to increase the contact area between the active region 101 and the bit line contact layer 104, and improve the performance of the memory. The target bit line pillars 103 may also be comprised of an etch stop layer 106, a barrier layer 107, a bit line conductive layer 108, and a bit line protection layer 109.
As an example, with continued reference to fig. 23, 24 and 25, the semiconductor structure includes a target gap 127, the target gap 127 being located between the first dielectric layer 110 and the second dielectric layer 119. Wherein the target gap 127 may be the first sub-gap 124 (as shown in fig. 23), and the target gap 127 may include the first sub-gap 124 and the second sub-gap 126 (as shown in fig. 25).
As an example, the target gap 127 is formed by a target phase-changeable layer.
As an example, referring to fig. 26 and 27, the semiconductor structure further includes a capping layer 128, where the capping layer 128 covers the top surface of the first dielectric layer 110, the top surface of the second dielectric layer 119, the top surface of the target conductive plug 129, and the top of the target gap 127. Referring to fig. 26, after forming the target conductive plug 129, the first sub-gap 124 and the second sub-gap 126, the capping layer 128 is formed, and the capping layer 128 is formed more firmly on the top of the device and is not prone to leakage at the corners because the target conductive plug 129 is not level with the top of the target bit line pillar 103; in other embodiments, referring to fig. 27, after forming the target conductive plug 129 and the first sub-gap 124, the capping layer 128 may be formed, where the target gap 127 in the device can also reduce the parasitic capacitance of the device.
As an example, the preset temperature-rising sublimation process includes a preset inert gas atmosphere, and the temperature ranges from 90 ℃ to 250 ℃, preferably from 110 ℃ to 210 ℃, specifically, the temperature of the preset inert gas atmosphere may be 90 ℃, 100 ℃, 150 ℃, 200 ℃, 220 ℃, 250 ℃, or the like; the material of the target phase-changeable layer 116 includes ammonium hexafluorosilicate.
As an example, the combination of the material used for the target phase-changeable layer, the temperature range used for the preset temperature rise sublimation process, and the gas atmosphere does not chemically or physically change other structures except the first phase-changeable layer 113 and the second phase-changeable layer 125, and only the first phase-changeable layer 113 and the second phase-changeable layer 125 are completely changed from a solid state to a gaseous state when the preset temperature rise sublimation process is performed, thereby being completely volatilized, forming the first sub-gap 124 and the second sub-gap 126, respectively. Therefore, the adoption of the preset heating sublimation process can protect the adjacent dielectric layers of the target gap 127 from being damaged, and avoid the failure of the device.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, although at least a portion of the steps in FIG. 1 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the steps or stages are performed is not necessarily sequential, and may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or steps.
In the semiconductor structure manufacturing method and the semiconductor structure, the first phase-changeable layer or the second phase-changeable layer is sublimated under the treatment of the preset heating sublimation process to form the target gap, so that parasitic capacitance of the device is reduced better, the target gap formed by the method is formed in a physical change mode instead of etching, damage to adjacent dielectric layers due to chemical reaction such as wet etching is avoided, the depth is too large due to the fact that the exposed top surface area of the position of the target gap is too small, material residues are caused to the bottom of the gap in the process of etching the gap, and the device manufacturing efficiency is improved. Therefore, the semiconductor structure prepared by the method disclosed by the invention avoids the problem of device failure, reduces the power consumption of the device and improves the operation speed of the device. In addition, as the bottom surface of the conductive plug stand column is lower than the top surface of the substrate, the contact area between the active area and the conductive plug stand column is increased, and the performance of the memory is further improved; the top surface of the conductive plug stand column is lower than the top surface of the target bit line stand column, so that a subsequently formed covering layer is firmer at the top of the device, and the electric leakage phenomenon is not easy to occur at the corner; and the bottom surface of the bit line contact layer is lower than the top surface of the substrate, so that the contact area between the active region and the bit line contact layer is increased, and the performance of the memory is further improved.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples merely represent several embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the disclosure. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.
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| CN202211179279.5A CN117832162A (en) | 2022-09-27 | 2022-09-27 | Semiconductor structure preparation method and semiconductor structure |
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| US7262444B2 (en) * | 2005-08-17 | 2007-08-28 | General Electric Company | Power semiconductor packaging method and structure |
| KR101950349B1 (en) * | 2012-12-26 | 2019-02-20 | 에스케이하이닉스 주식회사 | Method for gapfilling void―free polysilicon and mehto for fabricating semiconductor device using the same |
| US9425200B2 (en) * | 2013-11-07 | 2016-08-23 | SK Hynix Inc. | Semiconductor device including air gaps and method for fabricating the same |
| US10074639B2 (en) * | 2016-12-30 | 2018-09-11 | Texas Instruments Incorporated | Isolator integrated circuits with package structure cavity and fabrication methods |
| US10566530B2 (en) * | 2018-03-15 | 2020-02-18 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor devices |
| CN111180463A (en) * | 2020-01-03 | 2020-05-19 | 长江存储科技有限责任公司 | Three-dimensional memory and method of making the same |
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