CN117832086A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: forming a first epitaxial structure on a substrate, the first epitaxial structure comprising an opening region; forming an etching stop layer on a side of the first epitaxial structure away from the substrate; removing a portion of the etching stop layer located in the opening region; forming a side wall in the opening region corresponding to the side of the etching stop layer; etching the first epitaxial structure using the etching stop layer and the side wall as a mask to form an opening; and forming an electrode structure in the opening. The present invention can reduce the opening size of the semiconductor device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same.

Background technique

Semiconductor devices have important applications in modern electronic technology, and the corresponding performance requirements for semiconductor devices are becoming increasingly higher.

However, when manufacturing electrodes (such as gate electrodes) of existing semiconductor devices, the opening size is restricted by the process limit of the photolithography machine and cannot be further reduced, which makes the size of the gate electrode larger. The larger gate electrode size leads to a larger gate capacitance, which affects the switching speed of the semiconductor device and limits the application of the semiconductor device in the high-frequency field.

Summary of the invention

The invention provides a semiconductor device and a preparation method thereof, so as to reduce the opening size of the semiconductor device.

According to one aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

forming a first epitaxial structure on a substrate, wherein the first epitaxial structure comprises an opening region;

forming an etching stop layer on a side of the first epitaxial structure away from the substrate;

removing the portion of the etch stop layer located in the opening area;

forming a sidewall at the side of the opening area corresponding to the etch stop layer;

Using the etching stop layer and the sidewall as masks, etching the first epitaxial structure to form an opening;

An electrode structure is formed in the opening.

Optionally, forming a sidewall in the opening area includes:

Forming a spacer material layer on the entire surface, wherein the spacer material layer covers the etch stop layer and the first epitaxial structure exposed by removing the etch stop layer from the opening area;

The sidewall spacer is formed by etching the sidewall spacer material layer.

Optionally, the step of forming the sidewall material layer on the entire surface includes:

The thickness of the spacer material layer is determined according to the opening size corresponding to the first epitaxial structure and the final size of the semiconductor device.

Optionally, the etching stop layer includes a dielectric material layer;

Before forming the electrode structure in the opening, the method further includes:

The dielectric material layer and the sidewalls are removed.

Optionally, the material of the dielectric material layer includes silicon oxide, and the material of the sidewall spacer includes silicon nitride; or, the material of the dielectric material layer includes silicon nitride, and the material of the sidewall spacer includes silicon oxide.

Optionally, the etch stop layer comprises an epitaxial material layer;

The forming of the electrode structure in the opening comprises:

The electrode structure is formed to fill the opening and at least partially cover the epitaxial material layer.

Optionally, an etching selectivity ratio of the first epitaxial structure to the epitaxial material layer is greater than or equal to 5.

Optionally, the material of the epitaxial material layer includes aluminum nitride, and the material of the spacer includes silicon nitride or silicon oxide.

Optionally, before forming the sidewall in the opening area, the method further includes:

Etching a portion of the first epitaxial structure located in the opening region to form a sub-opening; wherein the sub-opening has a preset depth, and the preset depth is smaller than a depth of the opening corresponding to the first epitaxial structure;

The forming of a sidewall at a side of the opening area corresponding to the etch stop layer comprises:

A side wall is formed at a side of the sub-opening.

Optionally, the preset depth is less than or equal to half of the depth of the opening corresponding to the first epitaxial structure.

According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device is manufactured by the method for manufacturing a semiconductor device as described above.

The technical solution of the embodiment of the present invention adopts a method for preparing a semiconductor device, which includes forming a first epitaxial structure on a substrate, the first epitaxial structure including an opening area; forming an etch barrier layer on a side of the first epitaxial structure away from the substrate; removing the portion of the etch barrier layer located in the opening area; forming a side wall on the side of the opening area corresponding to the etch barrier layer; etching the first epitaxial structure using the etch barrier layer and the side wall as a mask to form an opening; and forming an electrode structure in the opening. Because the side wall structure is formed at the opening of the etch barrier layer before etching the first epitaxial structure, the size of the opening is further reduced, and the size of the opening subsequently formed on the first epitaxial structure is smaller, and the electrode structure formed is also smaller, which can further reduce the parasitic capacitance of the semiconductor device and improve the switching speed of the semiconductor device.

It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

FIG2 is a schematic diagram of a product structure corresponding to the main steps of a method for preparing a semiconductor device provided by an embodiment of the present invention;

3 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

4 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

5 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

6 is a schematic diagram of a product structure corresponding to the main steps of another method for preparing a semiconductor device provided by an embodiment of the present invention;

7 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

8 is a schematic diagram of a product structure formed corresponding to the main steps of another method for preparing a semiconductor device provided by an embodiment of the present invention;

FIG. 9 is a schematic diagram of a product structure formed corresponding to main steps of another method for preparing a semiconductor device provided by an embodiment of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

FIG. 1 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention. Referring to FIG. 1 , the method for preparing a semiconductor device includes:

Step S110, forming a first epitaxial structure on a substrate, wherein the first epitaxial structure includes an opening region;

Specifically, FIG. 2 is a schematic diagram of a product structure corresponding to the main steps of a method for preparing a semiconductor device provided in an embodiment of the present invention, in combination with FIG. 1 and FIG. 2. The semiconductor device of this embodiment may be a high electron mobility transistor (HEMT) semiconductor device, a heterojunction bipolar transistor (HBT), a heterojunction field effect transistor (HFET), or a modulation-doped FET (MODFET), etc., which is formed by a heterojunction. The first epitaxial structure 12 may be made by an epitaxial process, and the opening area HO of the first epitaxial structure 12 is an area where an opening needs to be formed, and the opening is subsequently used to form an electrode of the semiconductor device. Preferably, the gate parasitic capacitance in the semiconductor device has a greater influence on the switching performance of the semiconductor device, and the size of the gate parasitic capacitance is related to the size of the gate electrode. Therefore, the opening area described in this embodiment may be a corresponding area where a gate electrode needs to be formed.

By way of example, the substrate 11 is, for example, silicon, silicon carbide (SiC), gallium arsenide (GaAs), silicon germanium (SiGe), p-doped silicon, n-doped silicon, sapphire, silicon on insulator, or other semiconductor materials. In addition, the substrate 11 may also include, for example, group III elements, group IV elements, group V elements, or a combination thereof (e.g., group III-V compounds), etc. The first epitaxial structure 12 may form a heterojunction, and may exemplarily include a channel layer and a barrier layer, etc.

Step S120, forming an etching stop layer on a side of the first epitaxial structure away from the substrate;

Specifically, the etch stop layer 13 is used to prevent the first epitaxial structure 12 covered by the etch stop layer 13 from being corroded. The etch stop layer 13 can be formed by epitaxy or deposition processes, and the deposition process is, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low-power CVD (LPCVD) or plasma-assisted vapor deposition.

Step S130, removing the portion of the etching stop layer located in the opening area;

Specifically, the etching stop layer 13 can be patterned by a photolithography process, so that the portion of the etching stop layer 13 located in the opening area HO is removed, and the remaining portion is retained. As shown in FIG. 2 , a layer of photoresist 20 can be first formed on the etching stop layer 13, and then the photoresist 20 is exposed and developed using a mask, so that the portion of the photoresist 20 corresponding to the opening area HO is removed, and then the photoresist 20 is used as a mask to etch away the portion of the etching stop layer 13 located in the opening area HO. The etching process can be dry etching or wet etching, etc.

Step S140, forming a sidewall at the side of the opening area corresponding to the etching stop layer;

Specifically, as shown in FIG2 , after the portion of the etch stop layer 13 corresponding to the opening area HO is removed, the first epitaxial structure 12 needs to be etched using the etch stop layer 13 as a mask. Limited by the accuracy of the photolithography machine, the minimum size of the photoresist 20 that can be etched is also large, which also makes the minimum size of the opening area HO larger. In other words, the portion of the etched etch stop layer 13 cannot be further reduced due to the accuracy of the photolithography machine. The area of the first epitaxial structure 12 exposed by the etch stop layer 13 is large, and the opening formed on the first epitaxial structure 12 is also large, so that the gate electrode formed later is larger, which leads to a larger gate parasitic capacitance of the semiconductor device. In this embodiment, a sidewall 141 can be formed on the side of the etch stop layer 13. Since the sidewall 141 has a certain lateral (the arrangement direction of the etch stop layer 13 and the sidewall 141 in FIG2 ) dimension, the overall structure composed of the etch stop layer 13 and the sidewall 141 has a smaller area of the first epitaxial structure 12 exposed.

Step S150, etching the first epitaxial structure using the etching stop layer and the sidewall spacer as a mask to form an opening;

Specifically, the etching method of the first epitaxial structure 12 is well known to those skilled in the art, such as dry etching or wet etching. In this embodiment, due to the formation of the sidewall 141, the exposed area of the first epitaxial structure 12 is small, so that the opening HO1 formed by etching the first epitaxial structure 12 is also small. From the above analysis, it can be seen that in this embodiment, by forming the sidewall 141 at the position of the etching stop layer in the opening area, the size of the opening can be further reduced. The size of the opening can be further reduced under the condition of the maximum size of the lithography machine.

Step S160: forming an electrode structure in the opening.

Specifically, the electrode structure may include a second epitaxial structure 15, and the second epitaxial structure 15 is, for example, a p-type gate, that is, a p-type semiconductor material. The second epitaxial structure 15 can make the semiconductor device constitute an enhanced device. Of course, the electrode structure can also be other structures. The second epitaxial structure 15 can be formed by epitaxy or the like. Since the size of the opening HO1 is small, the second epitaxial structure 15 located in the opening HO1 is also small, so that the overall size of the electrode structure can be made smaller, thereby further reducing the gate parasitic capacitance of the semiconductor device.

The technical solution of this embodiment adopts a method for preparing a semiconductor device, which includes forming a first epitaxial structure on a substrate, the first epitaxial structure including an opening area; forming an etching barrier layer on a side of the first epitaxial structure away from the substrate; removing the portion of the etching barrier layer located in the opening area; forming a side wall on the side of the opening area corresponding to the etching barrier layer; etching the first epitaxial structure using the etching barrier layer and the side wall as a mask to form an opening; and forming an electrode structure in the opening. Since the side wall structure is formed at the opening of the etching barrier layer before etching the first epitaxial structure, the size of the opening is further reduced, and the size of the opening subsequently formed on the first epitaxial structure is smaller, and the electrode structure formed is also smaller, which can further reduce the parasitic capacitance of the semiconductor device and improve the switching speed of the semiconductor device.

Optionally, FIG3 is a flow chart of another method for preparing a semiconductor device provided in an embodiment of the present invention, with reference to FIG3. In this embodiment, the method for preparing a semiconductor device includes:

Step S110, forming a first epitaxial structure on a substrate, wherein the first epitaxial structure includes an opening region;

Step S120, forming an etching stop layer on a side of the first epitaxial structure away from the substrate;

Step S130, removing the portion of the etching stop layer located in the opening area;

In the above embodiment, step S140 specifically includes:

Step S141, forming a spacer material layer on the entire surface, the spacer material layer covering the etch stop layer and the first epitaxial structure exposed by removing the etch stop layer from the opening area;

2 , the spacer material layer 14 is formed by, for example, deposition or the like. Through the deposition process, a layer of spacer material layer 14 can be formed on the entire surface, and the material of the spacer material layer 14 can be a dielectric material or an epitaxial material.

Step S142, forming a sidewall by etching the sidewall material layer.

Specifically, the sidewall etching is, for example, dry etching, which has anisotropic characteristics. When the sidewall material layer 14 is etched to expose the corresponding etching barrier layer and the first epitaxial structure, the etching stops. Since the sidewall material layer at the corresponding position of the sidewall is thicker, when the etching stops, the sidewall material layer of this part will not be completely etched, but the lower sidewall 141 will be retained.

Step S150, etching the first epitaxial structure using the etching stop layer and the sidewall spacer as a mask to form an opening;

Step S160: forming an electrode structure in the opening.

Optionally, based on the above implementation, when the spacer material layer is formed on the entire surface, the step includes: determining the thickness of the spacer material layer according to the opening size corresponding to the first epitaxial structure and the final size of the semiconductor device.

Specifically, the opening size corresponding to the first epitaxial structure of this embodiment is an expected size. When the expected size is larger, the thickness of the corresponding sidewall material layer is also larger; when the expected size is smaller, the thickness of the corresponding sidewall material layer is also smaller. The thickness of the sidewall material layer is related to the lateral size of the sidewall. When the thickness of the sidewall material layer is larger, the lateral size of the sidewall formed subsequently is also larger, so that a smaller opening can be made on the first epitaxial structure. When the thickness of the sidewall material layer is smaller, the lateral size of the sidewall formed subsequently is smaller, so that a relatively larger opening can be made on the first epitaxial structure. In addition, the thickness of the sidewall material layer also needs to consider the overall size of the semiconductor device. If the final size of the semiconductor device is larger, the thickness of the corresponding sidewall material layer can be set larger; and if the final size of the semiconductor device is smaller, the thickness of the corresponding sidewall material layer needs to be set smaller to avoid affecting the performance of the semiconductor device.

Optionally, FIG4 is a flow chart of another method for preparing a semiconductor device provided in an embodiment of the present invention, in combination with FIG2 and FIG4. The method for preparing a semiconductor device in this embodiment includes:

Step S110, forming a first epitaxial structure on a substrate, wherein the first epitaxial structure includes an opening region;

Step S120, forming an etching stop layer on a side of the first epitaxial structure away from the substrate;

Specifically, in this embodiment, the material of the etching stop layer 13 is a dielectric material, which may be silicon oxide or silicon nitride.

Step S130, removing the portion of the etching stop layer located in the opening area;

Step S140, forming a sidewall at the side of the opening area corresponding to the etching stop layer;

Specifically, the material of the sidewall is different from the material of the etch stop layer, so as to avoid etching away the etch stop layer when the sidewall material layer is etched to form the sidewall. Exemplarily, when the material of the etch stop layer 13 is silicon oxide, the material of the sidewall 141 may be silicon nitride. When the material of the etch stop layer 13 is silicon nitride, the material of the sidewall 141 may be silicon oxide.

Step S150, etching the first epitaxial structure using the etching stop layer and the sidewall spacer as a mask to form an opening;

Step S200, removing the dielectric material layer and the sidewalls;

Specifically, as shown in FIG. 2 , in this embodiment, the dielectric material layer is not conducive to the subsequent epitaxial growth of the second epitaxial structure, so the dielectric material layer can be removed before forming the electrode structure. The removal method is, for example, wet etching. After the dielectric material layer and the sidewalls are etched, the first epitaxial structure 12 is exposed, which is conducive to the subsequent growth of the electrode structure (such as the second epitaxial structure in the electrode structure).

Step S160: forming an electrode structure in the opening.

In this embodiment, a dielectric material is selected as an etching stop layer, and the dielectric material and the sidewalls are subsequently removed. The material selection of the dielectric material is relatively diverse, which is conducive to reducing the preparation cost of semiconductor devices.

Optionally, FIG5 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, and FIG6 is a schematic diagram of a product structure corresponding to the main steps of another method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to FIG5 and FIG6. The method for preparing a semiconductor device includes:

Step S110, forming a first epitaxial structure on a substrate, wherein the first epitaxial structure includes an opening region;

Step S120, forming an etching stop layer on a side of the first epitaxial structure away from the substrate;

Specifically, in this embodiment, the material of the etch stop layer 13 is an epitaxial material layer. The material of the epitaxial material layer is, for example, aluminum nitride. The etch stop layer of this embodiment can not only be used as a mask for etching the first epitaxial structure, but also can continue to epitaxially form the second epitaxial structure in the electrode structure.

Step S130, removing the portion of the etching stop layer located in the opening area;

Step S140, forming a sidewall at the side of the opening area corresponding to the etching stop layer;

Specifically, the material of the sidewalls is different from the material of the etching barrier layer, so as to avoid etching away the etching barrier layer when etching the sidewall material layer to form the sidewalls. For example, the material of the sidewalls 141 in this embodiment can be silicon oxide or silicon nitride.

Step S150, etching the first epitaxial structure using the etching stop layer and the sidewall spacer as a mask to form an opening;

In this embodiment, forming an electrode structure in the opening includes:

Step S161, forming an electrode structure that fills the opening and at least partially covers the epitaxial material layer;

Specifically, the electrode structure in this embodiment includes a second epitaxial structure 15. Since the material of the etch stop layer 13 is an epitaxial material, the second epitaxial structure 15 can be directly epitaxially grown on the etch stop layer 13 without the step of removing the etch stop layer 13 in the embodiment corresponding to Figure 2, thereby saving process steps and improving the production efficiency of semiconductor devices.

Optionally, in the above embodiment, an etching selectivity ratio of the first epitaxial structure to the epitaxial material layer is greater than or equal to 5.

Specifically, since both the first epitaxial structure and the epitaxial material layer are epitaxial materials, if the etching selectivity of the first epitaxial structure and the epitaxial material layer is relatively small, when etching the first epitaxial structure, the epitaxial material layer will also be etched more, and thus may not be able to play the role of etching barrier. In this embodiment, by selecting the etching selectivity ratio of the first epitaxial structure and the epitaxial material layer to be greater than or equal to 5, it is ensured that the epitaxial material layer has a higher etching barrier effect.

It should be noted that the specific material of the epitaxial material layer can be selected according to the material of the first epitaxial structure, and can be aluminum nitride as described above, or other feasible materials.

Optionally, FIG. 7 is a flow chart of another method for preparing a semiconductor device provided in an embodiment of the present invention, FIG. 8 is a schematic diagram of a product structure formed by the main steps of another method for preparing a semiconductor device provided in an embodiment of the present invention, and FIG. 9 is a schematic diagram of a product structure formed by the main steps of another method for preparing a semiconductor device provided in an embodiment of the present invention, with reference to FIG. 7 to FIG. 9. The method for preparing a semiconductor device includes:

Step S110, forming a first epitaxial structure on a substrate, wherein the first epitaxial structure includes an opening region;

Step S120, forming an etching stop layer on a side of the first epitaxial structure away from the substrate;

Specifically, in the embodiment corresponding to FIG8 , the material of the etch stop layer 13 is a dielectric material, which needs to be removed later before the second epitaxial structure can be fabricated. In the embodiment corresponding to FIG9 , the material of the etch stop layer 13 is an epitaxial material layer, which does not need to be removed later, and the second epitaxial structure can be directly generated by epitaxy on the etch stop layer 13 .

Step S130, removing the portion of the etching stop layer located in the opening area;

Step S210, etching the portion of the first epitaxial structure located in the opening area to form a sub-opening; wherein the sub-opening has a preset depth, and the preset depth is smaller than the depth of the opening corresponding to the first epitaxial structure;

Specifically, in this embodiment, after the patterned etching stop layer, the first epitaxial structure may be further half-etched to form a sub-opening HO2. It should be noted that when the first epitaxial structure includes multiple film layers, the sub-opening HO2 may only penetrate part of the film layers, or penetrate a part of the uppermost layer (i.e., the film layer in contact with the etching stop layer).

Step S143, forming a side wall located at the side of the sub-opening;

Specifically, in this embodiment, the sidewall 141 is not only formed in the film layer where the etching stop layer is located, but also in the film layer corresponding to the first epitaxial structure. Due to the isotropy of wet etching, when etching the first epitaxial structure 12, not only an opening is formed, but also part of the first epitaxial structure is etched laterally along the sidewall of the opening. In this embodiment, since the sidewall 141 is also formed in the film layer corresponding to the first epitaxial structure, the size of the opening formed when wet etching is used can be reduced, and the size of the opening can be further reduced, thereby reducing the parasitic capacitance of the semiconductor device.

Step S150, etching the first epitaxial structure using the etching stop layer and the sidewall spacer as a mask to form an opening;

Step S160: forming an electrode structure in the opening.

Optionally, in the above embodiment, the preset depth is less than or equal to half the depth of the opening corresponding to the first epitaxial structure.

Specifically, if the preset depth is large, it may affect the gate characteristics of the semiconductor device, thereby affecting the performance of the semiconductor device. Therefore, by setting the preset depth in this embodiment, it is possible to ensure that the opening size of the semiconductor device is small and reduce the impact on the performance of the semiconductor device.

Optionally, referring to FIG. 2 , in the above embodiment, forming the first epitaxial structure on the substrate includes: forming one or a combination of a GaN layer 121, an AlN layer 122, an AlGaN layer 123, and a UGaN layer 124 on the substrate. The GaN layer is a channel layer, and the openings of this embodiment can all penetrate the UGaN layer, the AlGaN layer, and the AlN layer, and can partially penetrate the GaN layer. Before the subsequent production of the second epitaxial structure, a layer of AlGaN layer can also be covered first.

In addition, it should be noted that this embodiment only illustrates the electrode structure and a partial structure of the semiconductor device. Those skilled in the art know that the electrode structure may also include an ohmic metal layer and an electrode metal, etc. The semiconductor device may also include other electrodes, such as a source electrode and a drain electrode, etc.

The embodiment of the present invention further provides a semiconductor device, which is prepared by the method for preparing a semiconductor device provided by any embodiment of the present invention. The semiconductor device has the characteristics of small opening size and small electrode size, and thus has small parasitic capacitance, so that its switching speed is faster and more suitable for high-frequency application scenarios.

It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (11)

1. A method of manufacturing a semiconductor device, comprising:

forming a first epitaxial structure on a substrate, wherein the first epitaxial structure comprises an opening area;

forming an etching barrier layer on one side of the first epitaxial structure away from the substrate;

removing the part of the etching barrier layer located in the opening area;

forming a side wall on the side edge of the opening area corresponding to the etching barrier layer;

etching the first epitaxial structure by taking the etching barrier layer and the side wall as masks to form an opening;

and forming an electrode structure in the opening.

2. The method for manufacturing a semiconductor device according to claim 1, wherein forming a sidewall in the opening region comprises:

forming a side wall material layer on the whole surface, wherein the side wall material layer covers the etching barrier layer and the first epitaxial structure exposed by removing the etching barrier layer in the opening area;

and etching the side wall material layer through the side wall to form the side wall.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the forming of the sidewall material layer over the entire surface comprises:

and determining the thickness of the side wall material layer according to the opening size corresponding to the first epitaxial structure and the final size of the semiconductor device.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the etch stop layer comprises a dielectric material layer;

the method further comprises the following steps before the electrode structure is formed in the opening:

and removing the dielectric material layer and the side wall.

5. The method of manufacturing a semiconductor device according to claim 4, wherein the material of the dielectric material layer comprises silicon oxide, and the material of the sidewall comprises silicon nitride; or the material of the dielectric material layer comprises silicon nitride, and the material of the side wall comprises silicon oxide.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the etch stop layer comprises an epitaxial material layer;

the forming an electrode structure within the opening includes:

the electrode structure is formed filling the opening and at least partially covering the epitaxial material layer.

7. The method of manufacturing a semiconductor device according to claim 6, wherein an etching selectivity of the first epitaxial structure to the epitaxial material layer is greater than or equal to 5.

8. The method of manufacturing a semiconductor device according to claim 6, wherein the material of the epitaxial material layer comprises aluminum nitride, and the material of the sidewall comprises silicon nitride or silicon oxide.

9. The method for manufacturing a semiconductor device according to claim 1, wherein before forming the sidewall in the opening region, further comprises:

etching the part of the first epitaxial structure, which is positioned in the opening area, to form a sub-opening; the sub-openings have preset depths, and the preset depths are smaller than the depths of the openings corresponding to the first epitaxial structures;

forming a side wall on the side edge of the opening area corresponding to the etching barrier layer comprises:

and forming a side wall positioned at the side edge of the sub opening.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the preset depth is less than or equal to half of the depth of the opening corresponding to the first epitaxial structure.

11. A semiconductor device, characterized in that the semiconductor device is manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 10.