CN1178295C - Flip chip and flip chip type packaging substrate - Google Patents

Abstract

A flip chip and flip chip type package substrate, wherein the flip chip has a plurality of core power/ground pads, at least one signal pad ring, at least one power pad ring and at least one ground pad ring, all disposed on the active surface of the flip chip, and the pad rings are concentrically and annularly distributed around the core power/ground pads. In addition, the top conducting wire layer of the flip chip type package substrate is provided with a plurality of bump pads, the positions of the bump pads correspond to the positions of the welding pads of the flip chip respectively, a non-signal bump pad ring can be arranged on the periphery of the bump pad ring, and a pair of power traces or ground traces can be arranged on any conducting wire layer of the flip chip type package substrate and are respectively arranged on two sides of one signal trace to serve as the protective trace of the signal trace.

Description

Flip Chip and Flip Chip Package Substrate

technical field

The present invention relates to a flip chip and a flip chip package substrate, and more particularly to a flip chip with a plurality of pad rings, and a flip chip corresponding to the above flip chip with a plurality of bumps. Flip Chip Package Substrate with Block Spacer Ring.

Background technique

Flip chip bonding technology (Flip Chip, FC) is a common chip packaging technology used in chip size packaging (Chip Scale Package, CSP), which mainly uses the arrangement of the area array (Area Array), the chip ( The multiple die pads of the die are designed and arranged on the active surface of the chip, that is, the side of the chip with active components (active device), and bumps are formed on each pad respectively, and then Then, the bumps on the chip are connected to the corresponding contacts on the carrier, so that the chip is correspondingly bonded to the surface of the carrier in a flipping manner.

Due to the flip-chip bonding technology has the advantages of reducing the packaging area, increasing the packaging density, and shortening the signal transmission path, the flip-chip bonding technology has been widely used in the field of chip packaging, especially with high pins (High Pin Count ) chip packaging structure, such as flip-chip bonding (FC) with a ball grid array (BGA) flip-chip ball grid array (FCBGA) chip packaging type, or flip-chip Chip bonding (FC) and pin grid array (Pin Grid Array, PGA) chip packaging types can effectively package a single chip with up to hundreds of pads.

Whether it is the above-mentioned flip chip ball grid array (FCBGA), flip chip pin grid array (FCPGA), or other chip packaging technologies applied to flip chip bonding (FC), usually using flip chip The chip package substrate (substrate) is used as a carrier for flip-chip bonding, and the flip-chip package substrate (hereinafter referred to as the substrate) for flip-chip bonding is mainly composed of multi-layer patterned wire layers and multi-layer The insulation layers are interlaced and laminated, and a plurality of conductive plugs respectively penetrate through the above insulation layers to electrically connect the above-mentioned adjacent wire layers. In addition, the top surface of the substrate is further equipped with a plurality of bump pads for connecting the bumps on the chip, while the bottom surface of the substrate is equipped with a plurality of solder ball pads, which respectively pass through the interior of the substrate. The wires are wound to the solder ball pads on the bottom surface of the substrate, and conductive structures such as solder balls can be arranged on the solder ball pads to connect to next-level electronic devices, such as printed circuits. Board (Printed Circuit Board, PCB) and so on.

Please refer to FIG. 1 , which is a partial cross-sectional view of a known flip-chip packaging structure. On the active surface 12 of the chip 10, a plurality of bonding pads 14 are arranged in a surface matrix, while the flip-chip package substrate 20 (hereinafter referred to as the substrate 20) is composed of a multi-layer patterned wire layer 24 (such as the component label 24a, 24b, 24c...) and multi-layer insulating layers 26 (such as component numbers 26a, 26b, 26c) are formed by interlacing and stacking each other, and a plurality of conductive plugs (plug) 36 are used to penetrate the insulating layer 26 respectively. To electrically connect the conductive layer 24 . The types of the conductive plug 36 include a via 36a and a plated through hole (PTH) 36b, both of which have different sizes according to different plug manufacturing processes.

Please also refer to FIG. 1 , the top layer of the wiring layer 24 (that is, the one closest to the top surface 21 of the substrate 20) is the first wiring layer 24a, which has a plurality of bump pads 30, and the position of the bump pads 30 is Corresponding to the positions of the pads 14, so that the pads 14 can be connected to the corresponding bump pads 30 on the substrate 20 through the bumps 16, and then through the circuit formed by the wire layer 24 and the conductive plug 36, the chip 10 Part of the bonding pads 14 fan out to areas other than under the active surface 12 of the chip 10. In addition, the substrate 20 further includes a patterned solder mask (Solder Mask) 28, which covers the first insulating layer 26a and the first wiring layer 24a, and simultaneously exposes a plurality of bump pads of the first wiring layer 24a. 30, used to protect other parts of the first wire layer 24a and the first insulating layer 26a. In addition, the bottom surface 22 of the substrate 20 has a plurality of solder ball pads 34 for connecting conductive structures such as solder balls (not shown) for connecting to next-level electronic devices.

Please refer to FIG. 2A , which is a bottom view of the chip in FIG. 1 . The active surface 112 of the chip 110 is configured with a plurality of welding pads 114 (such as component numbers 114a, 114b, 114c, 114d, . It is signal pad (signal pad) 114a, power pad (power pad) 114b, ground pad (groundpad) 114c and core (core) power/ground pad 114d, wherein signal pad 114a, power pad 114b and ground The bonding pads 114c are located on the periphery of the core power/ground bonding pads 114d. It should be noted that, since the known signal pads 114a, power pads 114b and ground pads 114c are irregularly distributed on the active surface 112 of the chip 110, when the original pads on the chip 110 (not Shown) When redistributed on the active surface 112 of the chip 110 through the redistribution layer (Re-Distribution Layer, RDL) (not shown), the original pads of the chip 110 will be relatively increased after being re-distributed by winding. The line length of the bonding pad 114 increases, thereby increasing the signal transmission path length, thereby reducing the electrical performance of the chip 110 (Electrical Performance).

Next, please refer to FIG. 2B , which is a partial top view of a flip-chip packaging substrate corresponding to the chip shown in FIG. 2A . A plurality of bump pads 130 (such as component numbers 130a, 130b, 130c, 130d . Within the chip area 140 of the package substrate 120 , corresponding to the bonding pads 114 on the chip 110 shown in FIG. 2A , they are arranged and distributed in a planar matrix. In addition, in order to correspond to the signal pads 114a, power pads 114b, ground pads 114c and core power supply/ground pads 114d connected to the chip 110 in FIG. 130a, power bump pad 130b, ground bump pad 130c and core power supply/ground bump pad 130d, wherein the signal bump pad 130a, power supply bump pad 130b and ground bump pad 130c are all located on the core power supply/ground pad 130d the periphery. It should be noted that, since the known signal pads 114a, power pads 114b and ground pads 114c are irregularly distributed on the active surface 112 of the chip 110, as shown in FIG. The bump pads 130 a , the power bump pads 130 b and the ground bump pads 130 c are also irregularly distributed on the top surface 121 of the substrate 120 .

Contents of the invention

The first purpose of the present invention is to provide a flip chip, which is used to shorten the winding length of the internal circuit of the flip chip, so as to shorten the winding length of the reconfiguration circuit layer of the flip chip, thereby improving the electrical performance of the chip. In addition, the power pads and ground pads can be designed and distributed separately, which is not only beneficial to the wiring of the chip, but also makes the power and ground referenced by the same group of signals more even, which can also improve the electrical performance of the chip.

The second object of the present invention is to provide a flip-chip package substrate, the positions of the bump pads respectively correspond to the pad positions of the flip-chip of the first object, and correspondingly, the power bump pads and the ground bump pads are respectively The design is concentrated and distributed, so it is beneficial to the wiring of the substrate, and the guard trace can be arranged on both sides of the signal trace to avoid crosstalk between the signal trace and other adjacent signal traces. -talk) phenomenon, thereby improving the electrical performance of the chip.

Based on the above-mentioned first object of the present invention, the present invention proposes a flip chip, which has an active surface, and the flip chip further has a plurality of core power/ground pads, at least one signal pad ring, at least one power pad The pad ring and at least one ground pad ring are all arranged on the active surface, wherein the signal pad ring, the power pad ring and the ground pad ring are centered on these core power/ground pads and distributed in a concentric ring shape on the periphery of these core power/ground pads.

Based on the above-mentioned second object of the present invention, the present invention further proposes a flip-chip packaging substrate, which has a plurality of conductive layers, which overlap each other in sequence, and a plurality of insulating layers, which are respectively arranged between two adjacent conductive layers. Spaces are used to electrically isolate these wire layers and overlap with these wire layers, and a plurality of conductive plugs respectively penetrate through these insulating layers to electrically connect these conductive layers, wherein the topmost layer of these wire layers Having a plurality of core power/ground bump pads, at least one signal bump pad ring, at least one power bump pad ring, and at least one ground bump pad ring, wherein the signal bump pad ring, the power bump pad ring, and the ground bump pad The block pad ring is centered on these core power/ground bump pads, and is distributed concentrically around the periphery of these core power/ground bump pads.

In order to make the above-mentioned purposes, features and advantages of the present invention clearly understandable, a preferred embodiment is specifically cited below, and in conjunction with the attached icons, the detailed description is as follows:

Description of drawings

Fig. 1 is a partial sectional view of a known flip-chip packaging structure;

Fig. 2A is the bottom view of the chip of Fig. 1;

2B is a partial top view of a flip-chip packaging substrate corresponding to the chip in FIG. 2A;

Fig. 3A, Fig. 3C, Fig. 3E, Fig. 3G, Fig. 3I, Fig. 3K and Fig. 3M are the bottom views of a kind of chip of the preferred embodiment of the present invention;

Fig. 3B, Fig. 3D, Fig. 3F, Fig. 3H, Fig. 3J, Fig. 3L, and Fig. 3N are respectively the flip-chip type of the chip corresponding to Fig. 3A, Fig. 3C, Fig. 3E, Fig. 3G, Fig. 3I, Fig. 3K and Fig. 3M A partial top view of the package substrate;

4A is a partial schematic view of the first wiring layer of the flip-chip packaging substrate of FIG. 3B; and

FIG. 4B is a partial schematic diagram of the second wire layer of the flip-chip packaging substrate of FIG. 3B .

Graphical labeling instructions

10: chip 12: active surface

14: Welding pad 16: Bump

20: Flip chip package substrate 21: Top surface

22: Bottom surface 24, 24a～24c: wire layer

26, 26a～26c: insulation layer 28: solder mask layer

30: bump pad 32: plug pad

34: Solder ball pad 36: Conductive plug

36a: Conduction plug 36b: Plated through plug

110: chip 112: active surface

114, 114a～114d: Welding pads 120: Flip chip package substrate

121: top surface 130, 130a～130d: bump pad

150: chip area 210: chip

212: active surface 214, 214a～214d: welding pad

215, 215a～215f: welding pad ring 220: flip-chip package substrate

221: top surface 230, 230a～230d: bump pad

231, 231a～231f: bump backing ring

250: chip area 324a: first wire layer

324b: Second wire layer 330: Bump pad

331, 331a～331f: bump gasket ring 332: plug pad

333, 331a～331f: bump backing ring 336: conductive plug

340, 342: Conductive traces 340a, 342a: Ground traces

340b, 342b: signal traces 350: chip area

Detailed ways

Please refer to FIG. 3A , which is a bottom view of a chip according to a preferred embodiment of the present invention. The active surface 212 of the chip 210 is provided with a plurality of bonding pads 214 (such as component numbers 214 a , 214 b , 214 c , 214 d . . . ) in a matrix, forming a plurality of bonding pad rings 215 . In addition, according to different functions, the pads 214 can also be divided into signal pads 214a, power pads 214b, ground pads 214c, and core power/ground pads 214d, wherein the signal pads 214a, power pads 214b and ground pads The pads 214c are centered on the core power/ground pads 214 and distributed around the core power/ground pads 214d. It should be noted that, for a signal pad ring composed of a plurality of pads 214 (such as the second pad ring 215b, the third pad ring 215c and the sixth pad ring 215f), the pads 214 have 100% More than 50% are signal pads 214a, and preferably, more than 90% of the pads 214 of the signal pad ring are signal pads 214a, and the power pad ring (such as the fifth pad ring 215e) The same is true for the ground pad rings (such as the first pad ring 215a and the fourth pad ring 215d). In addition, the signal pad ring can be composed of single-layer, double-layer, three-layer or multi-layer ring-arranged pads 214. For example, the second pad ring 215b and the third pad ring 215c in FIG. 3A can be regarded as the same signal pad ring. Pad rings, likewise, power pad rings and ground pad rings.

Please also refer to FIG. 3A , the multi-circle welding pad rings 215 are concentrically arranged and distributed on the active surface 212 of the chip 210, and each ring of welding pad rings 215 can be respectively set as signal welding pad rings, power supply welding pad rings and grounding pads. pad ring. Taking the chip 210 of FIG. 3A as an example, the chip 210 has three signal pad rings (such as the second pad ring 215b, the third pad ring 215c and the sixth pad ring 215f), a power pad ring (such as the fifth Welding pad ring 215e) and two grounding welding pad rings (such as the first welding pad ring 215a and the fourth welding pad ring 215d), wherein the multi-circle welding pad ring 215 of the chip 210 in FIG. 3A is only arranged in the form of many concentric rings One of the ways of arrangement, and other ways of concentric ring arrangement are shown in the chips 210 in FIG. 3C , FIG. 3E , FIG. 3G , FIG. 3I , FIG. 3K and FIG. 3M . However, the multi-turn pad rings 215 with different functions of the chip 210 of the present invention are not limited to the concentric annular arrangements shown in FIGS. 3A, 3C, 3E, 3G, 3I, 3K and 3M. It can be arranged in other concentric rings. It is worth noting that in the preferred embodiment of the present invention, the sixth pad ring 215f in the outermost circle can be designed as a power pad ring or a ground pad ring. The shielding effect (Shielding).

Please also refer to FIG. 3A. In a preferred embodiment of the present invention, a plurality of welding pads 214 of the same function are arranged together to form a welding pad ring 215 of the same function, and the power supply welding pad 214b of the power supply welding pad ring 215e can be wound To be electrically connected to each other, the ground pads 214c of the ground pad ring 215a (or ground pad ring 215d) can be electrically connected to each other through winding wires, so that the power pads 214b and 214b referred to by each signal pad 214a and The ground pads 214c will be relatively uniform, which helps to improve the electrical performance of the chip.

Please refer to FIG. 1 and FIG. 3B at the same time, wherein FIG. 3B is a partial top view of a flip-chip packaging substrate corresponding to the chip in FIG. 3A . As shown in FIG. 3B , the flip-chip package substrate 220 (hereinafter referred to as the substrate 220 ) is composed of the patterned multilayer wiring layer 24 (such as component numbers 24a, 24b, 24c, ...) and multilayer insulation in FIG. Layers 26 (such as component numbers 26a, 26b, 26c, . The wire layers 24 are isolated and interlaced with the wire layers 24 . In addition, the substrate 220 also has a plurality of conductive plugs 36 shown in FIG. 1, such as vias 36a and plated through plugs (PTH) 36b, which respectively penetrate through the insulating layer 26 of FIG. 1 for electrical connection. Two adjacent wire layers 24 in FIG. 1 .

Please also refer to FIG. 1 and FIG. 3B. As shown in FIG. 3B, a plurality of bump pads 230 (such as component numbers 230a, 230b, 230c, . . . ) on the top surface 221 of the substrate 220 are the bumps in FIG. The pad 30 is composed of the first wire layer 24 a in FIG. 1 , wherein the first wire layer 24 a is the topmost layer of these wire layers 24 , that is, the wire layer 24 closest to the top surface 221 of the substrate 220 . Next, as shown in FIG. 1, the distribution positions of the bump pads 30 correspond to the distribution positions of the solder pads 14, so that the solder pads 14 can be connected to the corresponding bump pads 30 on the substrate 20 through the bumps 16, and then through the wire layer. 24 , conductive plugs 36 and other conductive structures, and fan out part of the bonding pads 14 of the chip 10 to areas other than the area below the active surface 12 of the chip 10 .

Please also refer to FIG. 1 and FIG. 3B. In order to conform to the distribution positions of the plurality of pads 214 of the chip 210 in FIG. 3A, the bump pads 230 of the substrate 220 are also distributed on the top surface of the substrate 220 in a matrix manner. 221 within the chip area 250 and form a plurality of bump pad rings 231 . In addition, according to the connection of the bump pad 230 to the signal pad 214a, the power pad 214b, and the ground pad 214c in FIG. The ground bump pad 230c and the core power supply/ground bump pad 230d, wherein the signal bump pad 230a, the power supply bump pad 230b and the ground bump pad 230c are distributed in the core power supply/ground bump pad 230d by the core power supply/ground bump pad 230d. The periphery of the ground bump pad 230d. It is worth noting that the signal bump pad rings (such as the second bump pad ring 231b, the third bump pad ring 231c and the sixth bump pad ring 231f) composed of a plurality of bump pads 230, the bump pads More than fifty percent of the pads 230 are signal bump pads 230a, and preferably more than ninety percent of the bump pads 230 of the signal bump pad ring are signal bump pads 230a, while power bump pads The same is true for backing rings such as fifth bump backing ring 231e and ground bump backing rings such as first bump backing ring 231a and fourth bump backing ring 231d. In addition, the signal pad pad ring system can correspond to the signal pad pad ring of the chip in FIG. The bump back ring 231b and the third bump back ring 231c can be regarded as the same signal bump back ring, as can the power bump back ring and the ground bump back ring.

Please also refer to FIG. 3B, the arrangement of the multi-turn bump backing ring 231 on the substrate 220 is only one of many concentric ring arrangements, and other concentric ring arrangements can also be as shown in FIGS. 3D, 3F, and 3H. , Figure 3J, Figure 3L and Figure 3N. However, the multi-turn bump backing ring 215 of the substrate 220 of the present invention is not limited to the concentric annular arrangement shown in FIG. 3B, FIG. 3D, FIG. 3F, FIG. 3H, FIG. 3J, FIG. 3L and FIG. Corresponding to the distribution of the bonding pads 214 of the chip 210 , there are other concentric circular arrangements.

Please refer to FIG. 4A and FIG. 4B in sequence, which are partial schematic diagrams of the first wire layer and the second wire layer of the flip-chip package substrate shown in FIG. 3B . As shown in FIG. 4A, the first wiring layer 324a (ie, the first wiring layer 24a in FIG. 1 ) has a plurality of bump pads 330 (ie, the bump pads 30 in FIG. 1 ), and they are arranged in a concentric ring shape. , divided into multi-turn bump back ring 331, that is, multi-turn bump back ring 231 shown in FIG. 3B, wherein FIG. within the chip area 350 (ie, the chip area 250 in FIG. 3B ). It is worth noting that, if taking the six-circle bump ring 231 of the flip-chip package substrate 220 in FIG. 3B as an example, the six-circle bump ring 331 in FIG. bump back ring 331b, signal bump back ring 331c, ground bump back ring 331d, power bump back ring 331e, and signal bump back ring 331f.

As shown in FIG. 4B, the second wiring layer 324b (such as the second wiring layer 24b of FIG. 1) has a plurality of plug pads (via pad) 332 (such as the plug pad 32 of FIG. 1), which are all located in the chip area 350. (that is, the chip region 250 of FIG. 3B ), wherein the bump pads 330 of the first wiring layer 324a of FIG. The plug pads 332 of the two wire layers 324b are electrically connected to each other. Similarly, the plurality of plug pads 332 of the second wire layer 324b also constitute a plurality of plug rings 333, which respectively correspond to the signal bump ring 331a, the power bump ring 331b and the first wire layer 324a. The ground bump ring 331c is the signal plug ring 333a, the power plug ring 333b and the ground plug ring 333c.

Please refer to FIG. 4A and FIG. 4B in sequence. As shown in FIG. 4A, the plurality of conductive traces 340 of the first wire layer 324a connect the outer three circles of the bump backing ring 231, including the ground bump backing ring 231f, the signal bump The bump pads 230 of the backing ring 231e and the signal bump backing ring 231d fan out to the outside of the chip area 350 respectively, and the inner three rings of the bump backing ring 231 include the ground bump backing ring 231c, the power bump backing ring 231b and the signal bump backing ring 231b. Part of the bump pads 230 of the bump pad ring 231a are electrically connected downwards to the second wire layer 324b in FIG. The plug ring 333b and the plug pad 332 of the signal plug ring 333a are fanned out to the outside of the chip area 350 through the conductive trace 342 respectively to the ground plug ring 333c and the plug pad 332 of the signal plug ring 333a .

As shown in FIG. 4A, the conductive trace 340 connected from the bump pad 330 of the ground bump pad ring 331f serves as the ground trace 340a, while the bump pad from the signal bump pad ring 331d or the signal bump pad ring 331e The conductive trace 340 connected by 330 is used as the signal trace 340b, in order to prevent the phenomenon of cross-talk (cross-talk) between the signal trace 340b and other adjacent signal traces 340b, that is, signal interference phenomenon, therefore, the preferred embodiment of the present invention is to arrange the paired grounding traces 340a (non-signal traces) on both sides of the signal traces 340b to be protected respectively, so as to serve as the protection traces of the signal traces 340b In addition, a pair of power traces (not shown) connected to the power terminal can also serve as a guard trace for the signal trace 340b. In addition, there may be one or more signal traces 340b sandwiched between the paired ground traces 340a, as shown in FIG. 4A .

As shown in FIG. 4B, the conductive traces 342 (that is, the ground traces 342a) of the plug pads 332 connected to the ground plug pad ring 333c in pairs can also be respectively configured on the plug pads 332 connected to the signal plug pad ring 333a. The two sides of the conductive trace 342 (that is, the signal trace 342b), that is, a pair of ground traces 340a can be respectively arranged on both sides of at least one signal trace 340b, and are used as protective traces for the signal trace 304b. The phenomenon of crosstalk between the signal trace 342b and other adjacent signal traces 342b is prevented. Likewise, the pair of conductive traces 342 connected to the power supply terminals can also serve as guard traces for the signal trace 342b. It should be noted that the width of the ground trace 342a as the guard trace can be greater than the width of the signal trace 342b, which will help reduce the resistance of the ground trace 342a. Similarly, as shown in FIG. 4A , the width of the ground trace 340 a as the guard trace can also be greater than the width of the signal trace 340 a, which also helps to reduce the resistance value of the ground trace 340 a.

To sum up, the flip chip of the present invention is to group the pads with different functions on the chip, and respectively arrange the pads on the active surface of the chip in a multi-ring arrangement, so as to shorten the reconfiguration circuit of the chip Layer winding length, thereby improving the electrical performance of the chip. In addition, the present invention also designs a flip-chip packaging substrate, which can correspond to the pad layout of the above-mentioned flip-chip, and a plurality of bump pads arranged in a matrix are arranged on the top surface of the substrate, so that large Part of the bump pads with the same function form the same bump pad ring. In addition, pairs of power traces or ground traces can be arranged on both sides of the signal traces to serve as protective traces for the signal traces. , thereby reducing the phenomenon of crosstalk between it and adjacent signal traces, so as to improve the electrical performance of the chip.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any skilled person in the art may make some changes and modifications without departing from the spirit and scope of the present invention. , so the protection scope of the present invention shall prevail as defined by the appended claims.

Claims (11)

1. a chip upside-down mounting type base plate for packaging is characterized in that, comprising:

A plurality of conductor layers, overlapped in regular turn;

A plurality of insulating barriers are disposed at respectively between two adjacent these conductive layers, in order to these conductor layers of electrical isolation, and interlaced superimposed with these conductor layers; And

A plurality of conductive plungers run through these insulating barriers respectively, in order to electrically connecting these conductive layers,

Wherein the top layer person of these conductor layers has a plurality of core power supplys/ground connection bump pads, at least one signal projection gasket ring, at least one power supply projection gasket ring and at least one ground connection projection gasket ring, wherein this signal projection gasket ring, this power supply projection gasket ring and this ground connection projection gasket ring are the center with these core power supply/ground connection bump pads, and be the periphery that concentric annular is distributed in these core power supply/ground connection bump pads

The periphery of wherein at least one this signal projection gasket ring disposes at least one non-signal projection gasket ring,

Wherein at least one this conductor layer has at least one signal traces (signal trace) and at least one protection trace (guard trace), and this protection trace is equipped on the adjacent position of this signal traces.

2. chip upside-down mounting type base plate for packaging as claimed in claim 1 is characterized in that: this signal projection gasket ring is made up of a plurality of bump pads, and these bump pads more than 50 percent are the signal bump pads.

3. chip upside-down mounting type base plate for packaging as claimed in claim 1 is characterized in that: this signal projection gasket ring is made up of a plurality of bump pads, and these bump pads are the multilayer annular arrangement.

4. chip upside-down mounting type base plate for packaging as claimed in claim 1 is characterized in that: this power supply projection gasket ring is made up of a plurality of bump pads, and these bump pads more than 50 percent are the power supply bump pads.

5. chip upside-down mounting type base plate for packaging as claimed in claim 1 is characterized in that: this power supply projection gasket ring is made up of a plurality of bump pads, and these bump pads are the multilayer annular arrangement.

6. chip upside-down mounting type base plate for packaging as claimed in claim 1 is characterized in that: this ground connection projection gasket ring is made up of a plurality of bump pads, and these bump pads more than 50 percent are the ground connection bump pads.

7. chip upside-down mounting type base plate for packaging as claimed in claim 1 is characterized in that: this ground connection projection gasket ring is made up of a plurality of bump pads, and these bump pads are the multilayer annular arrangement.

8. chip upside-down mounting type base plate for packaging as claimed in claim 1 is characterized in that: this protection trace is a power trace.

9. chip upside-down mounting type base plate for packaging as claimed in claim 1 is characterized in that: this protection trace is the ground connection trace.

10. chip upside-down mounting type base plate for packaging as claimed in claim 1 is characterized in that: this non-signal projection gasket ring is a power supply projection gasket ring.

11. chip upside-down mounting type base plate for packaging as claimed in claim 1 is characterized in that: this non-signal projection gasket ring is a ground connection projection gasket ring.

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