CN1178009A - Delay time measurement method and pulse generator for delay time measurement - Google Patents

Abstract

A method for accurately measuring the delay time of a signal path(10) constituted by an IC of a CMOS structure in a state which is the same as, or approximate to, the actual operation state. A loop oscillation circuit including the signal path (10) is constittuted, and is brought into a loop oscillation state by feeding a start pulse ST to the circuit. An interpolation pulse P1 having a frequency which is the same as, or approximate to, the frequency of the pulse signal propagated with the signal path is in an actual operation state, is inserted, this interpolation pulse P1 and the loop oscillation signal PLO are fed to the signal path, and the signal path is brought into the substantially same temperature state as that of the actual operation state. The cycle of the loop oscillation signal PLO is measured under this state so as to measure the delay time of the signal path.

Description

Delay time measurement method and delay time measurement pulse generator

The present invention relates to a delay time measurement method suitable for measuring the delay time of signals transmitted in each signal path in a device with multiple signal paths, and in particular to a method for making each signal path in exactly the same state as the actual working state An actual delay time measurement method for measuring the delay of the signal path in a state or a state close thereto, and a pulse generating device for delay time measurement used for implementing the method.

For example, in an IC test device (called IC tester) for testing various semiconductor integrated circuits (hereinafter referred to as IC), a test signal of a prescribed pattern is applied to each input terminal of the IC under test (tested IC), And compare its response output signal with the expected value signal, and generate a bad (FAIL) signal whenever the two signals are inconsistent, and judge whether the tested IC is a defective product based on the generated bad signal. Therefore, at least as many test signal supply paths as the number of input terminals of the IC to be tested, that is, signal paths, are provided on the IC testing apparatus. The IC testing device has a structure that can simultaneously perform tests on 16, 32, 64 ICs to be tested, and can test a large number of ICs in a short time. Therefore, in practice, several hundred channels of signal paths are provided in an IC tester.

However, the phase of the test signal of a predetermined pattern supplied to each input terminal of the IC under test needs to be adjusted to a desired phase according to the purpose of the test. For this purpose, the delay times in the signal paths of the respective test signals must be provided as known values. Moreover, it is required that signal paths of all test signals preferably have consistent delay times (the same). Therefore, in the field of IC test equipment, the delay time of each test signal supply path is regularly measured, and the adjustment work of eliminating the error of the delay time based on the measurement result to achieve the same delay time is performed in the field of IC test equipment.

Not limited to IC test equipment, in an electronic device or an integrated circuit having a structure in which a signal (pulse) such as a clock signal or the like is passed through each of a plurality of signal paths to a circuit or element (part) of the subsequent stage, or In a test device or various measurement devices that test electronic components or components other than ICs that also have multiple signal paths, it is also necessary to measure the delay time of the signal transmitted in each signal path, and based on the measurement results Adjusting the delay time by eliminating the error of the delay time to achieve the same delay time, or adjusting the delay time by supplying a signal with a predetermined phase to a subsequent circuit or element.

In this way, the operation of eliminating the error of the delay time of each signal path to adjust to the same delay time, or the operation of adjusting the delay time so that a signal is supplied with a predetermined phase is generally called skew adjustment.

An example of a conventional delay time measurement method will be described with reference to FIG. 3 . FIG. 3 shows a circuit configuration in which a delay time measuring device 20 used for implementing the delay time measuring method is connected to one signal path 10 . Usually, each signal path 10 is composed of a signal path 11 connected in series with a plurality of logic elements and a variable delay 12 inserted in one path of the signal. The variable delay 12 is provided for adjusting the delay time of the signal path 10 . In various measuring devices, the signal path 10 can be regarded as one of a plurality of signal paths for supplying a clock signal (time stamp signal) from a clock signal generator to the device under test, for example. In addition, in an IC testing device, it can be regarded as one of a plurality of signal paths for supplying a test signal of a predetermined pattern from a pattern generator to an IC to be tested.

To determine the delay time of the signal path 10 , a delay time measuring device 20 is connected to the input 14 of the signal path 10 . The output end 13 of signal path 10 is connected on the delay time measuring device 20 by connecting path 21, forms following loop: Signal path 10→its output end 13→connecting path 21→delay time measuring device 20→the input end of signal path 10 14. The delay time measuring device 20 is composed of a start pulse generator 22 for supplying a loop oscillation start pulse ST to the signal path 10, and a counter 23 for measuring the period of the pulse transmitted in the loop.

Next, a delay time measurement method will be described. If a start pulse ST is input from the start pulse generator 22 to the input 14 of the signal path 10 , the start pulse ST is output to the output 13 after a delay time τ seconds generated by the signal path 10 has elapsed. If the delay time of the connection path 21 is sufficiently small to be negligible compared with the delay time of the signal path 10 , then the pulse transmitted on the signal path 10 will be fed back to the input terminal 14 after τ seconds. The fed back pulse is output to the output terminal 13 of the signal path 10 after τ seconds, and then fed back to the input terminal 14 . As shown in FIG. 4 , the loop including the signal path 10 becomes a loop oscillation state whose period is the delay time τ that the signal path 10 has through such repetitions. The counter 23 measures the period of the loop oscillation signal P _LO and finds the delay time τ of the signal path 10 .

In the conventional delay time measuring method, if the delay time τ of the signal path 10 is short and the frequency of the loop oscillation signal P _LO is close to the frequency of the actual operation of the signal path 10 (hereinafter referred to as actual operation), then It is possible to measure the delay time closest to the delay time of the real-time signal path. However, since miniaturization and low power consumption tend to be required recently, MOS-structured ICs (MOS·IC), especially CMOS (complementary MOS) tend to be used in circuits such as various measurement devices and test devices. structure IC. Since ICs with a CMOS structure consume little power and can achieve a high degree of integration, there is an advantage that miniaturization can be achieved.

However, since the transmission delay time of the signal in the consumable path or circuit constituted by a CMOS-structured IC is relatively long, when the above-mentioned signal path 10 is constituted by a CMOS-structured IC, if the delay time τ is measured using the The above existing delay time measurement method makes the loop including the signal path 10 perform loop oscillation, and the loop oscillation frequency is a relatively low frequency.

As an example, when the circuit from the generation of the waveform of the test signal of the specified pattern in the IC test device to the supply of the test signal to the terminal of the IC under test is composed of a CMOS structure IC, the delay time is about 100ns . If the delay time is 100ns, the loop oscillation frequency is 1/100ns=10MHz. On the other hand, the frequency of the test signal was set to a high frequency of about 100 MHz in the IC tester. Therefore, a large difference arises between the frequency at which the loop oscillates and the number of frequencies in actual operation.

In various measurement devices or electronic devices, for example, when a high-frequency time scale (clock) signal is used, if the signal path to which the time scale signal is supplied is formed by an IC with a CMOS structure, the frequency of loop oscillation is different from the actual frequency. There is also a large difference between the frequencies of work.

Another disadvantage of ICs with a CMOS structure is that power consumption varies with operating speed due to the characteristic of dissipating power only when the states of active elements are reversed. For example, when the signal path 10 operating at 100MHz is actually operated, when the delay time is measured by loop oscillation at 1/10 of its frequency, that is, 10MHz, since the power consumption at 100MHz and 10MHz is different, the IC internal The temperature is a temperature different from the actual working time. Since the delay time τ of an IC having a CMOS structure varies with the temperature inside the IC, there is a disadvantage that an accurate delay time cannot be measured in real operation.

A first object of the present invention is to provide a delay time measuring method capable of measuring a delay time substantially the same as that of a signal path in an actual operating state.

A second object of the present invention is to provide a pulse generator for delay time measurement used for carrying out the delay time measurement method of the present invention.

In order to achieve the above-mentioned first object, according to the delay time measurement method of the present invention, a circuit oscillation circuit including a signal path for which delay time should be measured is constituted, and in the period of the oscillation signal of the circuit oscillation circuit, the When the signal path is in a real working state, the frequency of the signal transmitted in the signal path is equal to or close to that of the signal, and the oscillating signal and the signal inserted in the period of the oscillating signal are transmitted in the signal path The signal path is in substantially the same state as the actual working state, and the oscillation signal of the loop oscillation circuit is taken out and its cycle is measured, and the measured cycle is used as the delay time of the signal path.

In a preferred embodiment, said signal path is formed by an IC of CMOS structure and is inserted in the period of said loop oscillator signal with the The frequency of the signal is set equal to the insertion pulse.

And, the number of insertion pulses inserted in the cycle of the loop oscillation signal is preset in the memory, and if the counter counts one more insertion pulse than the set number of insertion pulses, the counter generates an output signal, and measure the delay time of the signal path through the period of the output signal of the counter.

In order to achieve the above-mentioned second object, according to the present invention, the delay time measurement pulse generating device used for implementing the delay time measurement method includes: a start pulse generator, which generates a signal path for including the delay time that should be measured. A loop oscillation circuit performs a loop oscillation start pulse; a synchronous oscillation circuit oscillates synchronously with the loop oscillation signal of the loop oscillation circuit, and causes the The frequency of the pulse signal is equal to or a pulse signal with a frequency close to it oscillates within the cycle of the loop oscillating signal; the memory stores the number of pulse signals that the synchronous oscillating circuit oscillates within the cycle of the loop oscillating signal; the counter, for The synchronous oscillating circuit counts the number of pulse signals oscillating within the period of the loop oscillating signal; and the gate circuit, the counter oscillates only with the value stored in the memory within the period of the loop oscillating signal After counting the number of pulse signals, if one more pulse signal is counted, the oscillation of the synchronous oscillation circuit is stopped; the pulse extractor is fed back from the loop oscillation signal transmitted in the signal path and in the In the pulse train formed by the pulse signal oscillating within the cycle of the loop oscillating signal, only the loop oscillating signal is taken out; the controller returns the counter to the to the initial state, and restarts the oscillation of the synchronous oscillation circuit.

According to the delay time measuring method of the present invention, the signal path for which the delay time is to be measured is substantially the same as the actual operating state, and the delay time of the signal path is measured in the same operating state as the actual operating state. Therefore, it is possible to obtain an accurate delay time of the signal path that is substantially equal to the delay time in an actual operating state.

Furthermore, according to the delay time measuring pulse generator of the present invention, the signal path can be brought into the same state as the actual operating state with a relatively simple circuit. Therefore, the delay time measuring method according to the present invention is easily realized.

Brief description of the attached drawings:

Fig. 1 is a block diagram showing a circuit configuration of a pulse generating device for delay time measurement used for implementing the delay time measurement method of the present invention;

Fig. 2 is a timing chart for explaining the operation of the pulse generating device for delay time measurement shown in Fig. 1;

Fig. 3 is a block diagram showing the circuit structure of the delay time measuring device used for implementing the existing delay time measuring method;

Fig. 4 is a timing chart for explaining the operation of the delay time measuring device shown in Fig. 3 .

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 .

FIG. 1 shows a circuit configuration in which a delay time measuring pulse generator 30 used for implementing the delay time measuring method of the present invention is connected to one signal path 10 . Also in this embodiment, like the signal path 10 shown in FIG. 3 , each signal path 10 is constituted by a signal path in which a plurality of logic elements are connected in series and a variable delay inserted in the signal path. In addition, in various measurement circuits, each signal path 10 can be regarded as one of a plurality of signal paths for supplying a time stamp signal (time stamp signal) from a time stamp signal generating unit to the device under test, for example, and, in the IC In the test device, it can be regarded as one of a plurality of signal paths that supply a test signal of a predetermined pattern from the pattern generator to the IC under test.

In order to implement the delay time measurement method according to the present invention, the delay time measurement is connected to the input terminal 14 of the signal path 10 with the pulse generating device 30, and the frequency of the signal transmitted to the signal path 10 is the same as or close to it when the actual operation is performed. pulse.

Since the output end 13 of the signal path 10 is connected to the delay time measurement pulse generator 30 through the connection path 21, the following loop is formed: signal path 10 → its output end 13 → connection path 21 → delay time measurement pulse Generator 20 → input 14 of signal path 10 .

Delay time measurement pulse generating device 30 includes: a start pulse generator 35, which generates a start pulse ST for loop oscillation; a counter 41, which inputs a loop oscillation signal P _LO fed back by a connection path; a controller 42, which controls the counter 41; AND gate circuit 31, the loop oscillation signal P _LO fed back through the connection path 21 is provided to the non-inversion input end, and the output of the counter 41 is provided to the inversion input end; memory 38, which can be inserted into the loop oscillation cycle The number of the insertion pulse _PI ; Synchronous oscillation circuit 36, provides the output of AND gate circuit 31 and the output of start pulse generator 35 to it; Counter 39, provides the output of described synchronous oscillation circuit 36 to it; Controller 40 , used to preset the value of the insertion pulse P _I stored in the memory 38 to the counter.

The synchronous oscillation circuit 36 includes: an OR gate circuit 32, which provides the output of the AND gate circuit 31, the output of the start pulse generator 35, and the output of the synchronous oscillation circuit 36; The output undergoes waveform shaping; the AND gate circuit 34 inputs the output of the pulse shaping circuit 33 and the output of the counter 39 to it. The output of AND circuit 34 is provided to input 14 of signal path 10 . Thus, the AND gate circuit 31 and the synchronous oscillator circuit 36 form part of a feedback loop, whereby the signal path 10, the connection path 21, the AND gate circuit 31 and the synchronous oscillator circuit 36 (OR gate circuit 32, pulse shaping circuit 33 and AND gate Circuit 34) constitutes a loop oscillation circuit.

Therefore, when the start pulse ST is supplied from the start pulse generator 35 to the synchronous oscillation circuit 36, the _loop oscillation starts, and as shown in A in FIG. A determined period repeatedly transmits a loop oscillation state in said loop.

In the delay time measuring method according _to the present invention, as _shown in B in _FIG. . The frequency of the insertion pulse _PI is selected to be equal to or close to the frequency of a signal transmitted in a certain signal path 10 in the working state. Therefore, the frequency of the insertion pulse _PI may vary from device to device, but it is a known value.

If an insertion pulse P _I having a frequency equal to or close to the frequency of the signal transmitted in the signal path 10 in the real operating state is inserted into the period τ of the loop oscillation signal P _LO , the insertion pulse P _I and the loop The oscillating signal P _LO is transmitted together in the signal path 10 . Therefore, the signal path 10 is in a state that is the same as or close to the real working state. As a result, the power consumed in the signal path 10 is substantially the same as the power consumed during actual operation, so the temperature change of the signal path 10 is also substantially the same as during actual operation. Therefore, according to the delay time measurement method of the present invention, it is possible to measure the delay time of the signal path 10 under the temperature fluctuation state substantially the same as the temperature fluctuation state of the signal path 10 in the actual operating state. Therefore, if the signal path 10 is made of CMOS Even with the IC configuration of this structure, it is possible to measure an accurate delay time that is substantially the same as the delay time of the signal path 10 in actual operation.

What described synchronous oscillating circuit 36 represented is the situation that constitutes synchronous oscillating circuit by the loop, and described loop is directly fed back to the feedback path 37 of OR gate circuit 32 by the pulse that will obtain from the output of AND gate circuit 34, OR gate circuit 32, Pulse shaping circuit 33, and AND gate circuit 34. Thus, through the short loop comprising the feedback path 37, an insertion pulse _PI is generated at a frequency equal to or close to the frequency of the signal transmitted in the signal path 10 in the real operating state. Then, the pulse shaping circuit 33 performs an operation of shaping the waveform of the input pulse into a pulse of a predetermined amplitude and amplifying the peak value of the pulse to a predetermined value. The loop oscillation operation is maintained by this amplitude amplification operation.

In the memory 38 of the delay time measuring pulse generator 30, the number of insertion pulses P _I inserted into the oscillation period τ of the loop oscillation circuit including the signal path 10 is stored. Although the oscillation period τ of the loop oscillation circuit is determined by measurement, the measured value may be an approximate value. If the number of insertion pulses _PI inserted into the oscillation period τ is N, the value N is set to the memory 38 . Said value N is initially preset into the counter 39 by a start pulse ST under the control of the controller 40 . The counter 39 counts the insertion pulse _PI which is the oscillation output of the synchronous oscillation circuit 36, and subtracts 1 (-1 ₎ from the preset value every time the insertion pulse PI is input. If the preset value of the counter 39 becomes 0, and after the value of the inserted pulse _PI counted coincides with the numerical value N set in the memory, the following pulse is counted, then the output of the counter 39 falls to L (low level). logic. As a result, the AND gate 34 is in an OFF state, and thus the oscillation operation of the synchronous oscillation circuit 36 is temporarily stopped.

The loop oscillation signal P _LO fed back from the signal path 10 through the connection path 21 is input to the controller 40 through the AND circuit 31 , and the value N stored in the memory 38 is preset again under the control of the controller 40 into counter 39. By presetting the value N, the output of the counter 39 returns to H (high level) logic, so the AND circuit 34 is turned on (ON) (enable state), and the loop oscillation signal P _LO is passed. As a result, the oscillation operation of the synchronous oscillation circuit 36 is restarted. The AND gate circuit 31 cooperates with the counter and controller 42 to extract only the loop oscillation signal P _LO from the pulse train fed back through the connection path 21 . That is, an operation is performed to extract the first pulse from a pulse train consisting of a loop oscillation signal P _LO and a subsequent insertion pulse _PI train. Like the counter 39 , the counter 41 is preset to the value N stored in the memory 38 by the values of the start pulse ST and the oscillation signal P _LO under the control of the controller 38 . If the counter 41 is preset to the value in the memory 38 , the counter 41 becomes H logic, and thus L logic as its inverted output is supplied to one input terminal of the AND circuit 31 . As a result, the AND gate circuit 31 is turned off, preventing the passage of the pulse train following the loop oscillating signal P _LO .

The counter 41 is decremented from the preset value N by 1 (-1) every time the insertion pulse _PI fed back via the connection path 21 is input. If the next insertion pulse P _I is counted after the preset value N becomes 0, the output of the counter 41 falls to L logic, so the AND gate circuit 31 is in an open state. Thus, the feedback loop oscillation signal P _LO is input to the controllers 40 and 42 through the AND gate 31 , whereby the counters 39 and 41 are preset. Returning to the open state by said preset AND gate 31 results in the AND gate 31 passing only the loop oscillating signal P _LO . Therefore, by measuring the period τ (C in FIG. 2 ) of the output signal of the counter 39 or 41, the delay time of the signal path 10 can be measured. Since the loop oscillating signal P _LO and the insertion pulse _PI are transmitted in the signal path 10, the signal path 10 becomes substantially the same state as in real operation, so that the loop oscillating signal P _LO shown in C in FIG. The period τ is substantially the same as the delay time of the signal path 10 in real operation. That is, accurate delay time of the signal path 10 can be measured.

And, in the pulse generating device for measuring the delay time, the AND gate 34 is controlled by the counter 39 and the controller 40, and the counter 41 and the controller 42 are additionally set to control the AND gate 31, but the counter 41 and the controller may not be additionally provided. 42, while counter 39 and controller 40 are used concurrently. Also, the synchronous oscillation circuit 36 is used as a loop oscillation circuit, but it goes without saying that synchronous oscillators of other forms or structures may also be used.

As described above, according to the present invention, even when the transmission delay time of the signal path is long and the oscillation frequency of the loop oscillation circuit including the signal path is low, it is possible to transfer the real-time transmission of the signal path to the signal path. The insertion pulse with the same or close frequency of the signal is inserted into the loop oscillation cycle to measure the delay time of the signal path. Therefore, the signal path operates with approximately the same power consumption as the actual operation, and the temperature change is also substantially equal. As a result, even when the signal path is formed by a CMOS IC, the delay time is greatly affected by temperature changes, and the signal path (IC chip) can be measured under the same temperature state as in actual operation. Therefore, there is a significant advantage that an accurate delay time without error can be determined.

Claims (6)

1. One kind time delay assay method, constitute the oscillation circuit circuit that comprises the signal path that to measure time delay, and the cycle of the oscillator signal by measuring described oscillation circuit circuit measure the time delay of described signal path, it is characterized in that, described time delay assay method, in the cycle of the oscillator signal of described oscillation circuit circuit, insert and be under the positive activity state at described signal path, the frequency of the signal that in described signal path, transmits equate or with the signal of its close frequencies, and described oscillator signal transmitted in described signal path with signal in the cycle that is inserted in described oscillator signal and make described signal path be in identical with the positive activity state in fact state, take out the oscillator signal of described oscillation circuit circuit and measure its cycle, with time delay in described cycle of recording as described signal path.
2. 2. time delay as claimed in claim 1, assay method is characterized in that, described signal path is that the IC by the CMOS structure constitutes.
3. 3. time delay as claimed in claim 1 assay method, it is characterized in that, the interior signal of cycle that is inserted in described oscillator signal is a pulse signal, the quantity of the described pulse signal that inserts is set in advance in the storer, when counting down to when Duoing one pulse signal, measure from time delay in cycle of the signal of counter output as described signal path than the pulse signal of the quantity of described setting.
4. 4. time delay as claimed in claim 1, assay method is characterized in that, in various determinators, described signal path is to provide a plurality of signal paths of timing signal one from the timing signal generating unit to determined chip.
5. 5. time delay as claimed in claim 1, assay method is characterized in that, in the IC test unit, described signal path is from mode generator to a plurality of signal paths of the test signal that supplied a pattern by test IC.
6. 6. pulse generator for measuring delay time for use in said, it is characterized in that, described pulse generator for measuring delay time for use in said is to use for implementing assay method time delay described in each of claim 1 to 5, comprise: the beginning pulse producer, generation is used to make the oscillation circuit circuit that comprises the signal path that should measure time delay to carry out the beginning pulse of oscillation circuit; The synchronized oscillation circuit, be synchronized with the oscillation circuit signal of described oscillation circuit circuit and vibrate, and make and equate with the frequency that is in the pulse signal that under the positive activity state, in described signal path, transmits at described signal path or in the cycle of described oscillation circuit signal, vibrate with the pulse signal of its close frequencies; Storer, the quantity of storing the pulse signal that described synchronized oscillation circuit vibrates in the cycle of described oscillation circuit signal; Counter, the quantity of the pulse signal that described synchronized oscillation circuit was vibrated in the cycle of described oscillation circuit signal is counted; Gate circuit, described counter if count a pulse signal again, then stop the vibration of described synchronized oscillation circuit after the quantity of the pulse signal that only vibrates with the numerical value that is stored in the described storer is counted in the cycle of described oscillation circuit signal; The pulse extractor from the train of impulses that the described oscillation circuit signal of the feedback by transmitting and the described pulse signal that vibrates are formed, only takes out described oscillation circuit signal in the cycle of described oscillation circuit signal described signal path; Controller makes described counter turn back to original state by the described oscillation circuit signal that takes out by described pulse extractor, and restarts the vibration of described synchronized oscillation circuit.

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