CN117807936A - A method to quickly package Vivado IP core based on LabVIEW - Google Patents

Abstract

The invention belongs to the field of computer technology, and specifically relates to a method of quickly packaging Vivado IP core based on LabVIEW, which includes the following steps: S1: install the LabVIEW FPGA IP Export Utility plug-in, and download the LabVIEW 2020FPGA Module and LabVIEW 2020FPGA Compilation Tool for Vivado; S2: install Device terminal driver, S3: Create and compile VI for IP export, S4: Select compilation under New in the program specification, and fill in the production name and top-level VI in turn, S5: Select Export VI to Netlist in the new program specification File, S6: Export the suffix .dcp and .vhd files, and verify whether it is successful on the Vivado software. In the above S1, before using the LabVIEW FPGA IP Export Utility, you need to install the LabVIEW FPGA module first. On the one hand, the invention reduces the requirements for developers to master the ability, that is, they only need to master the graphical programming of LabVIEW, without the need for proficient use of hardware description languages and high-level synthesis. On the other hand, it saves the time of verifying the correctness of the IP core. Time resources, that is, we can export the IP core after successfully compiling and running in LabVIEW.

Description

LabVIEW-based method for rapidly packaging VivadoIP core

Technical Field

The invention belongs to the technical field of computers, and particularly relates to a method for rapidly packaging VivadoIP cores based on LabVIEW.

Background

FPGA (Field Programmable Gate Array) is a programmable logic device, its basic principle is that it is formed by programmable logic unit (Look-Up Table, LUT) and programmable connection line, LUT can be programmed according to user-defined logic function, and the connection line can connect every LUT according to need in order to realize the required circuit function, while designing, users can use Hardware Description Language (HDL) or graphic design tool to define the required circuit function, then burn the circuit function designed into FPGA chip, realize the required digital circuit function;

the application field of the FPGA is very wide, including the fields of aerospace, communication, artificial intelligence, digital signal processing and the like, the FPGA is widely applied by virtue of the advantages of high performance and high reliability, high chip integration level, strong safety, strong privacy protection and the like, and although the FPGA is widely applied in the field of computer application, the FPGA also has some challenges, wherein the most outstanding difficulty is that the development difficulty is high, the hardware design and the FPGA programming technology need to be mastered, and the programming model and the development tool of the FPGA are complex due to the programmability and the reconfigurability of the FPGA, so that a higher technical level is required;

in the FPGA development process, a development tool named Vivado is most popular, which is an Integrated Design Environment (IDE) introduced by Xilinx (Xilinx) company for designing, implementing and verifying systems based on Xilinx FPGA and SoC. Vivado provides various design methods including High Level Synthesis (HLS), hardware Description Language (HDL), IP core integration, graphical editing, etc., wherein an IP core is a pre-designed, reusable, verified circuit function module that can be obtained or created by an IP core catalog or IP core generator of Vivado. The IP core can greatly improve the development efficiency and quality of the FPGA, because the IP core can avoid the repeated design of the same or similar circuit functions, and can also utilize the existing optimization and verification technology;

however, there are also some problems and limitations in designing IP cores in Vivado, mainly the following:

the design of the IP core in Vivado may involve different levels of abstraction, including High Level Synthesis (HLS) and Hardware Description Language (HDL), and a developer needs to be skilled in both techniques and languages, which has high requirements on the developer's ability;

designing an IP core in Vivado requires comprehensive simulation and verification of the IP core, which may consume a significant amount of time and resources. Ensuring correctness, performance and fault tolerance are key challenges in the design process, and have high requirements on the technical level of developers;

therefore, how to simplify and optimize the IP core design in Vivado, and improve the efficiency and quality of the developer is a problem to be solved.

Disclosure of Invention

The invention aims to provide a method for rapidly packaging a VivadoIP core based on LabVIEW, which reduces the requirement on the mastering capability of a developer, namely only the graphic programming of LabVIEW is mastered, and the proficiency application of hardware description language and high-level synthesis is not needed, and saves the time resource for verifying the correctness of the IP core, namely, the IP core can be exported after the compiling operation in LabVIEW is successful.

The technical scheme adopted by the invention is as follows:

a method for rapidly packaging VivadoiP cores based on LabVIEW comprises the following steps:

s1: installing LabVIEW FPGA IP Export Utility plug-ins and downloading LabVIEW 2020FPGA Module and LabVIEW 2020FPGA Compilation Tool for Vivado;

s2: installing equipment terminal drive;

s3: creating and compiling a VI for IP export;

s4: selecting a newly built compatibility in the program specification, and sequentially filling in a production name and a top layer VI;

s5: selecting Export VI to Netlist File in the new program specification;

s6: the exported suffixes are the.dcp and. vhd files, and verification is performed on the Vivado software for success.

In the step S1, before LabVIEW FPGA IP Export Utility, a LabVIEW FPGA module needs to be installed.

The LabVIEW FPGA IP Export Utility includes the following two options:

1. LabVIEW FPGA Netlist Export Utility: exporting an FPGA algorithm into an encrypted netlist;

2. LabVIEW FPGA VHDL Export Utility: the FPGA algorithm is exported as an encrypted netlist or plaintext VHDL.

In S2, the device terminal driver searches for and downloads in NIPackage Manager.

In the step S3, when creating and compiling the VI, the input line and the output line of the module explicitly need to be exported, and for the control connected with the input line and the output line, the right click selects and outputs the corresponding input control/display control.

In S5, if the Export VI to Netlist File option is not available, it is checked whether the activation state of FPGA IP Export Utility in NI License Manager is activated, which includes the following states:

a: if the FPGA IP Export Utility activation state in NI License Manager is not activated, activating is required;

b: if the activation state of FPGA IP Export Utility in NI License Manager is activated, the refresh is completed.

In the step S6, whether the verification is successful or not is verified on the Vivado software, wherein the verification comprises the following states:

c: if the verification on the Vivado software is unsuccessful, returning to S3, and compiling the VI again;

d: and if the verification is successful on the Vivado software, ending.

The Export VI to Netlist File last exported file is at the following locations:

x \NIFPGA\compatibility \project-name > _ < target-name > _ < build-specific name > _ < unique-string > \source_files, where X is the driver location where LabVIEW is installed.

The invention has the technical effects that:

the invention reduces the requirement on the mastering capability of a developer, namely only the graphic programming of LabVIEW is mastered, and the technical application of hardware description language and high-level synthesis is not needed, and saves the time resource for verifying the correctness of the IP core, namely, the IP core can be exported after the compiling operation in LabVIEW is successful.

Drawings

FIG. 1 is a flow chart of a LabVIEW-based fast encapsulating IP core in the present invention;

FIG. 2 is an overview of a specific example item in the present invention;

fig. 3 is a top level VI design flow diagram in accordance with the present invention.

Detailed Description

The present invention will be specifically described with reference to examples below in order to make the objects and advantages of the present invention more apparent. It should be understood that the following text is intended to describe only one or more specific embodiments of the invention and does not limit the scope of the invention strictly as claimed.

As shown in fig. 1-3, a method for quickly packaging VivadoIP cores based on LabVIEW, which is a graphical programming language and development environment developed by american national instruments corporation (National Instruments, abbreviated as NI). LabVIEW uses a graphical programming language to create programs by dragging, connecting icons and lines. This graphical programming approach enables a user to intuitively represent and understand the functionality of the program. The graphical interface allows the user to construct a virtual instrument, simulate the functions of an actual instrument, and be used for data acquisition, analysis and visualization, which means that LabVIEW can be integrated with various hardware devices, including sensors, data acquisition cards, instruments and the like. In general, labVIEW is a powerful engineering tool, and the design and development processes of a complex system are simplified in a graphical programming mode, and the detailed description is omitted again;

whereas the Vivado general workflow is as follows:

1. creating engineering: creating a new FPGA project in the Vivado, and selecting a target FPGA model.

2. Design input: hardware description language writing (Verilog, VHDL) or High Level Synthesis (HLS) was performed using Vivado IDE.

3. IP integration: add reusable IP cores, or design custom IP cores.

4. And (3) design synthesis: design synthesis using Vivado maps the design to a logic gate level.

5. The realization is as follows: vivado performs layout, timing analysis and generates a bit stream file.

6. Debugging and verification: the design is verified and debugged using the Vivado debug tool.

7. Generating a bit stream file: a bitstream file is generated for configuring the FPGA.

8. Downloading configuration: and downloading the bit stream file to the target FPGA to complete configuration.

Because the graphic programming of LabVIEW can enable a beginner to quickly get on hand, the method for developing the IP core comprises the following steps:

s1: NIPackage Manager, a download is searched and LabVIEW FPGA IP Export Utility plug-in is installed, and a configuration environment is required while the plug-in is installed, namely, a LabVIEW 2020FPGA Module and a LabVIEW 2020FPGA Compilation Tool for Vivado 2019.1 (the version corresponds to the used Vivado version) are required to be downloaded. LabVIEW FPGA IP Export Utility can be used to derive LabVIEW FPGA-written algorithms for deployment on third party hardware, for deriving LabVIEW FPGA-written algorithms as VHDL source code or netlist;

notably, the export tool 2021 version after 5 months 1 does not support the win7 system, requiring the first installation of LabVIEW FPGA modules for use LabVIEW FPGA IP Export Utility;

LabVIEW FPGA IP Export Utility two options are provided:

1. LabVIEW FPGA Netlist Export Utility: deriving an FPGA algorithm into an encrypted netlist (.dcp)

2. LabVIEW FPGA VHDL Export Utility: exporting the FPGA algorithm as an encrypted netlist or plaintext VHDL (. Vhd and RTL style);

s2: installing a device terminal driver, searching for download device terminal drivers (device terminal drivers viewable on the project overview page) in NIPackage Manager, e.g., compactRIO and Drivers;

s3: creating and compiling a VI for IP export, in compiling the VI, taking care of definitely needing to export input lines and output lines of a module, for a control connected to the lines, right clicking to select and output a corresponding input control/display control for avoiding format mismatch, wherein the compiling option of the VI further comprises a clock frequency for matching the frequency of the clock;

s4: clicking a program generation specification under an FPGA terminal by a right button, selecting a newly built program specification, sequentially filling in a production name and a top layer VI, and selecting your top layer VI in source files;

s5: right clicking on the newly created specification selects Export VI to Netlist File from the new program specifications, i.e., exports IP in encrypted netlist mode;

if there is no Export VI to Netlist File option, it is checked whether the activation state of FPGA IP Export Utility in NI License Manager is activated, including the following states:

a: if the FPGA IP Export Utility activation state in NI License Manager is not activated, activation is required;

b: if the activation state of FPGA IP Export Utility in NI License Manager is activated, refreshing is performed;

export VI to Netlist File the final export file may be found at the following locations:

X:\NIFPGA\compilation\<project-name>_<target-name>_<build-specname>_<unique-string>\source_files；

wherein X is the drive location where LabVIEW is installed;

s6: the exported suffixes are the dcp file and the vhd file which are the design and the comprehensive file required by the IP core, and whether the verification is successful or not is carried out on Vivado software;

verifying on Vivado software whether it is successful includes the following states:

c: if the verification on the Vivado software is unsuccessful, returning to S3, and compiling the VI again;

d: if the verification is successful on the Vivado software, the process is ended.

In the above step, the LabVIEW version used is 2020, and downloading 2020 version and above (2020, 2021, 2022Q3, 2023Q 1) is recommended.

The method reduces the capability requirement of an FPGA developer, the developer can design the IP core of Vivado only by using the graphic programming of LabVIEW, and the LabVIEW expresses the program structure by using the graphic programming language in a mode of icons and connecting wires, so that the program design is more visual and easy to understand, and a more friendly development environment is provided for engineers and beginners who do not have the advantages of traditional text programming;

the LabVIEW programming is mainly used in the work, the flow is simple, the resources are rich, the development environment is mature, and the operation is easier than that of Vivado software. LabVIEW is a tool that has been developed for virtual instrument design, providing a rich library of virtual instruments that allows users to conveniently simulate, test and analyze experiments. This is very advantageous for laboratory and test applications. And it provides a large number of advanced kits for use in a variety of fields of signal processing, image processing, control system design, and the like. These kits may accelerate the development process, particularly for applications requiring complex algorithms and analysis. And a higher hardware abstraction layer is provided, so that a user can develop without deep knowledge of the bottom details of the FPGA. This reduces the threshold for learning and development for some beginners and rapid prototyping.

The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention. Structures, devices and methods of operation not specifically described and illustrated herein, unless otherwise indicated and limited, are implemented according to conventional means in the art.

Claims (8)

1. A method of quickly packaging VivadoIP core based on LabVIEW, which is characterized by including the following steps: S1: Install the LabVIEW FPGA IP Export Utility plug-in, and download the LabVIEW 2020FPGA Module and LabVIEW 2020FPGA Compilation Tool for Vivado; S2: Install the device terminal driver; S3: Create and compile VI for IP export; S4: Select compilation under New in the program specification, and fill in the production name and top-level VI in turn; S5: Select Export VI to Netlist File in the new program specification; S6: Export files with .dcp and .vhd suffixes, and verify whether they are successful on the Vivado software. 2. A method of quickly packaging VivadoIP core based on LabVIEW according to claim 1, characterized in that: in the S1, before using the LabVIEW FPGA IP Export Utility, install the LabVIEW FPGA module first. 3. A method of quickly packaging VivadoIP core based on LabVIEW according to claim 2, characterized in that: the LabVIEW FPGA IP Export Utility includes the following two options: 1. LabVIEW FPGA Netlist Export Utility: Export FPGA algorithms into encrypted netlists; 2. LabVIEW FPGA VHDL Export Utility: Export FPGA algorithms into encrypted netlists or plain text VHDL. 4. A method for quickly packaging Vivado IP core based on LabVIEW according to claim 1, characterized in that: in the S2, the device terminal driver is searched and downloaded in the NIPackage Manager. 5. A method of quickly packaging the VivadoIP core based on LabVIEW according to claim 1, characterized in that: when creating and compiling the VI in S3, the input lines and output lines of the module that need to be exported are clearly defined. For the input lines and To output the control connected to the line, right-click and select the corresponding input control/display control to output. 6. A method of quickly packaging VivadoIP core based on LabVIEW according to claim 1, characterized in that: in the S5, if there is no Export VI to Netlist File option, you need to check the FPGA IP Export in the NI License Manager Whether the activation status of Utility is activated, it includes the following status: A: If the activation status of the FPGA IP Export Utility in the NI License Manager is not activated, you need to activate it; B: If the activation status of the FPGA IP Export Utility in the NI License Manager has been activated, just refresh it. 7. A method of quickly packaging the Vivado IP core based on LabVIEW according to claim 1, characterized in that: in the S6, whether the verification on the Vivado software is successful includes the following states: C: If the verification on the Vivado software is unsuccessful, return to S3 and recompile the VI; D: If the verification is successful on the Vivado software, the process ends. 8. A method of quickly packaging VivadoIP core based on LabVIEW according to claim 6, characterized in that: The final export file of the Export VI to Netlist File is at the following location: X:\NIFPGA\compilation\<project-name>_<target-name>_<build-specname>_<unique-string>\source_files, where X is the drive location where LabVIEW is installed.