CN117806812B - A random whitening enhanced PUF extraction system based on information sequence - Google Patents
A random whitening enhanced PUF extraction system based on information sequence Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
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Abstract
The invention discloses an information sequence-based stochastic whitening enhancement PUF extraction system which comprises an upper computer, a first interface module, a second interface module, an input mapping transformation module, an output mapping transformation module, a multi-path selector module and a PUF unit module, wherein the upper computer is connected with the input mapping transformation module through the first interface module and outputs excitation of the upper computer to the input mapping transformation module, the output of the input mapping transformation module is connected with the multi-path selector module, the input end of the multi-path selector module is connected with the PUF unit module, and the multi-path selector module, the output mapping transformation module and the second interface module are connected in sequence and then connected with the input of the upper computer, and the response after the stochastic whitening enhancement processing of the output mapping transformation module is returned to the upper computer. The invention improves the generation quantity of the excitation response and reduces the occupation of resources.
Description
Technical Field
The invention relates to the technical field of information security, in particular to a random whitening enhancement PUF extraction system based on an information sequence.
Background
A Physical Unclonable Function (PUF) refers to inputting a stimulus to a chip and outputting an unpredictable response function using random process variations that are unavoidable in the chip manufacturing process. The PUF circuit is a hardware function realization circuit which depends on chip characteristics, has uniqueness and randomness, and realizes the function of uniquely corresponding to an excitation signal and a response signal by extracting technological parameter deviation which is necessarily introduced in the chip manufacturing process. Because the PUF circuit structures of the same type are identical and the function is deterministic and unique after each PUF circuit is fabricated, another significant feature of PUF circuits is unclonability. The above-mentioned properties of PUF circuits make them useful for constructing security chips and protecting against various attacks.
The existing weak PUF circuit system and extraction method have the defects that the number of stimulus responses extracted from the weak PUF circuit is insufficient and the consumed circuit resources are high.
Disclosure of Invention
In order to solve the problems, the invention provides a random whitening enhancement PUF extraction system based on an information sequence, which utilizes a dynamic linear mapping structure to carry out confusion processing on initial response of a PUF and excitation of an upper computer input FPGA board card, so that the quantity of excitation response is greatly increased, and the expansion of a small quantity of excitation response of a weak PUF is realized.
The invention provides an information sequence-based stochastic whitening enhancement PUF extraction system, which has the following specific technical scheme:
the system comprises an upper computer, a first interface module, a second interface module, a linear mapping module, a multiplexer module and a PUF unit module, wherein the linear mapping module comprises an input mapping transformation module and an output mapping transformation module;
The output of the upper computer is connected with the first interface module, the output of the first interface module is connected with the input mapping conversion module, and the excitation of the upper computer is output to the dynamic input mapping conversion module through the first interface module;
The output of the input mapping transformation module is connected with the multiplexer module, and the input end of the multiplexer module is connected with the PUF unit module;
The output of the multiplexer module is connected with the output mapping conversion module, the output mapping conversion module is connected with the input of the upper computer through the second interface module, and the response after the random whitening enhancement processing of the dynamic output mapping conversion module is returned to the upper computer.
Further, the multiplexer module includes at least one multiplexer, and an output of each multiplexer is connected to an input of the output mapping module.
Furthermore, the multiplexer adopts a multiplexer with a four-out structure and comprises four input ends, and each input end is correspondingly connected with one PUF unit.
Further, the linear mapping module is composed of a weight calculation module and a register module;
when the excitation/response is different, the dynamic linear mapping module can process the excitation/response differently;
The weight calculation module is used for outputting corresponding weight values for different input excitation/response sequences, wherein the weight values are the operation times of the register module.
Furthermore, the register module is formed by cascading a plurality of registers and exclusive-or gates, and the number of the registers is the same as the number of bits of input excitation.
Furthermore, the register module adopts the longest linear feedback shift register sequence to generate a random sequence, and the sequence at a specific position is intercepted by the weight calculation module and input to the multiplexer module.
Further, the operation structure of the linear feedback shift register is as follows:
S0＝S1*g1⊙S2*g2⊙……⊙Sn-2*gn-2⊙Sn-1*gn-1⊙Sn*gn
M0＝{Sn-1,Sn-2,Sn-3,……,S3,S2,S1,S0}
Wherein { S 1,S2,S3,……,Sn-1,Sn } is an initial value in n registers, { g 1,g2,g3,……,gn-1,gn } represents tap selection of a register, g value of a tap register is set to be 1, the rest is 0;S 0, a value fed back to the tail end of a register group when the linear feedback shift register runs each time, and M 0 is a new sequence after the linear feedback shift register runs once.
Further, the weight calculation process of the weight calculation module is as follows:
s1, initializing bit number parameters N=1 and weights and S=0 after the weight calculation module receives N bit excitation data;
s2, judging whether the N-th bit is excited to be 1, if so, executing S=S+N, and simultaneously, adding 1 to the bit number parameter N in an iteration mode, otherwise, executing the next step;
And S3, after all bits are excited in a circulating way, the obtained weight, S and n bit excitation data are transmitted to the register module.
Further, the working process of the register module is as follows:
after n bit excitation data and an S value are input into the register module, respectively storing the n bit data into an n bit register;
m2, selecting data with specific digits in the register to carry out exclusive OR in each clock period, shifting the cascaded register data rightwards, and storing the value after exclusive OR in the register at the leftmost side after shifting;
M3, repeatedly executing the step M2 according to the set first times, deriving the data in all registers to obtain an excitation sequence, and inputting the n bit excitation sequence to the selection ends of the first n/2 multiplexers;
and M4, repeatedly executing the step M2 according to the set second times, exporting the data in all the registers again to obtain a new excitation sequence, and inputting the n-bit excitation sequence to the selection ends of the rear n/2 multiplexers.
Further, the first number is (n-1) ×s, and the second number is S.
The beneficial effects of the invention are as follows:
The invention utilizes dynamic linear mapping transformation to process the traditional weak PUF, solves the problem of insufficient excitation response of the traditional weak PUF, increases the application scene of the weak PUF, and can generate a large number of excitation response based on the system structure of the invention, thereby reducing the occupation of resources in an FPGA board card and reducing the deployment difficulty of the PUF compared with the traditional strong PUF.
Drawings
Fig. 1 is a schematic diagram of the overall architecture of the system.
Fig. 2 is a schematic diagram of a multiplexer module and PUF cell module architecture.
FIG. 3 is a schematic diagram of a register module architecture.
Fig. 4 is a flow chart illustrating the execution of the weight calculation module.
Detailed Description
In the following description, the technical solutions of the embodiments of the present invention are clearly and completely described, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the embodiments of the present invention, it should be noted that, the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship conventionally put in use of the product of the present invention as understood by those skilled in the art, merely for convenience of describing the present invention and simplifying the description, and is not indicative or implying that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used merely for distinguishing between descriptions and not for understanding as indicating or implying a relative importance.
In the description of the embodiments of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed" and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, integrally connected, directly connected, or indirectly connected through an intermediary. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Example 1
The embodiment 1 of the invention discloses a random whitening enhancement PUF extraction system based on an information sequence, as shown in fig. 1, and specifically comprises the following steps:
The system comprises an upper computer, a first interface module, a second interface module, a linear mapping module, a multiplexer module and a PUF unit module;
The first interface module and the second interface module are used for carrying out data interaction between the upper computer and the FPGA board card, and particularly, the first interface module and the second interface module can adopt RS232 serial ports;
The linear mapping module, the multiplexer module and the PUF unit module are integrated on the FPGA board card.
The linear mapping module comprises an input mapping transformation module and an output mapping transformation module;
the input mapping transformation module is used for processing the excitation sequences with small original differences, so that the randomness whitening of the original sequences is enhanced, the differences of the original sequences are enlarged, and the output mapping transformation module is used for increasing the randomness of the response sequences.
In this embodiment, the linear mapping module is composed of a weight calculation module and a register module;
When the stimulus/response is different, the dynamic linear mapping module will process the stimulus/response differently.
The weight calculation module is used for outputting corresponding weight values for different input excitation/response sequences, wherein the weight values are the operation times of the register module.
In this embodiment, the register module is formed by cascade connection of 64 registers and exclusive-or gates, and the number of the registers is the same as the number of bits of input excitation.
Specifically, the register module adopts the longest linear feedback shift register sequence to generate a random sequence, and the sequence at a specific position is intercepted by the weight calculation module and input to the multiplexer module;
the number of bits of the selected registers in this embodiment is 64, 63, 61, 60, and the values in the four registers are exclusive-ored in each clock cycle.
Referring to fig. 3, the operation structure of the linear feedback shift register is as follows:
S0＝S1*g1⊙S2*g2⊙……⊙Sn-2*gn-2⊙Sn-1*gn-1⊙Sn*gn
M0＝{Sn-1,Sn-2,Sn-3,……,S3,S2,S1,S0}
Wherein { S 1,S2,S3,……,Sn-1,Sn } is an initial value in n registers, { g 1,g2,g3,……,gn-1,gn } represents tap selection of a register, g value of a tap register is set to be 1, the rest is 0;S 0, a value fed back to the tail end of a register group when the linear feedback shift register runs each time, and M 0 is a new sequence after the linear feedback shift register runs once.
The output of the upper computer is connected with the first interface module, the output of the first interface module is connected with the input mapping conversion module, and the excitation of the upper computer is output to the dynamic input mapping conversion module through the first interface module;
The output of the input mapping transformation module is connected with the multiplexer module, and the input end of the multiplexer module is connected with the PUF unit module;
The output of the multiplexer module is connected with the output mapping conversion module, the output mapping conversion module is connected with the input of the upper computer through the second interface module, and the response after the random whitening enhancement processing of the dynamic output mapping conversion module is returned to the upper computer.
As shown in fig. 2, in this embodiment, the multiplexer module includes at least one multiplexer, and an output of each multiplexer is connected to an input of the output mapping module.
The multiplexer module consists of n four-out-of-one multiplexers, and the multiplexers consist of 4-bit input ends, 1-bit output ends and 2-bit selection ends;
when the excitation signal received by the selection end of the multiplexer is 00, the PUF signal of the first input end of the multiplexer is output from the output port, when the excitation signal received by the selection end of the multiplexer is 01, the PUF signal of the second input end of the multiplexer is output from the output port, when the excitation signal received by the selection end of the multiplexer is 10, the PUF signal of the third input end of the multiplexer is output from the output port, and when the excitation signal received by the selection end of the multiplexer is 11, the PUF signal of the fourth input end of the multiplexer is output from the output port.
In this embodiment, each input end of the multiplexer is correspondingly connected to one PUF unit;
specifically, the PUF cell module is configured to generate an initial response, and the multiplexer module is composed of n×4 PUF cells, where the PUF cells may be any weak PUF cells, including but not limited to a PUF, an SRAM PUF, where the PUF cells are independent of each other and do not affect each other.
Based on the register module structure of the present embodiment, the workflow of the system is described as follows:
firstly, powering up an FPGA board card, and generating initial response by a PUF unit module;
The upper computer inputs excitation to the FPGA through an RS232 serial port, and an input mapping module for dynamically inputting an excitation input value through the serial port;
As shown in fig. 4, 64bit excitation data is input to the weight calculation module, and bit number n=1 and weight sum s=0 are initialized;
judging whether the N-th bit is excited to be 1, if so, executing S=S+N, and simultaneously, iteratively adding 1 to the bit number parameter N to execute N=N+1, if so, keeping the current weight sum unchanged, and executing S=S, N=N+1;
And repeating the judgment logic of the last step 64 times to obtain the weight sum S, and transmitting the obtained weight sum S and n bit excitation data to the register module.
After the 64bit excitation data and the S value are input into the register module, the 64bit data are respectively stored into a 64bit register;
in each clock period, selecting 64, 63, 61 and 60-bit data in the register to carry out exclusive or, shifting the cascaded register data rightwards, and storing the exclusive or value in the register at the leftmost side after shifting;
repeatedly executing the processing step (n-1) of the register for S times, namely 63 x S times, deriving the data in the 64 registers to obtain excitation sequences, and inputting the 64bit excitation sequences to the selection ends of the first 32 multiplexers;
The above-mentioned processing steps of the registers are repeatedly executed S times, the data in the 64 registers are derived again to obtain a new excitation sequence, and the 64bit excitation sequence is input to the selection terminals of the last 32 multiplexers.
The invention is not limited to the specific embodiments described above. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification, as well as to any novel one, or any novel combination, of the steps of the method or process disclosed.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116192406A (en) * | 2023-02-27 | 2023-05-30 | 哈尔滨工业大学（深圳） | PUF structure |
| CN116522296A (en) * | 2023-04-06 | 2023-08-01 | 合肥工业大学 | Strong PUF-oriented machine learning-resistant CRP confusion method |
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| CN111027102B (en) * | 2019-11-13 | 2023-05-26 | 云南大学 | High-safety configurable RO-PUF circuit structure |
| CN111611629A (en) * | 2020-06-24 | 2020-09-01 | 中物院成都科学技术发展中心 | Physical fingerprint extraction system and method for chip |
| CN112713894B (en) * | 2021-01-13 | 2022-08-30 | 温州大学 | Strong and weak mixed PUF circuit |
| CN114357479A (en) * | 2021-12-23 | 2022-04-15 | 国网辽宁省电力有限公司信息通信分公司 | APUF improvement method, device and system based on random number and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116192406A (en) * | 2023-02-27 | 2023-05-30 | 哈尔滨工业大学（深圳） | PUF structure |
| CN116522296A (en) * | 2023-04-06 | 2023-08-01 | 合肥工业大学 | Strong PUF-oriented machine learning-resistant CRP confusion method |
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