CN117790422A - Dielectric layer for nanoplatelet protection and method of forming the same - Google Patents

Abstract

The present disclosure relates to a dielectric layer for nanosheet protection and a method for forming the same. A device includes a gate stack and a stack structure, the gate stack having a top, and the stack structure is located below the top of the gate stack. The stack structure includes a plurality of semiconductor nanostructures, and an upper nanostructure in the plurality of semiconductor nanostructures overlaps with a corresponding lower nanostructure. The stack structure also includes a plurality of gate structures, each gate structure including a lower portion of the gate stack. Each gate structure in the plurality of gate structures is located between two semiconductor nanostructures in the plurality of semiconductor nanostructures. A dielectric layer extends over a top surface and sidewalls of the stack structure. The dielectric layer includes a lower sublayer and an upper sublayer, the lower sublayer including a first dielectric material, and the upper sublayer is above the lower sublayer and is formed of a second dielectric material different from the first dielectric material. A gate spacer is located on the dielectric layer. A source/drain region is located next to the gate stack.

Description

Dielectric layer for nanosheet protection and method for forming the same

Technical field

The present disclosure relates to dielectric layers for nanosheet protection and methods of forming the same.

Background technique

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric, conductive, and semiconductor layers of materials over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components thereon. and components.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing minimum feature sizes, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other issues arise that need to be addressed.

Contents of the invention

According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a protruding semiconductor stack, the semiconductor stack comprising: a plurality of sacrificial layers; and a plurality of nanostructures, wherein the plurality of sacrificial layers and the plurality of nanostructures are arranged alternately; depositing a dielectric layer on the sidewalls and top surface of the protruding semiconductor stack, wherein the dielectric layer comprises: a lower sublayer; and an upper sublayer, above the lower sublayer, wherein the lower sublayer and the upper sublayer comprise different dielectric materials; forming a dummy gate electrode layer on the dielectric layer; patterning the dummy gate electrode layer to form a dummy gate electrode, wherein the dielectric layer serves as an etch stop layer; forming a gate spacer on an additional sidewall of the dummy gate electrode; removing the dummy gate electrode; etching the dielectric layer to reveal the protruding semiconductor stack; removing the plurality of sacrificial layers; and forming a replacement gate stack, wherein the replacement gate stack fills the space left by the removed dummy gate electrode and the removed plurality of sacrificial layers.

According to another embodiment of the present disclosure, a semiconductor device is provided, including: a gate stack including a top; and a stack structure located below the top of the gate stack, the stack structure including: a plurality of semiconductor nanostructures , an upper nanostructure of the plurality of semiconductor nanostructures overlaps a lower nanostructure of the plurality of semiconductor nanostructures; and a plurality of gate structures, each gate structure including a lower portion of the gate stack, wherein , each gate structure of the plurality of gate structures is located between two semiconductor nanostructures of the plurality of semiconductor nanostructures; a dielectric layer extends on the top surface and sidewalls of the stacked structure, Wherein, the dielectric layer includes: a lower sub-layer including a first dielectric material; and an upper sub-layer above the lower sub-layer, wherein the upper sub-layer includes a second dielectric different from the first dielectric material. material; a gate spacer on the dielectric layer; and a source/drain region next to the gate stack.

According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a first dielectric isolation region and a second dielectric isolation region, including at least some portions in the semiconductor substrate; a protruding structure protruding above the top surface of the dielectric isolation region, wherein the protruding structure is laterally located between the first dielectric isolation region and the second dielectric isolation region, and wherein the protruding structure comprises: a plurality of semiconductor layers; and a plurality of gate stack portions, wherein the plurality of semiconductor layers and the plurality of gate stack portions are alternately arranged; a plurality of internal spacers, comprising a plurality of pairs, each pair being located on opposite sides of one of the plurality of gate stack portions; and a dielectric layer, comprising: a top portion, above the protruding structure, wherein the top portion has a first thickness; and a sidewall portion, in contact with one of the plurality of internal spacers, wherein the sidewall portion has a second thickness different from the first thickness.

Description of the drawings

Aspects of the present disclosure can best be understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Figures 1 to 3, Figure 4A, Figure 4B, Figure 5 to Figure 7, Figure 8A, Figure 8B, Figure 8C, Figure 8D, Figure 8E, Figure 9A, Figure 9B, Figure 10A, Figure 10B, Figure 10C, Figure 11A , Figure 11B, Figure 11C, Figure 12A, Figure 12B, Figure 13A, Figure 13B, Figure 13C, Figure 13D, Figure 13E, Figure 14A, Figure 14B, Figure 15A, Figure 15B, Figure 15C and Figure 15D illustrate some Perspective, cross-sectional and top views of intermediate stages in forming a gate all around (GAA) transistor according to an embodiment.

Figure 16 illustrates a process flow for forming GAA transistors in accordance with some embodiments.

Detailed ways

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed on the second feature. Embodiments in which one feature and a second feature are formed so that the first feature and the second feature may not be in direct contact. Furthermore, this disclosure may repeat reference numbers and/or letters in various examples. This repetition is for simplicity and clarity and does not inherently indicate a relationship between the various embodiments and/or configurations discussed.

Additionally, spatially relative terms are used herein (e.g., “below,” “beneath,” “lower,” “above,” “higher,” etc.) to readily describe the relative position of one element or feature illustrated in the figures to another. A relationship between (one or more) elements or (one or more) features. These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted similarly.

Gate-All-Around (GAA) transistors with improved dummy gate dielectrics and methods of forming the same are provided. According to some embodiments, formation of the GAA transistor includes depositing a composite dummy gate dielectric that includes two or more layers formed of different dielectric materials, thereby reducing damage to underlying silicon nanostructures. The dummy gate dielectric may be a non-conformal layer having a top that is thicker than the sidewall portions. The embodiments discussed herein are intended to provide examples of enabling making or using the disclosed subject matter, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the intended scope of the various embodiments. The same reference numbers are used to refer to the same elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Figures 1 to 3, Figure 4A, Figure 4B, Figure 5 to Figure 7, Figure 8A, Figure 8B, Figure 8C, Figure 8D, Figure 8E, Figure 9A, Figure 9B, Figure 10A, Figure 10B, Figure 10C, Figure 11A , Figure 11B, Figure 11C, Figure 12A, Figure 12B, Figure 13A, Figure 13B, Figure 13C, Figure 13D, Figure 13E, Figure 14A, Figure 14B, Figure 15A, Figure 15B, Figure 15C and Figure 15D illustrate some Perspective, cross-sectional and top views of intermediate stages of forming a GAA transistor according to the embodiment. The corresponding process is also schematically reflected in the process flow shown in FIG. 16 .

Referring to FIG. 1 , a perspective view of wafer 10 including substrate 20 is shown. A multilayer structure including multilayer stack 22 is formed on substrate 20 . According to some embodiments, substrate 20 is (or includes) a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, or the like, although other substrates and/or structures may be used, such as semiconductor-on-insulator (SiGe) substrates. SOI), strained SOI, silicon germanium on insulator, etc. Substrate 20 may be doped as a p-type semiconductor, but in other embodiments it may be doped as an n-type semiconductor.

According to some embodiments, the multilayer stack 22 is formed by a series of epitaxial processes for depositing alternating materials. The corresponding process is shown as process 202 in the process flow 200 shown in Figure 16. According to some embodiments, the multilayer stack 22 includes a first layer 22A and a second layer 22B, the first layer 22A is formed of a first semiconductor material and the second layer 22B is formed of a second semiconductor material different from the first semiconductor material. Because of epitaxy, the first layer 22A and the second layer 22B have the same lattice direction as the substrate 20.

According to some embodiments, the first layer 22A of the first semiconductor material is formed from or includes SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (eg, SiGe) is by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, first layer 22A is formed at about Peace Treaty/> The first thickness in the range between. However, any suitable thickness may be used while remaining within the scope of the embodiments.

Once the first layer 22A has been deposited on the substrate 20, the second layer 22B is deposited on the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GasB, InAlAs, InGaAs, GasB, GaAsSB, and combinations thereof, and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A is silicon germanium, the second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable material combination can be used for the first layer 22A and the second layer 22B.

According to some embodiments, second layer 22B is epitaxially grown on first layer 22A using a deposition technique similar to that used to form first layer 22A. According to some embodiments, second layer 22B is formed to a similar thickness as first layer 22A. The second layer 22B may also be formed to a thickness different from the first layer 22A.

Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multi-layer stack 22 until the desired topmost layer of the multi-layer stack 22 has been formed. According to some embodiments, the first layers 22A have the same or similar thicknesses to each other, and the second layers 22B have the same or similar thicknesses to each other. The first layer 22A may also have the same or a different thickness than the second layer 22B. According to some embodiments, first layer 22A is removed in a subsequent process and is instead referred to as sacrificial layer 22A throughout this specification. According to an alternative embodiment, second layer 22B is sacrificed and removed in a subsequent process.

According to some embodiments, pad oxide layer 12 and hard mask 14 are formed over multilayer stack 22 . Pad oxide layer 12 may include silicon oxide, silicon carbide, etc., while hard mask layer 14 may include silicon nitride, and other materials may be used. Pad oxide layer 12 and hard mask layer 14 are patterned to form a plurality of elongated strips, which are also referred to as pad oxide and hard mask.

Referring to FIG. 2 , a portion of underlying substrate 20 and multilayer stack 22 are patterned in an etching process(es) such that trenches (filled with isolation regions 26 ) are formed. The trench extends into substrate 20 . The remainder of the multi-layer stack is referred to below as multi-layer stack 22'. The corresponding process is shown as process 204 in the process flow 200 shown in FIG. 16 . Below the multilayer stack 22', some portion of the substrate 20 is left behind and is referred to below as substrate strip 20'. Multilayer stack 22' includes semiconductor layer 22A and semiconductor layer 22B. Semiconductor layer 22A is alternatively referred to as a sacrificial layer, and semiconductor layer 22B is alternatively referred to as a nanostructure below. Parts of the multilayer stack 22' and the underlying substrate strip 20' are collectively referred to as semiconductor strips 27.

In the embodiments described above, the GAA transistor structures may be patterned by any suitable method. For example, these structures may be patterned using one or more photolithography processes, including dual or multi-patterning processes. Typically, a dual-patterning process or a multi-patterning process combines a photolithography process and a self-alignment process, allowing for the creation of patterns with, for example, smaller pitches than achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

Next, isolation regions 26 are formed, which may also be referred to as shallow trench isolation (STI) regions throughout this specification. The corresponding process is shown as process 206 in the process flow 200 shown in FIG. 16 . STI region 26 may include a lining oxide (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of substrate 20 . The lining oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), CVD, or the like. STI region 26 may also include a dielectric material over the liner oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPVCD, or the like. A planarization process (eg, a chemical mechanical polishing (CMP) process or a mechanical grinding process) may then be performed such that the top surface of the dielectric material is flush with, for example, the top surface of hard mask layer 14 and the remaining portion of the dielectric material is STI Area 26.

3 , the STI region 26 is recessed so that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin (structure) 28 (also referred to as a nanosheet). The corresponding process is shown as process 208 in the process flow 200 shown in FIG. 16 . The protruding fin 28 includes some of the top of the substrate strip 20 'and the multilayer stack 22 '. The recessing of the STI region 26 can be performed by a dry etching process, wherein, for example, NF ₃ and NH ₃ are used as etching gases. During the etching process, plasma can be generated. Argon gas can also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 26 is performed by a wet etching process. For example, the etching chemical can include HF. The pad oxide layer 12 and the hard mask 14 are removed.

Referring to FIGS. 4A and 4B , dielectric layer 32 is deposited on the sidewalls and top surfaces of protruding fins 28 , as well as the top surface of STI region 26 . The corresponding process is shown as process 210 in the process flow 200 shown in FIG. 16 . Figure 4A shows a perspective view and Figure 4B shows the vertical cross-section 4B-4B shown in Figure 4A. According to some embodiments, dielectric layer 32 is a single (homogeneous) layer, with the entire dielectric layer 32 being formed from the same material and having the same composition. Throughout this specification, when two layers are referred to as having the same composition, this means that the two layers have the same elements and that the percentages of the corresponding elements in the two layers are the same as each other. Conversely, when two layers are said to have different compositions, it means that at least one of the two layers has at least one element that is not in the other layer, or that both layers have the same element, but both layers The percentages of elements in are different from each other.

According to alternative embodiments, dielectric layer 32 is a composite layer including two or more sublayers. For example, FIGS. 4A and 4B show a composite layer 32 including a lower sublayer 32A and an upper sublayer 32B on the lower sublayer 32A. A dotted line (interface) is drawn between lower sublayer 32A and upper sublayer 32B to indicate that dielectric layer 32 may be a single layer (in these embodiments, no interface is formed therein), or may be a composite layer. When a composite layer, dielectric layer 32 may include two layers, three layers, or more layers, with adjacent layers being formed of different dielectric materials.

According to some embodiments in which dielectric layer 32 is a single layer, dielectric layer 32 may be formed from a material that has a lower etch rate than silicon oxide, wherein the etch rate is responsive to the etch rate used to remove and clean subsequently formed dummy gate electrode 34 ( 13A to 13E). According to some embodiments, cleaning is performed using HF, and dielectric layer 32 may include elements other than oxygen (eg, carbon and/or nitrogen). For example, dielectric layer 32 may be formed from or include SiC _x (x ranges between about 0.8 and about 1), SiO _x C _y (x and y range between about 0.8 and about 1) , SiO _x N _y , SiC _x N _y , SiN _x (x is in the range between about 0.8 and about 1.33), SiO _x C _y N _z (x and y are in the range between about 0.1 and about 0.3, and z in a range between about 0.4 and about 0.6), etc.

According to alternative embodiments in which dielectric layer 32 is a composite layer, lower sub-layer 32A may be formed from SiO _x (x ranges between about 0.8 and about 2.0, or between about 0.8 and 1.33). Lower sublayer 32A may also be formed from a non- _SiOx dielectric material, which may be a material described above that has a lower etch rate than _silicon oxide in subsequent removal and cleaning of dummy gate electrode 34. For example, non- _SiOx dielectric materials _may be formed from or include _SiCx , _SiOxCy , _{SiOxNy , SiCxNy , SiNx , SiOxCyNz} , and the _like .

According to _{yet another alternative embodiment in which dielectric layer 32 is a composite layer, each of lower sub-layer 32A and upper sub-layer 32B may be formed from or include a non-SiO x dielectric} material. Although the materials of the lower sub-layer 32A and the upper sub-layer 32B are different from each other, each of the lower sub-layer 32A and the upper sub-layer 32B may be formed by ( having a lower etching rate than silicon oxide in subsequent removal and cleaning of the dummy gate electrode 34 above) materials. For example, lower sub-layer 32A and upper sub-layer 32B may each be selected from the same candidate material group, which may include SiC _x , SiO _{x Cy} , SiO _x N _y , SiC _x N _y , SiN _x , SiO _x C _y N _z etc.

According to yet another alternative embodiment in which dielectric layer 32 is a composite layer, each of lower sub-layer 32A and upper sub-layer 32B may have a consistent composition. When dielectric layer 32 is a single layer, the entire dielectric layer 32 can be deposited to have a consistent composition. According to an alternative embodiment, dielectric layer 32 has a gradually changing composition, with different portions including the same elements (eg, silicon, oxygen, and nitrogen), while the percentages of the elements are gradually changed from bottom to top. For example, the bottom _of dielectric layer ₃₂ may include _SiO or any combination of three. The atomic percent y of AE gradually increases from the bottom of dielectric layer 32 to the top of dielectric layer 32 . This can be achieved, for example, by gradually changing the flow rate of the precursor when using CVD. As will be discussed in subsequent paragraphs, when formed from a different material than lower sub-layer 32A, upper sub-layer 32B may act as a firewall to prevent sheet damage.

According to some embodiments, dielectric layer 32 is formed using an atomic layer deposition (ALD) process that includes multiple ALD cycles. Each ALD cycle may include a first phase followed by a second phase. The first stage may include introducing (also known as pulsing or feeding) a first precursor into the ALD chamber, cleaning the first precursor, and conducting the plasma. During the pulse modulation and initial cleaning phase in the first stage, the plasma can be turned off. The second stage may include: introducing the second precursor into the ALD chamber, cleaning the second precursor, and turning on the plasma. During the pulse modulation and initial cleaning phase in the second stage, the plasma can be turned off. The plasma can also be turned on in the second stage, but not in the first stage. The purge gas may include N ₂ , Ar, Ne, Kr, He, etc. or combinations thereof. Plasma processing may be performed in a processing gas including N ₂ , Ar, Ne, Kr, He, O ₂ , NH ₃ , N ₂ O, etc., or combinations thereof.

According to some embodiments, the first precursor includes a silicon-containing precursor, which may include silane, disilane, aminosilane, di-sec-butylaminosilane (DSBAS), bis(tert-butylamino)silane (BTBAS), etc., or their combination. The second precursor may include another element(s), for example, C, N and/or O. For example, when N is to be included in the dielectric layer, the second precursor may include ammonia. The resulting dielectric layer 32 may include SiC, SiN, SiO, SiCN, SiOCN, SiON, etc. or combinations thereof.

According to alternative embodiments, other deposition methods such as CVD may be used to form dielectric layer 32 . The composition of dielectric layer 32 can be controlled by adjusting the flow rate of the corresponding precursor. According to some embodiments in which the composition of dielectric layer 32 is gradually changed, the flow rate and flow rate ratio of the precursor may be gradually changed as deposition of dielectric layer 32 proceeds.

According to some embodiments, as shown in FIGS. 5 and 6 shown subsequently, dummy gate electrode layer 34 is patterned in an anisotropic etch process, and this is performed using dielectric layer 32 as an etch stop layer. Patterning process. Because of process variations, the top of dielectric layer 32 on top of protruding fins 28 may be damaged and may also have more loss than the vertical portions of dielectric layer 32 on the sidewalls of protruding fins 28 . When the top of dielectric layer 32 is damaged or removed due to process variations, top nanostructures 22B may be exposed and suffer loss. This leads to process degradation and deviations. Accordingly, dielectric layer 32 may be formed with a top thickness that is greater than the sidewall thickness, thereby providing greater process margin for top nanostructure loss.

Figure 4B shows the vertical cross-section view 4B-4B in Figure 4A. Dielectric layer 32 includes a top portion 32T directly above protruding fin 28, and the top thickness of the top portion is designated T1 (including T1A, T1B, and T1C). Thickness T1 may be measured at the middle vertical line of the corresponding protruding fin 28 . According to some embodiments, top 32T has a consistent thickness. For example, Figure 4B shows that thickness T1A, thickness T1B, and thickness T1C can be the same, varying by less than about 10% or less.

Dummy gate dielectric layer 32 also includes sidewall portions 32S on the sidewalls of protruding fins 28 , and horizontal portions 32H that overlap and contact the top surface of STI region 26 . Thickness T3 of horizontal portion 32H may be equal to thickness T2, both thickness T2 and thickness T3 being less than thickness T1. Therefore, dielectric layer 32 is a non-conformal layer. According to some embodiments, each of thickness ratio T1/T2 and thickness ratio T1/T3 is greater than about 1.5, and may be greater than about 2.0 (eg, in a range between about 2 and about 5). When one or more of lower sub-layer 32A and upper sub-layer 32B are non-conformal, thickness ratio T1'/T2' and thickness ratio T1"/T2" may also be greater than about 1.5, and may be greater than about 2.0, for example, in In the range between about 2 and about 5. Thickness T1' and thickness T2' are the top thickness and sidewall thickness, respectively, of lower sub-layer 32A. Thickness T1 ″ and thickness T2 ″ are the top thickness and sidewall thickness, respectively, of upper sub-layer 32B.

According to some embodiments, the top thickness T1 may be about Peace Treaty/> within the range between. Sidewall thickness T2 and bottom thickness T3 can be found at/> Peace Treaty/> within the range between.

According to some embodiments in which dielectric layer 32 includes two or more dielectric layers, zero, one, or more sublayers in dielectric layer 32 may have non-conformal profiles in any combination of the above, while the other(s) Sublayers (if any) can be conformal. For example, when there are two sub-layers, lower sub-layer 32A may have a conformal profile and upper sub-layer 32B may have a non-conformal profile. This profile allows upper sublayer 32A to stop etching during subsequent patterning of the dummy gate electrode layer. According to alternative embodiments, lower sub-layer 32A may have a non-conformal profile, while upper sub-layer 32B may have a conformal profile. According to yet another alternative embodiment, both lower sub-layer 32A and upper sub-layer 32B have non-conformal profiles.

To achieve the non-conformal profile of dielectric layer 32, a CVD mode ALD process is employed, where the ALD process conditions are adjusted to achieve a thicker top thickness than the sidewall thickness. Adjustment of the process conditions may include reducing the precursor introduction time (feed time) so that the precursor has less time to diffuse to the bottom of the trench between protruding fins 28 and less time for the precursor to adsorb. Adjustment of process conditions may also include increasing the pressure of the precursor during precursor introduction. Adjustment of process conditions may also include reducing the plasma on-time (hereinafter referred to as plasma treatment time) so that fewer reactions occur.

According to some embodiments, in an ALD cycle for forming non-conformal dielectric layer 32, the precursor introduction time may be in a range between about 0.01 seconds and about 0.2 seconds. The pressure may be in a range between about 2 Torr and about 3.5 Torr. The plasma treatment time may be in a range between about 0.1 seconds and about 3 seconds.

It should be understood that the profile of the dielectric layer 32 can be the result of a combination of various factors. Therefore, experiments can be conducted to find the desired combination of process conditions to achieve the desired profile. The experiment can include forming a plurality of sample dielectric layers 32 on a plurality of sample wafers. In the formation, a plurality of sample dielectric layers are formed using a plurality of different combinations of process conditions (e.g., pressure, precursor introduction time, plasma treatment time, etc.). The profile of the sample dielectric layer is measured to determine the correlation between the process conditions and the profile of the dielectric layer. Therefore, the desired process conditions can be selected as the conditions that lead to the desired profile of the dielectric layer 32.

It should be understood that in related processes, the dummy dielectric layer may be formed simultaneously with the gate oxide of the IO transistor. According to embodiments of the present disclosure, because the material and structure of dielectric layer 32 are different from those of the gate oxide of the IO transistor, the formation of dielectric layer 32 and the formation of the gate oxide of the IO transistor are decoupled, and are formed in separate processes and have different structures. For example, the gate oxide of an IO transistor may be formed of silicon oxide and may be conformal, while the dielectric layer 32 of a GAA transistor may be formed of the materials described above and may be non-conformal.

Referring to FIG5 , a dummy gate electrode layer 34 is deposited. The corresponding process is shown as process 212 in the process flow 200 shown in FIG16 . A planarization process is then performed to level the top surface of the dummy gate electrode layer 34. For example, the dummy gate electrode layer 34 may be formed using polycrystalline silicon or amorphous silicon, and other materials such as amorphous carbon may also be used. One (or more) hard mask layers 36 are also formed on the dummy gate electrode layer 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbon nitride, or a multilayer thereof.

Referring to FIG. 6 , hard mask layer 36 and dummy gate electrode layer 34 are patterned in etching process 39 to form dummy gate stack 37 including hard mask 36 and dummy gate electrode 34 . The corresponding process is shown as process 214 in the process flow 200 shown in FIG. 16 . The resulting structure is shown in Figure 6. According to some embodiments, the patterning process is performed by an anisotropic etching process. The etching gas may include fluorine (F ₂ ), chlorine (Cl ₂ ), hydrogen chloride (HCl), hydrogen bromide (HBr), bromine (Br ₂ ), C ₂ F ₆ , CF ₄ , SO ₂ , HBr, Cl ₂ and Mixtures of _O2 or combinations thereof. The etching is performed using dielectric layer 32 as an etch stop layer. According to some embodiments, by selecting an appropriate combination of materials and etching chemicals for dielectric layer 32, the etch rate of dielectric layer 32 is lower than the etch rate of silicon oxide. As a result, dielectric layer 32 in embodiments of the present disclosure stops etching better than silicon oxide, which can also be the gate oxide for IO transistors (which can be formed in the same wafer/die as GAA transistors) things.

Because the etching process 39 is anisotropic, the top of the dielectric layer 32 experiences more losses from the sidewall portions. As the top of dielectric layer 32 becomes thicker, the possibility of completely removing the top of dielectric layer 32 by patterning process 39 decreases. Therefore, the underlying top nanostructure 22B is less likely to be etched, or less lost if etched. For example, during patterning process 39, _SiOx and _SiOxCyNZ may have _{an approximate} /Minute Agreement/> Etch rates in the range between /min. _SiCx and _{SiCxNy ,} on the other hand, can have significantly lower etch rates, which can be around/> /Minute Agreement/> /minute. _SiNx can also have a significantly lower etch rate, which can be achieved at approximately /Minute Agreement/> /minute.

According to some embodiments in which dielectric layer 32 is a composite layer, one but not both of upper sub-layer 32B and lower sub-layer 32A is non-conformal, and the etch rate of the non-conformal sub-layer (during patterning process 39) is also The etch rate of the conformal sublayer may be lower than that of the conformal sublayer to minimize the possibility of completely removing the top of dielectric layer 32 .

Next, FIG. 7 shows that a gate spacer 38 is formed on the sidewall of the dummy gate stack 37. The corresponding process is shown as process 216 in the process flow 200 shown in FIG. 16. According to some embodiments, the gate spacer layer 38 is formed of a dielectric material (e.g., silicon nitride (SiN), silicon dioxide ( _SiO2 ), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc.), and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The formation process of the gate spacer 38 may include: depositing one or more dielectric layers, and then performing (one or more) anisotropic etching processes on (one or more) dielectric layers. The remaining portion of (one or more) dielectric layers is the gate spacer 38.

Figures 8A, 8B and 8E illustrate the formation of recesses 42 from which epitaxial regions are formed. Figures 8A and 8B show cross-sectional views of the structure shown in Figure 8E. 8A shows the vertical cross-section A-A in FIG. 8E, which cuts through the portion of the protruding fin 28 that is not covered by the dummy gate stack 37 and the gate spacer. Figure 8A also shows fin spacers 38' located on the sidewalls of protruding fins 28. FIG. 8B shows the reference cross-section B-B in FIG. 8E , which reference cross-section is parallel to the longitudinal direction of the protruding wing 28 .

8A, 8B, and 8E illustrate that exposed portions of dielectric layer 32 are etched. The corresponding process is shown as process 218 in the process flow 200 shown in FIG. 16 . The portions of dummy gate stack 37 and gate spacers 38 directly beneath dielectric layer 32 and protruding fins 28 remain after the etching process. The corresponding process is shown as process 220 in the process flow 200 shown in FIG. 16 . The remainder of dielectric layer 32 is considered part of dummy gate stack 37 . According to some embodiments, the etching process includes dry etching performed using C ₂ F ₆ , CF ₄ , SO ₂ , a mixture of HBr, Cl ₂ and O ₂ , a mixture of HBr, Cl ₂ , O ₂ and CH ₂ F ₂ , etc. A process to etch the multi-layer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multi-layer semiconductor stack 22', or may be lower than the bottom of the multi-layer semiconductor stack 22'. The etching may be anisotropic such that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight.

Referring to Figure 8B, sacrificial semiconductor layer 22A is laterally recessed to form lateral recesses 41 that are recessed from the edges of corresponding overlying and underlying nanostructures 22B. The corresponding process is shown as process 222 in the process flow 200 shown in FIG. 16 . Lateral recessing of sacrificial semiconductor layer 22A may be achieved by a wet etching process using a material for sacrificial semiconductor layer 22A (eg, silicon germanium (SiGe)) in contrast to the material of nanostructure 22B and substrate 20 ( For example, silicon (Si) is a more selective etchant. For example, in embodiments in which sacrificial semiconductor layer 22A is formed of silicon germanium and nanostructures 22B are formed of silicon, the wet etching process may be performed using an etchant such as hydrochloric acid (HCl). The wet etching process may be performed using a dipping process, a spraying process, etc., and may use any suitable process temperature (e.g., between about 400°C and about 600°C) and suitable process time (e.g., between about 100 seconds and about 1000 seconds between) execution. According to alternative embodiments, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of dry and wet etching processes.

Figures 8C and 8D show top views of the structure shown in Figure 8B, where the top views are taken from a horizontal plane through the sacrificial semiconductor layer 22A and the nanostructure 22B, respectively. Referring to FIGS. 8C and 8D , the edges of nanostructures 22B may be aligned with the inner edges of gate spacers 38 . Figure 8C shows that the edges of sacrificial semiconductor layer 22A are laterally recessed. As a result, some interior portions of lower sublayer 32A of dielectric layer 32 may be exposed.

During the lateral recessing of the sacrificial semiconductor layer 22A and the subsequent cleaning process, damage may be caused to the lower sublayer 32A. This may result in through-channels (air gaps) 43 being formed in lower sub-layer 32A. According to some embodiments, upper sub-layer 32B is resistant to chemicals used in the lateral recessing and subsequent cleaning processes of sacrificial semiconductor layer 22A, and thus through-channel 43 will be blocked by upper sub-layer 32B. In other words, upper sublayer 32B has a lower etch rate than lower sublayer 32A.

Figures 9A and 9B illustrate the formation of internal spacers 44. The corresponding process is shown as process 224 in the process flow 200 shown in FIG. 16 . The formation process includes depositing a spacer layer extending into recess 41 and performing an etching process to remove portions of the inner spacer layer outside recess 41 , leaving inner spacer layer 44 in recess 41 . The inner spacer 44 may be formed of or include SiOCN, SiON, SiOC, SiCN, etc. According to some embodiments, the etching of the spacer layer may be performed by a wet etching process, wherein the etching chemicals may include H ₂ SO ₄ , dilute HF, ammonia solution (NH ₄ OH, aqueous ammonia solution), etc., or combinations thereof.

10A, 10B, and 10C show cross-sectional and perspective views of source/drain regions 48 formed in recess 42 by epitaxy. The corresponding process is shown as process 226 in the process flow 200 shown in FIG. 16 . Depending on the context, individually or collectively, the source/drain region(s) may refer to a source or a drain. According to some embodiments, source/drain regions 48 may exert pressure on nanostructure 22B (which acts as a channel for the corresponding GAA transistor), thereby improving performance.

According to some embodiments, the corresponding transistor is n-type, so the epitaxial source/drain region 48 is formed to be n-type by doping with n-type dopants. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown to form the epitaxial source/drain region 48. According to alternative embodiments, the corresponding transistor is p-type, so the epitaxial source/drain region 48 is formed to be p-type by doping with p-type dopants. For example, silicon boron (SiB), silicon germanium boron (SiGeB), etc. can be grown to form the epitaxial source/drain region 48. After filling the recess 42 with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to expand horizontally, and a small facet can be formed. Further growth of the epitaxial region 48 can also cause adjacent epitaxial regions 48 to merge with each other, thereby forming a gap 49 (Figure 10C).

After the epitaxial process, the epitaxial region 48 may be further implanted with p-type impurities or n-type impurities to form source and drain regions, which are also indicated using reference numeral 48. According to an alternative embodiment of the present disclosure, when the epitaxial region 48 is in-situ doped with n-type impurities or p-type impurities during epitaxy and the epitaxial region 48 is also a source/drain region, the implantation process is skipped.

11A, 11B, and 11C show cross-sectional and perspective views of the structure after formation of contact etch stop layer (CESL) 50 and interlayer dielectric (ILD) 52. A corresponding process is shown as process 228 in the process flow 200 shown in FIG. 16 . Figure 11A shows cross-section 11A-11A in Figure 11B. CESL 50 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 52 may include dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 may be formed from an oxygen-containing dielectric material, which may be a silicon oxide based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

Figures 12A and 12B through Figures 15A and 15B illustrate processes for forming replacement gate stacks and contact plugs. In FIGS. 12A and 12B , a planarization process (eg, a CMP process or a mechanical grinding process) may be performed to make the top surface of the ILD 52 flush. According to some embodiments, the planarization process may remove hard mask 36 to reveal dummy gate electrode 34, as shown in Figure 12A. The corresponding process is shown as process 230 in the process flow 200 shown in FIG. 16 . According to alternative embodiments, the planarization process may expose hard mask 36 and be stopped on hard mask 36 . According to some embodiments, after the planarization process, dummy gate electrode 34 (or hard mask 36), gate spacer 38, and the top surface of ILD 52 are level within process variations.

Next, in the process illustrated in FIGS. 13A, 13B, and 13C, dummy gate electrode 34 (and hard mask 36, if remaining) is removed in one or more etching processes, thereby forming recess 58, As shown in Figure 13A and Figure 13B. The corresponding process is shown as process 232 in the process flow 200 shown in FIG. 16 . Portions of gate dielectric 32 in recess 58 are exposed.

According to some embodiments, the removal of dummy gate electrode 34 may be performed by a dry and/or wet etching process. For example, when dry etching is performed, the etching gas may include F2 _{, Cl2} , HCl, HBr, _{Br2 , C2F6} , _CF4 , SO2 _, etc. or a combination thereof. After removing the dummy gate electrode 34, a cleaning process may be performed, which may be performed using a dry etching process such as HF.

Figures 13D and 13E show top views of the structures shown in Figures 13A, 13B and 13C, taken from the same horizontal plane as shown in Figures 8C and 8D respectively. It can be observed from Figure 13E that if through-channel 43 penetrates the entire dielectric layer 32, the chemicals used to etch dummy gate electrode 34 and the subsequent cleaning process can pass through opening 58 and through-channel 43 to reach nanostructure 22B , the nanostructure 22B may be formed of or include silicon. Therefore, nanostructure 22B may be damaged, thus forming voids 43E. According to embodiments of the present disclosure, upper sub-layer 32B advantageously blocks through-channel 43 from extending therein, and thus through-channel 43 will not be able to penetrate the entire dielectric layer 32 . Chemicals in recess 58 will not be able to reach and damage nanostructure 22B.

Referring to Figures 14A and 14B, the exposed portions of gate dielectric 32 are etched. The corresponding process is shown as process 234 in the process flow 200 shown in FIG. 16 . On the other hand, the portion of gate dielectric 32 directly beneath gate spacer 38 is protected from removal.

Sacrificial layer 22A is then removed leaving recesses 58 extending between nanostructures 22B. The corresponding process is shown as process 236 in the process flow 200 shown in FIG. 16 . Sacrificial layer 22A may be removed by performing an isotropic etching process (eg, a wet etching process) using an etchant that is selective for the material of sacrificial layer 22A such that nanostructures 22B, 22B, Substrate 20, STI region 26, and remaining gate dielectric 32 are relatively unetched. According to some embodiments, wherein the sacrificial layer 22A includes, for example, SiGe, the nanostructures 22B include, for example, silicon or carbon-doped silicon. Chemicals such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide ( _NH4OH ), etc. may be used to remove sacrificial layer 22A.

Referring to FIGS. 15A, 15B, and 15C, gate stack 70 is formed. The corresponding process is shown as process 238 in the process flow 200 shown in FIG. 16 . Gate dielectric 62 is formed first. According to some embodiments, each of the gate dielectrics 62 includes an interface layer 64 and a high-k dielectric layer 66 on the interface layer 64 . Interface layer 64 may be formed of or include silicon oxide, which may be deposited by a conformal deposition process such as ALD or CVD. According to some embodiments, high-k dielectric layer 66 includes one or more dielectric layers. For example, high-k dielectric layer 66 may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

Gate electrode 68 is formed over gate dielectric 62 . During the formation process, a conductive layer is first formed on high-k dielectric layer 66 to fill the remainder of recess 58 . Gate electrode 68 may include metal-containing materials such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and/or multiple layers thereof. Gate electrode 68 may also include filler metals such as cobalt, tungsten, and the like. Gate dielectric 62 and gate electrode 68 also fill the space between adjacent nanostructures 22B in nanostructures 22B, and fill the bottom nanostructures 22B in nanostructures 22B and the underlying liner in substrate strip 20'. Bottom strips with 20' of space between them. After filling recess 58 , a planarization process (eg, a CMP process or a mechanical grinding process) may be performed to remove excess portions of gate dielectric 62 and gate electrode 68 over the top surface of ILD 52 . Gate electrode 68 and gate dielectric 62 are collectively referred to as gate stack 70 of the resulting nanoFET.

Next, the gate stack 70 is recessed such that a recess is formed directly above the gate stack 70 and between opposite portions of the gate spacer 38 . A gate mask 74 including one or more layers of dielectric material (e.g., silicon nitride or silicon oxynitride, etc.) is filled in each of the recesses, and then a planarization process is performed to remove parts of the first ILD 52 The excess portion of dielectric material that extends above.

15A and 15B also show that ILD 76 is deposited over ILD 52 and over gate mask 74. An etch stop layer (not shown) may (or may not) be deposited before the formation of ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, etc. ILD 76 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

ILD 76, ILD 52, CESL 50, and gate mask 74 are etched to form recesses (occupied by contact plugs 80A and 80B) through which source/drain regions 48 and/or the gate are epitaxially Stack 70 is exposed. The recessed portion may be formed by an anisotropic etching process (eg, RIE or NBE, etc.). According to some embodiments, the recess may be formed by etching ILD 76 and ILD 52 using a first etch process, etching gate mask 74 using a second etch process, and possibly etching CESL 50 using a third etch process. Although FIG. 15B illustrates contact plugs 80A and 80B in the same cross-section, in various embodiments, contact plugs 80A and 80B may be formed in different cross-sections such that Reduce the risk of short circuiting each other.

After the recesses are formed, suicide regions 78 ( FIGS. 15B and 15C ) are formed over epitaxial source/drain regions 48 . According to some embodiments, silicide region 78 is formed by first depositing a metal layer (not shown) that is capable of interacting with the underlying semiconductor material of epitaxial source/drain regions 48 (eg, silicon, silicon germanium, germanium) react to form a suicide region and/or a germanide region, and then a thermal annealing process is performed to form the suicide region 78 . Metals may include nickel, cobalt, titanium, tantalum, platinum, tungsten, etc. Unreacted portions of the deposited metal are then removed, for example by an etching process.

Gate contact plug 80A and source/drain contact plug 80B are formed. The corresponding process is shown as process 240 in the process flow 200 shown in Figure 16. Source/drain contact plug 80B is formed on silicide region 78. Gate contact 80A is located on gate electrode 68 and contacts gate electrode 68. Contact plug 80A and contact plug 80B can each include one or more layers, for example, barrier layer and filling material. Barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, etc. Conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process (e.g., CMP process) can be performed to remove excess material from the surface of ILD 76. Therefore, GAA transistor 82 is formed.

The gate dielectric 32 may be present in the final GAA transistor 82 and may have a single-layer structure or a multi-layer structure. FIG. 15D shows a cross section 15D-15D (FIG. 15B). In FIG. 15D, the area marked 44/70 indicates that an internal isolation member 44 and/or a gate electrode 70 may appear in the cross section shown. A top view of the structure can also be found in FIGS. 13D and 13E, in which the space 58 is filled with a replacement gate stack 70 and the sacrificial semiconductor layer 22A is also replaced with the replacement gate stack 70. In the GAA transistor 82, the dielectric layer 32 can be distinguished, for example, by transmission electron microscopy (TEM), energy dispersive X-ray (EDX), electron energy loss spectroscopy (EELS), and the like.

Embodiments of the present disclosure have several advantageous features. By forming multiple layers of dummy gate dielectric, damage to the nanostructure is avoided. Furthermore, by forming a non-conformal dummy gate dielectric layer, the loss of the top nanostructure is avoided or reduced. Experiments have revealed that by forming a non-conformal dummy gate dielectric layer, the loss of the top nanostructure can be reduced to 30% of the loss when using a conformal dummy gate dielectric layer.

According to some embodiments, a method includes: forming a protruding semiconductor stack, the semiconductor stack including: a plurality of sacrificial layers; and a plurality of nanostructures, wherein the plurality of sacrificial layers and the plurality of nanostructures are arranged alternately; depositing a dielectric layer on the sidewalls and top surface of the protruding semiconductor stack, wherein the dielectric layer includes: a lower sublayer; and an upper sublayer above the lower sublayer, wherein the lower sublayer and the upper sublayer include different dielectric materials; forming a dummy gate electrode layer on the dielectric layer; patterning the dummy gate electrode layer to form a dummy gate electrode, wherein the dielectric layer serves as an etch stop layer; forming a gate spacer on an additional sidewall of the dummy gate electrode; removing the dummy gate electrode; etching the dielectric layer to reveal the protruding semiconductor stack; removing the plurality of sacrificial layers; and forming a replacement gate stack, wherein the replacement gate stack fills the space left by the removed dummy gate electrode and the removed plurality of sacrificial layers.

In an embodiment, the first of the lower sub-layer and the upper sub-layer is formed as a non-conformal layer. In an embodiment, the non-conformal first of the lower sub-layer and the upper sub-layer is formed using atomic layer deposition. In an embodiment, the second of the lower sub-layer and the upper sub-layer is also formed using atomic layer deposition, and the second of the lower sub-layer and the upper sub-layer is a conformal layer. In an embodiment, both the lower sub-layer and the upper sub-layer have a top thickness equal to the sidewall thickness.

In an embodiment, the method further includes: etching a portion of the protruding semiconductor stack after forming the gate spacer, wherein a portion of the protruding semiconductor stack below the gate spacer and the dummy gate electrode remains after etching; and causing The plurality of sacrificial layers are laterally recessed, wherein via holes are formed to penetrate the lower sub-layer, and wherein the via holes are blocked by the upper sub-layer. In an embodiment, the upper sub-layer is exposed at a time after the dummy gate electrode is removed, and wherein the upper sub-layer blocks chemicals used in removing the dummy gate electrode from extending into the via.

In an embodiment, after etching the dielectric layer to reveal the protruding semiconductor stack, a portion of the dielectric layer directly beneath the gate spacer remains. In an embodiment, the lower sub-layer includes silicon oxide and the upper sub-layer includes silicon and carbon. In an embodiment, the lower sub-layer includes silicon oxide and the upper sub-layer includes silicon and nitrogen.

According to some embodiments, a device includes: a gate stack including a top; a stack structure located below the top of the gate stack, the stack structure including: a plurality of semiconductor nanostructures, an upper nanostructure of the plurality of semiconductor nanostructures and The lower nanostructures of the plurality of semiconductor nanostructures overlap; and a plurality of gate structures, each gate structure including a lower portion of the gate stack, wherein each of the plurality of gate structures is located on the plurality of semiconductor nanostructures. between two semiconductor nanostructures in the structure; a dielectric layer extending over the top surface and sidewalls of the stacked structure, wherein the dielectric layer includes: a lower sub-layer including a first dielectric material; and an upper sub-layer between the lower sub-layers on, wherein the upper sub-layer includes a second dielectric material different from the first dielectric material; a gate spacer on the dielectric layer; and a source/drain region next to the gate stack.

In an embodiment, a first layer of the lower sub-layer and the upper sub-layer is a non-conformal layer, a top of the first layer above a top surface of the stacked structure has a first thickness, and a top of the first layer is on a side of the stacked structure. The lower portion of the wall has a second thickness that is different from the first thickness. In embodiments, the ratio of the first thickness to the second thickness ranges between about 2 and about 5.

In an embodiment, the second layer in the lower sub-layer and the upper sub-layer is a conformal layer. In an embodiment, the lower sub-layer has an air gap therein, and wherein the upper sub-layer and one of the plurality of semiconductor nanostructures are located on opposite sides of the air gap. In an embodiment, the lower sub-layer includes silicon oxide and the upper sub-layer includes silicon carbide. In an embodiment, the stacked structure further includes dielectric internal spacers, each dielectric internal spacer located between two semiconductor nanostructures of the plurality of semiconductor nanostructures, wherein the lower sub-layer is in contact with the dielectric internal spacers.

According to some embodiments, a device includes: a semiconductor substrate; first and second dielectric isolation regions, including at least some portions of the semiconductor substrate; and a protruding structure protruding above a top surface of the dielectric isolation region, wherein , the protruding structure is laterally located between the first dielectric isolation region and the second dielectric isolation region, and wherein the protruding structure includes: a plurality of semiconductor layers; and a plurality of gate stack portions, wherein the plurality of semiconductor layers and the plurality of gate stacks the gate stack portions are alternately positioned; a plurality of internal spacers, including a plurality of pairs, each pair being located on an opposite side of one of the plurality of gate stack portions; and a dielectric layer including: a top, on the protruding structure thereon, wherein the top portion has a first thickness; and a sidewall portion in contact with one of the plurality of inner spacers, wherein the sidewall portion has a second thickness different from the first thickness. In an embodiment, the dielectric layer includes multiple sub-layers formed of different materials. In embodiments, the first thickness is greater than the second thickness, and the ratio of the first thickness to the second thickness ranges between about 2 and about 5.

The above summarizes the features of several embodiments to enable those skilled in the art to better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

Example 1 is a method of forming a semiconductor device, including: forming a protruding semiconductor stack, the semiconductor stack including: a plurality of sacrificial layers; and a plurality of nanostructures, wherein the plurality of sacrificial layers and the plurality of nanostructures Alternately arranged; depositing dielectric layers on sidewalls and top surfaces of the protruding semiconductor stack, wherein the dielectric layer includes: a lower sub-layer; and an upper sub-layer over the lower sub-layer, wherein the lower sub-layer and the upper sub-layer including different dielectric materials; forming a dummy gate electrode layer on the dielectric layer; patterning the dummy gate electrode layer to form a dummy gate electrode, wherein the dielectric layer is forming an etch stop layer; forming gate spacers on additional sidewalls of the dummy gate electrode; removing the dummy gate electrode; etching the dielectric layer to reveal the protruding semiconductor stack; removing the plurality of sacrificial layer; and forming a replacement gate stack that fills the space left by the removed dummy gate electrode and the removed plurality of sacrificial layers.

Example 2 is the method of Example 1, wherein the first of the lower sub-layer and the upper sub-layer is formed as a non-conformal layer.

Example 3 is the method of Example 2, wherein the non-conformal first of the lower sub-layer and the upper sub-layer is formed using atomic layer deposition.

Example 4 is the method of Example 3, wherein a second one of the lower sub-layer and the upper sub-layer is also formed using atomic layer deposition, and all of the lower sub-layer and the upper sub-layer The second one is the conformal layer.

Example 5 is the method of Example 1, wherein both the lower sublayer and the upper sublayer have a top thickness equal to a sidewall thickness.

Example 6 is the method of Example 1, further comprising: after forming the gate spacer, etching a portion of the protruding semiconductor stack, wherein after the etching, retaining a portion of the protruding semiconductor stack located on the gate electrode spacers and a portion below the dummy gate electrode; and laterally recessing the plurality of sacrificial layers, wherein via holes are formed to penetrate the lower sublayer, and wherein the via holes are formed by the upper Sublayer blocking.

Example 7 is the method of Example 6, wherein the upper sub-layer is exposed at a time after the dummy gate electrode is removed, and wherein the upper sub-layer blocks removal of the dummy gate electrode. The chemicals used in extend into the vias.

Example 8 is the method of Example 1, wherein after etching the dielectric layer to reveal the protruding semiconductor stack, a portion of the dielectric layer directly beneath the gate spacer remains.

Example 9 is the method of Example 1, wherein the lower sublayer includes silicon oxide and the upper sublayer includes silicon and carbon.

Example 10 is the method of Example 1, wherein the lower sublayer includes silicon oxide and the upper sublayer includes silicon and nitrogen.

Example 11 is a semiconductor device, comprising: a gate stack including a top; a stack structure located below the top of the gate stack, the stack structure comprising: a plurality of semiconductor nanostructures, an upper nanostructure in the plurality of semiconductor nanostructures overlapping with a lower nanostructure in the plurality of semiconductor nanostructures; and a plurality of gate structures, each gate structure comprising a lower portion of the gate stack, wherein each gate structure in the plurality of gate structures is located between two semiconductor nanostructures in the plurality of semiconductor nanostructures; a dielectric layer extending on a top surface and sidewalls of the stack structure, wherein the dielectric layer comprises: a lower sublayer comprising a first dielectric material; and an upper sublayer above the lower sublayer, wherein the upper sublayer comprises a second dielectric material different from the first dielectric material; a gate spacer on the dielectric layer; and a source/drain region located next to the gate stack.

Example 12 is the device described in Example 11, wherein a first layer among the lower sublayer and the upper sublayer is a non-conformal layer, the first layer has a first thickness at a top portion above the top surface of the stacked structure, and the first layer has a second thickness at a lower portion on a sidewall of the stacked structure that is different from the first thickness.

Example 13 is the device of Example 12, wherein the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness ranges between about 2 and about 5.

Example 14 is the device of Example 12, wherein the second layer of the lower sub-layer and the upper sub-layer is a conformal layer.

Example 15 is the device of Example 11, wherein the lower sublayer has an air gap therein, and wherein the upper sublayer and one of the plurality of semiconductor nanostructures are located opposite the air gap. side.

Example 16 is the device of Example 11, wherein the lower sublayer includes silicon oxide and the upper sublayer includes silicon carbide.

Example 17 is the device of Example 11, wherein the stacked structure further includes a dielectric internal spacer, each of the dielectric internal spacers being located between two of the plurality of semiconductor nanostructures, wherein , the lower sublayer is in contact with the dielectric inner spacer.

Example 18 is a semiconductor device including: a semiconductor substrate; first and second dielectric isolation regions, including at least some portions of the semiconductor substrate; and a protruding structure protruding above the dielectric isolation region. The top surface of the invention, wherein the protruding structure is laterally located between the first dielectric isolation region and the second dielectric isolation region, and wherein the protruding structure includes: a plurality of semiconductor layers; and a plurality of gate electrodes a stack portion, wherein the plurality of semiconductor layers and the plurality of gate stack portions are alternately disposed; a plurality of internal spacers including a plurality of pairs, each pair being located on one gate of the plurality of gate stack portions; on an opposite side of the pole stack portion; and a dielectric layer including: a top portion over the protruding structure, wherein the top portion has a first thickness; and a sidewall portion with one of the plurality of internal spacers Internal spacer contacts, wherein the sidewall portions have a second thickness that is different than the first thickness.

Example 19 is the device of Example 18, wherein the dielectric layer includes a plurality of sub-layers formed of different materials.

Example 20 is the device of Example 18, wherein the first thickness is greater than the second thickness, wherein a ratio of the first thickness to the second thickness is in a range between about 2 and about 5.

Claims (10)

1. A method of forming a semiconductor device, comprising:

forming a protruding semiconductor stack, the semiconductor stack comprising:

a plurality of sacrificial layers; and

a plurality of nanostructures, wherein the plurality of sacrificial layers and the plurality of nanostructures are alternately arranged;

depositing a dielectric layer on sidewalls and a top surface of the protruding semiconductor stack, wherein the dielectric layer comprises:

a lower sub-layer; and

an upper sub-layer over the lower sub-layer, wherein the lower sub-layer and the upper sub-layer comprise different dielectric materials;

forming a dummy gate electrode layer on the dielectric layer;

patterning the dummy gate electrode layer to form a dummy gate electrode, wherein the dielectric layer serves as an etch stop layer;

forming a gate spacer on an additional sidewall of the dummy gate electrode;

removing the dummy gate electrode;

etching the dielectric layer to reveal the protruding semiconductor stack;

removing the plurality of sacrificial layers; and

A replacement gate stack is formed that fills the space left by the removed dummy gate electrode and the removed plurality of sacrificial layers.

2. The method of claim 1, wherein a first of the lower sub-layer and the upper sub-layer is formed as a non-conformal layer.

3. The method of claim 2, wherein the non-conformal first one of the lower sub-layer and the upper sub-layer is formed using atomic layer deposition.

4. The method of claim 3, wherein a second of the lower sub-layer and the upper sub-layer is also formed using atomic layer deposition, and the second of the lower sub-layer and the upper sub-layer is a conformal layer.

5. The method of claim 1, wherein both the lower sub-layer and the upper sub-layer have a top thickness equal to a sidewall thickness.

6. The method of claim 1, further comprising:

etching a portion of the protruding semiconductor stack after forming the gate spacer, wherein after the etching, a portion of the protruding semiconductor stack under the gate spacer and the dummy gate electrode remains; and

The plurality of sacrificial layers are laterally recessed, wherein a via is formed to penetrate the lower sub-layer, and wherein the via is blocked by the upper sub-layer.

7. The method of claim 6, wherein the upper sub-layer is exposed at a time after the dummy gate electrode is removed, and wherein the upper sub-layer blocks chemicals used in removing the dummy gate electrode from extending into the via.

8. The method of claim 1, wherein a portion of the dielectric layer directly under the gate spacer remains after etching the dielectric layer to reveal the protruding semiconductor stack.

9. A semiconductor device, comprising:

a gate stack including a top;

a stack structure located below a top of the gate stack, the stack structure comprising:

a plurality of semiconductor nanostructures, an upper nanostructure of the plurality of semiconductor nanostructures overlapping a lower nanostructure of the plurality of semiconductor nanostructures; and

a plurality of gate structures, each gate structure comprising a lower portion of the gate stack, wherein each gate structure of the plurality of gate structures is located between two semiconductor nanostructures of the plurality of semiconductor nanostructures;

A dielectric layer extending over the top surface and sidewalls of the stacked structure, wherein the dielectric layer comprises:

a lower sub-layer comprising a first dielectric material; and

an upper sub-layer over the lower sub-layer, wherein the upper sub-layer comprises a second dielectric material different from the first dielectric material;

a gate spacer on the dielectric layer; and

source/drain regions located beside the gate stack.

10. A semiconductor device, comprising:

a semiconductor substrate;

a first dielectric isolation region and a second dielectric isolation region, including at least some portions in the semiconductor substrate;

a protruding structure protruding above a top surface of the dielectric isolation region, wherein the protruding structure is located laterally between the first dielectric isolation region and the second dielectric isolation region, and wherein the protruding structure comprises:

a plurality of semiconductor layers; and

a plurality of gate stack portions, wherein the plurality of semiconductor layers and the plurality of gate stack portions are alternately placed;

a plurality of internal spacers comprising a plurality of pairs, each pair being located on opposite sides of one of the plurality of gate stack portions; and

A dielectric layer, comprising:

a top over the protruding structure, wherein the top has a first thickness; and

a sidewall portion in contact with one of the plurality of inner spacers, wherein the sidewall portion has a second thickness different from the first thickness.