CN117743253A - Interface for remote memory - Google Patents

Abstract

The present invention discloses a system having an interface for remote storage. In some embodiments, the system includes: an interface circuit having: a first interface configured to connect to the processing circuit; and a second interface configured to Connected to the memory, the first interface includes a cache coherence interface, and the second interface is different from the first interface.

Description

Interface for remote storage

Cross-references to related applications

This application claims the priority and benefit of U.S. Provisional Application No. 63/408,725 entitled "REMOTE ACCESS SOLUTION FOR CXLMEMORY CLUSTERING ACROSS SERVERS" filed on September 21, 2022, the entire contents of which are incorporated herein by reference.

Technical field

One or more aspects of embodiments in accordance with the present disclosure relate to computing systems, and more particularly to interfaces for remote memory.

Background technique

In a computing system, a host central processing unit (CPU) may be connected to host memory through, for example, an address bus and a data bus, or through the use of a high-speed interconnect such as CXL. Some systems for forming connections to memory may limit the length of conductors (eg, cables) that can be used to form these connections.

Aspects of the present disclosure are directed to this general technical environment.

Contents of the invention

According to an embodiment of the present disclosure, a system is provided, including: an interface circuit having: a first interface configured to be connected to a processing circuit; and a second interface, the first interface being connected to a processing circuit. Two interfaces are configured to connect to the memory, the first interface includes a cache coherence interface, and the second interface is different from the first interface.

In some embodiments, the system further includes a memory server connected to the second interface.

In some embodiments, the second interface includes a remote direct memory access interface.

In some embodiments, the second interface includes a computer cluster interconnect interface.

In some embodiments, the computer cluster interconnect interface includes an Ethernet interface.

In some embodiments, the storage server is connected to the second interface by a cable having a length greater than 6 feet.

In some embodiments, the cache coherence interface includes a Compute Express Link (CXL) interface.

In some embodiments, the first interface is configured to: send data to the processing circuit in response to a load instruction executed by the processing circuit; and to send data from the processing circuit in response to a store instruction executed by the processing circuit. The processing circuit receives the data.

In some embodiments, the system further includes a Compute Express Link (CXL) root complex connected between the processing circuitry and the first interface.

According to an embodiment of the present disclosure, a system is provided, including: an interface circuit having: a first interface configured to be connected to a processing circuit; and a second interface, the first interface being connected to a processing circuit. Two interfaces are configured to connect to the memory, the first interface includes a Compute Express Link (CXL) interface, and the second interface is different from the first interface.

In some embodiments, the system further includes a memory server connected to the second interface.

In some embodiments, the second interface includes a remote direct memory access interface.

In some embodiments, the second interface includes a computer cluster interconnect interface.

In some embodiments, the computer cluster interconnect interface includes an Ethernet interface.

In some embodiments, the storage server is connected to the second interface by a cable having a length greater than 6 feet.

In some embodiments, the CXL interface includes a cache coherence interface.

In some embodiments, the first interface is configured to: send data to the processing circuit in response to a load instruction executed by the processing circuit; and to send data from the processing circuit in response to a store instruction executed by the processing circuit. The processing circuit receives the data.

In some embodiments, the system further includes: a CXL root complex connected between the processing circuit and the first interface.

According to an embodiment of the present disclosure, a method is provided, comprising: executing, by a central processing unit, a store instruction for storing a first value in a first memory location at a first address; in response to said executing said store instructions transmitting, by the interface circuit, a store command to the memory including the first memory location, the store command being a command for storing the first value in the first memory location, wherein the interface circuit having: a first interface connected to the central processing unit; and a second interface connected to the memory, the first interface comprising a Compute Express Link (CXL) interface, and The second interface is different from the first interface.

In some embodiments, the method further includes: executing, by the central processing unit, a load instruction for loading a value in a second memory location at a second address into a register of the central processing unit; in response to The execution of the load instruction causes the interface circuit to send a read command to the memory, where the read command is a command for reading a value in the second memory location.

Description of drawings

These and other features and advantages of the present disclosure will be recognized and understood by reference to the specification, claims, and drawings, in which:

1A is a block diagram of a single host computing system in accordance with an embodiment of the present disclosure;

1B is a flowchart of a startup process according to an embodiment of the present disclosure;

1C is a block diagram of a single host computing system including a graphics processing unit, in accordance with an embodiment of the present disclosure;

1D is a block diagram of a single host computing system including multiple different memory pool servers, in accordance with an embodiment of the present disclosure;

2 is a block diagram of a multi-host computing system according to an embodiment of the present disclosure;

3 is an operational block diagram of a single host computing system in accordance with an embodiment of the present disclosure;

4 is a block diagram of a multi-host computing system with switches in accordance with an embodiment of the present disclosure; and

Figure 5 is a flowchart of a method according to an embodiment of the present disclosure.

Detailed ways

The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of interfaces for remote memory provided in accordance with the present disclosure and is not intended to represent the only forms in which the disclosure may be constructed or utilized. The description sets forth the features of the disclosure in connection with the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures may be implemented by different embodiments, which are also intended to be within the scope of the present disclosure. As shown elsewhere herein, similar element numbers are intended to indicate similar elements or features.

In various computing applications, the memory requirements of the host can change over time, such as when a new application is launched on the host, when a currently running application is closed, or when user needs for the application change. However, equipping a host with enough main memory to handle the highest foreseeable demands can be costly. Additionally, cable length limitations that may exist for some interfaces between the host central processing unit (CPU) and storage may limit the capacity available to the storage (eg, to capacity available within the same rack as the host CPU).

Therefore, some embodiments create a mechanism that allows host applications to access memory pools beyond the local rack level using normal load and store commands. Such embodiments may combine a cache-coherent interface to an interface circuit (eg, a Compute Express Link (CXL) interface) that may operate as the front-end of a memory pool with a low-latency remote memory access protocol that operates as the back-end of a memory pool. (e.g., RDMA) memory pool. The system can dynamically allocate resources through interface circuits and shared memory pools. Such embodiments may enable the decomposition of memory into physically separate memory resources (e.g., resources that do not need to be in the same rack as the processing circuitry that uses those resources), thus avoiding the need for some memory interface links (e.g., peripheral-based Component Interconnect Express (PCIe) links such as CXL, which may have cable length limitations such as between 8 inches (PCIe Gen 3) and 15 inches (PCIe Gen 1)) .

In some embodiments, a host can access a pool of memory using load and store semantics and avoid the need to implement physical resources, such as dynamic random access memory (DRAM), on devices within the same rack as the host. Exploded memory (via a low-latency remote memory access protocol (e.g., RDMA)) can be used to allocate resources at runtime. In some embodiments, the interface circuits can be reconfigured to any size and mapped to remote memory pools, and the remote memory pools can provide flowing memory that can be dynamically combined to meet the needs of the server in a composable disaggregated memory architecture. Resource collection. Some embodiments result in lower total cost of ownership (TCO) and overcome the cable constraints present in some interfaces by supporting long-distance memory disaggregation via RDMA (which is compatible with cables having lengths greater than, for example, 6 feet). Line length limit.

Referring to FIG. 1A , in some embodiments, computing system 100 includes a host 102 including a central processing unit (CPU) 105 (which may be or include processing circuitry) and local memory 110 (which may be double data rate (DDR) memory) )) and the memory system 115. The memory system may include interface circuitry 120 that includes a front-end interface 130 with a cache-coherent memory access protocol (e.g., cxl.mem) and a back-end interface 135 with low-latency remote memory access capabilities (e.g., RDMA enabled network interface card). Front-end interface 130 may be a CXL interface (eg, CXL.mem); in this case, interface circuit 120 may be referred to as a CXL device. Storage pool server 125 may include a backend interface 135 and a storage pool 140 . Memory pool 140 may include, for example, a bank of dynamic random access memory configured as memory modules, each memory module including a plurality of memory chips on a printed circuit board. The storage may be directly connected to the backend interface 135 of the storage pool server 125, or some or all of the storage may be implemented in one or more storage servers connected to the storage pool server 125 through a computer cluster interconnect interface.

Front-end interface 130 may be connected to the address bus and data bus of CPU 105 . Thus, from the perspective of the CPU 105 , the storage provided by the memory system 115 may be substantially the same as the local memory 110 and, in operation, the addresses of load and store instructions are within the physical address range assigned to the interface circuit 120 , memory system 115 may respond directly to load and store instructions executed by CPU 105. This ability of memory system 115 to respond directly to load and store instructions executed by CPU 105 may eliminate the need for the CPU to call driver functions to store data in or retrieve data from memory system 115 .

The host 102 may view the interface circuit 120 as a CXL device that advertises its memory resources to the host 102 through CXL discovery. For example, an appropriate value stored in a base address register (BAR) in the CXL interface of interface circuit 120 may determine the size of the memory address range allocated to interface circuit 120 . On startup, to determine the size of memory available through the interface circuit 120, the CPU may write a word of all binary ones to the appropriate base address register, and then read the same base address register; in response, the interface circuit 120 may Sends a word indicating the size of the available memory area. Host 102 may use memory resources by executing load instructions or store instructions of the instruction set of CPU 105 .

Figure IB illustrates a method that may be employed at startup. In some embodiments, upon startup, the RDMA network interface controller 135 in the interface circuit 120 sends a discovery message to the memory pool server 125 at 155 . The memory pool server 125 then responds to the discovery message at 160 with a response reporting the capabilities of the memory pool server 125. Reported capabilities may include, for example, storage pool server 125 capacity, storage pool server 125 bandwidth, and storage pool server 125 latency. RDMA network interface controller 135 may maintain this capability information and provide the capability information to memory interface 130 for CXL booting at 165 . Memory interface 130 may then perform CXL startup at 170 and provide memory related information to host 102 using a consistent device attribute table (CDAT) (which may be employed under the CXL standard to send memory information to the host).

The connection between interface circuit 120 and memory pool server 125 may be a remote direct memory access connection, as shown. The remote direct memory access connection may include cable 145 (eg, a power cable (having multiple conductors) or an optical cable (including multiple optical fibers)). Cable 145 may form a connection between backend interface 135 in interface circuit 120 and another backend interface 135 in storage pool server 125 . The interface between the RDMA network interface controllers 135 may be Ethernet or any other suitable computer cluster interconnect interface, such as Infini Band or Fiber Channel.

Configuration of the backend interface 135 of the interface circuit 120 may include communicating with the memory pool server 125 using an Internet Protocol (IP) address of the memory pool server 125 (which may be part of the configuration of the backend interface 135 ). The interface circuit 120 may negotiate with the memory pool server 125 at startup for memory resources and establish a remote direct memory access connection with the RDMA server to perform read or write operations.

From the perspective of host 102, interface circuit 120 may be a CXL Type 3 device. In operation, the remote direct memory access system may generate one or more queue pairs (QPs) and register one or more memory regions (MRs). In response to load and store operations performed by CPU 105 of host 102, the queue pairs and memory regions may then be used to perform remote direct memory access read operations and remote direct memory access write operations.

For example, when CPU 105 of host 102 executes a store instruction to store a first value in a first memory location at a first address, the first address is mapped to interface circuit 120 , interface circuit 120 may receive the store instruction ( As a result of the first address being mapped to interface circuit 120 ), and in response to executing the store instruction, interface circuit 120 may send a store command to memory pool server 125 . The store command may be sent via remote direct memory access; for example, to store the first value in memory pool 140 of memory pool server 125 , interface circuit 120 may initiate a remote direct memory access write transfer to store the first value in in the memory pool 140.

As another example, if CPU 105 of host 102 executes a load instruction to load a value in a second memory location at a second address into a register of CPU 105 , the second address is mapped to interface circuit 120 , then the interface Circuitry 120 may receive a load instruction (as a result of the second address being mapped to interface circuitry 120 ), and in response to executing the load instruction, interface circuitry 120 may send a read command to memory pool server 125 . A read command may be sent via remote direct memory access; for example, to read a value stored in memory pool 140 of memory pool server 125 , interface circuit 120 may initiate a remote direct memory access read transfer to read from memory pool 140 Take value.

CXL 2.0 supports hot-swappable features. Therefore, in embodiments where front-end interface 130 is a CXL interface, new connections can be made to interface circuit 120 while the host is operating, or interface circuit 120 can be disconnected while the host is operating, without disturbing the operation of the host. In some embodiments, the latency of memory system 115 is sufficiently low (eg, as a result of using a low latency protocol such as Infini Band or RDMA) to enable support of the cache coherence preservation feature of CXL.cache.

Referring to FIG. 1C , in some embodiments, a graphics processing unit (GPU) 148 is connected to the CPU 105 and interface circuitry 120 . For example, the connection may be made through CXL switch 150 . In some embodiments, graphics processing unit 148 is part of host 102 , as shown; in other embodiments, graphics processing unit 148 may be the primary processing circuitry of another host, or graphics processing unit 148 may be a separate CXL A device (eg, a Type 2 CXL device) that is not part of the host 102 and is connected to the host through a CXL link like the interface circuit 120 . In some embodiments, graphics processing unit 148 is in a Type 2 CXL device.

Additionally, as shown in FIG. 1C , in some embodiments, multiple memory pool servers 125 are connected to the RDMA network interface controller 135 of the interface circuit 120 . Each of the storage pool servers 125 may be connected to the interface circuit 120 via any suitable type of connection (eg, Ethernet, Infini band, or Fiber Channel), as shown. Interface circuit 120 may include a single RDMA network interface controller 135 capable of supporting multiple respective connections to multiple memory pool servers 125, as shown, or interface circuit 120 may include multiple RDMA network interface controllers 135 or have multiple A NIC of physical interfaces, each physical interface connected to the memory interface 130 of the interface circuit 120 and each physical interface (i) connected to a corresponding one of the memory pool servers 125 and (ii) configured to support the memory interface 130 on the interface circuit 120 The protocol used in the connection to the corresponding storage pool server 125 (such as Ethernet, Infini band, or Fiber Channel). For example, a connection formed using Infiniband may have lower latency than a connection using Ethernet. Such a connection (for example, one using Infini band) can satisfy the latency requirements of one or more of the three CXL protocols (cxl.io, cxl.mem, and cxl.cache).

Referring to FIG. 1D, in some embodiments, the memory pool servers 125 are configured differently. For example, one of the memory pool servers 125 may include a memory pool 140a optimized for high bandwidth, and one of the memory pool servers 125 may include a memory pool 140a optimized for low bandwidth. A latency-optimized memory pool 140b, and one of the memory pool servers 125 may include a memory pool 140c optimized for high capacity. In some embodiments, the type of connection employed to connect the storage pool server 125 to the interface circuit 120 may be selected to provide a certain level of performance to the host 102 . For example, an Infini band connection, which may have relatively low latency, may be used to connect a memory pool server 125 including a memory pool 140b optimized for low latency to the interface circuit 120 such that the total latency experienced by the host 102 is due to Reduce: (i) the type of memory pool 140 used and (ii) the type of connection used to connect the memory pool server 125 to the interface circuit 120.

In some embodiments, applications running on host 102 may require different characteristics of memory; for example, applications may require low latency memory for performance reasons. In some embodiments, such applications may be aware of the different performance characteristics of different memory pool servers 125 connected to the host 102 through the interface circuitry 120 . The application may access this information as a result of the boot process (described above), which may cause the information to be stored in the host (eg, via the operating system of host 102). The application, when it requests memory from the operating system, can then request memory with performance characteristics that will result in acceptable performance for the application.

Referring to FIG. 2 , in some embodiments, multiple hosts may each be connected to the memory pool server 125 and share the memory resources of the memory pool server 125 . As in the embodiment of FIG. 1A , each interface circuit 120 provides a memory device with a configured dynamic memory size to a corresponding host without requiring physical memory resources (eg, DRAM memory) to be physically present in the interface circuit 120 . A pool of decomposed memory resources may be created, for example, in one or more memory servers, and it may be placed at a remote location. A remote collection of memory servers may be called a memory farm. Memory resources may be accessed using low latency network protocols, such as remote direct memory access; in such embodiments, memory resources may be used efficiently and total cost of ownership (TCO) may be reduced.

Referring to Figure 3, as discussed above, interface circuitry 120 may occupy a portion of the physical address space of CPU 105. Host 102 may also include (in addition to CPU 105 and local memory 110) a CXL root complex 305, which may form an interface on the host side to the CXL link of Figure 1A. In some embodiments, during operation, the host writes to the physical address space mapped CXL-DRAM and the request is sent to the CXL root complex 305 (via the address bus and data bus of the CPU 105), the CXL root complex 305 Transaction layer packets (TLPs) are generated and sent to interface circuitry 120, and interface circuitry 120 converts the transaction layer packets into remote direct memory accesses and sends the remote direct memory accesses through the computer cluster interconnect interface.

Figure 4 shows an embodiment including a CXL switch 405. Each of the plurality of hosts 102 is connected to a CXL switch 405 (which may be or may include, for example, a CXL 2.0 switch) that is connected to one or more interface circuits 120 (each interface circuit is labeled in FIG. 4 "IC") and zero or more other CXL devices 410 (each CXL device is labeled "D" in Figure 4). Interface circuit 120 may be connected to a single shared memory pool server 125 via a remote direct memory access connection (as shown), or the interface circuit 120 may be connected to multiple memory pool servers 125 (e.g., each interface circuit 120 may be connected to to the corresponding storage pool server 125).

Figure 5 is a flow diagram of a method in some embodiments. The method includes, at 505, executing, by the central processing unit, a store instruction for storing a first value in a first memory location at a first address; and at 510, in response to executing the store instruction, causing, by the interface circuitry, a store instruction to store a first value in a first memory location at a first address. A store command is sent to a memory including a first memory location, the store command being a command to store a first value in the first memory location. The method may also include, at 515, executing, by the central processing unit, a load instruction to read a second value, which may be stored in a second memory location at a second address; and at 520 At, a read command is sent by the interface circuit to the memory including the second memory location in response to executing the load instruction, the read command being a command to read the second value from the second memory location.

As used herein, a computer cluster interconnect interface is any interface suitable for interconnecting computers, such as InfiniBand, Ethernet, or Fiber Channel.

As used herein, a "portion" of something means "at least some" of the thing, and may equally mean less than all of the thing or all of the thing. Likewise, a "part" of a thing includes the whole thing as a special case, that is, the instance of which the whole thing is a part. As used herein, when the second amount is "within Y" of the first amount X, it is meant that the second amount is at least X-Y and the second amount is at most X+Y. As used herein, when a second value is "within Y%" of a first value, it is meant that the second value is at least (1-Y/100) times the first value, and that the second value is at most (1+Y/100) times the number of values. As used herein, the term "or" shall be construed as "and/or" such that, for example, "A or B" means either "A" or "B" or "A and B."

The background provided in the Background section of this disclosure is included only to set the context and the contents of this section are not deemed to be prior art. Any component or combination of components described (eg, in any system diagram included herein) may be used to perform one or more operations of any flowchart included herein. Furthermore, (i) the operations described are exemplary operations and may include various additional steps not expressly covered, and (ii) the temporal order of the operations described may vary.

The terms "processing circuitry" and "means for processing" are each used herein to mean any combination of hardware, firmware, and software for processing data or digital signals. Processing circuit hardware may include, for example, application specific integrated circuits (ASICs), general or special purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable devices such as field programmable gate arrays (FPGAs). logical device. As used herein, in processing circuitry, each function is performed by hardware configured to perform that function (i.e., hardwired), or more generally by hardware configured to execute instructions stored in a non-transitory storage medium hardware (such as CPU) to execute. Processing circuitry can be fabricated on a single printed circuit board (PCB) or distributed across several interconnected PCBs. The processing circuit may include other processing circuitry; for example, the processing circuit may include two processing circuits, an FPGA and a CPU, interconnected on a PCB.

As used herein, when a method (eg, an adjustment) or a first quantity (eg, a first variable) is said to be "based on" a second quantity (eg, a second variable), it means that the second quantity is the The method inputs or affects the first quantity, e.g., the second quantity can be an input to a function that computes the first quantity (e.g., the only input, or one of several inputs), or the first quantity can be equal to the second quantity, or The first quantity may be the same as the second quantity (eg, stored in the same location or locations in memory as the second quantity).

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, Layers and/or segments shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the inventive concept.

For ease of description, terms such as "beneath," "below," or "beneath" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms such as "lower", "under", "above", "upper", etc. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" may encompass both upper and lower orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree and are intended to describe inherent variations in measured or calculated values that would be recognized by one of ordinary skill in the art .

As used herein, the singular forms "a," "an" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprise" and/or "comprising" designate the presence, but not the presence, of stated features, integers, steps, operations, elements and/or parts. Excludes the presence or addition of one or more other features, integers, steps, operations, elements, parts and/or combinations thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one" when used after a list of elements modify the entire list of elements without modifying the individual elements in the list. Furthermore, when describing embodiments of the inventive concept, the use of "may" means "one or more embodiments of the present disclosure." Additionally, the term "exemplary" is intended to refer to an example or illustration. As used herein, the terms "use", "using" and "used" may be considered to be equivalent to the terms "utilize", "utilizing" and "utilized" respectively. "Synonymous.

It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly "on," "connected to," "Coupled to" or "adjacent to" another element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly adjacent" another element or layer, there are no intervening elements or layers present.

Any numerical range recited herein is intended to include all subranges containing the same numerical precision within the recited range. For example, a range of "1.0 to 10.0" or "between 1.0 and 10.0" is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a value equal to or greater than 1.0 Minimum value and maximum value equal to or less than 10.0, e.g. like 2.4 to 7.6. Similarly, a range described as "within 35% of 10" is intended to include the recited minimum value of 6.5 (i.e., (1–35/100) times 10) and the recited maximum value of 13.5 (i.e., (1+35 /100) times 10) (and inclusive), i.e., have a minimum value equal to or greater than 6.5 and a maximum value equal to or less than 13.5, e.g. like 7.4 to 10.6. Any maximum numerical limitations recited herein is intended to include any lower numerical limitations contained therein, and any minimum numerical limitations recited herein is intended to include any higher numerical limitations contained therein.

Some embodiments include features listed in the following numbered statements.

1. A system including:

Interface circuit, which has:

a first interface configured to connect to the processing circuit; and

a second interface, configured to connect to the memory,

the first interface includes a cache coherence interface, and

The second interface is different from the first interface.

2. The system of statement 1, further comprising a memory server connected to the second interface.

3. The system of Statement 1 or Statement 2, wherein the second interface includes a remote direct memory access interface.

4. The system of any one of the preceding statements, wherein the second interface includes a computer cluster interconnect interface.

5. The system of statement 4, wherein the computer cluster interconnect interface includes an Ethernet interface.

6. The system of any one of statements 2 to 5, wherein the memory server is connected to the second interface by a cable having a length greater than 6 feet.

7. The system of any one of the preceding statements, wherein the cache coherence interface includes a Compute Express Link (CXL) interface.

8. The system of any one of the preceding statements, wherein the first interface is configured to:

sending data to the processing circuit in response to a load instruction executed by the processing circuit; and

Data is received from the processing circuit in response to store instructions executed by the processing circuit.

9. The system of any one of the preceding statements, further comprising a Computational Express Link (CXL) root complex connected between the processing circuitry and the first interface.

10. A system comprising:

Interface circuit, the interface circuit has:

a first interface configured to connect to the processing circuit; and

a second interface configured to connect to the memory,

the first interface includes a Compute Express Link (CXL) interface, and

The second interface is different from the first interface.

11. The system of statement 10, further comprising a memory server connected to the second interface.

12. The system of Statement 10 or Statement 11, wherein the second interface includes a remote direct memory access interface.

13. The system of any one of statements 10 to 12, wherein the second interface includes a computer cluster interconnect interface.

14. The system of any one of statements 10 to 13, wherein the computer cluster interconnect interface includes an Ethernet interface.

15. The system of any one of statements 10 to 14, wherein the memory server is connected to the second interface by a cable having a length greater than 6 feet.

16. The system of any one of statements 10 to 15, wherein the CXL interface includes a cache coherence interface.

17. The system of any one of statements 10 to 16, wherein the first interface is configured to:

sending data to the processing circuit in response to a load instruction executed by the processing circuit; and

Data is received from the processing circuit in response to store instructions executed by the processing circuit.

18. The system of any one of statements 10 to 17, further comprising: a CXL root complex connected between the processing circuitry and the first interface.

19. A method comprising:

a store instruction executed by the central processing unit for storing a first value in a first memory location at a first address,

and sending, by the interface circuit to a memory including the first memory location, a store command in response to the execution of the store instruction, the store command being for storing the first value in the first memory location. The command,

The interface circuit has:

a first interface connected to the central processing unit; and

a second interface, the second interface being connected to the memory,

the first interface includes a Compute Express Link (CXL) interface, and

The second interface is different from the first interface.

20. The method of statement 19, further comprising:

execution by the central processing unit of a load instruction for loading a value in a second memory location at a second address into a register of the central processing unit,

A read command is sent by the interface circuit to the memory in response to the execution of the load instruction, the read command being a command to read a value in the second memory location.

Although exemplary embodiments of interfaces for remote memory have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it should be understood that interfaces for remote memory constructed in accordance with the principles of the present disclosure may be implemented differently than as specifically described herein. The invention is also defined in the appended claims and their equivalents.

Claims (20)

1. A system, comprising:

an interface circuit, the interface circuit having:

a first interface configured to be connected to a processing circuit; and

a second interface configured to connect to a memory,

the first interface includes a cache coherency interface, and

the second interface is different from the first interface.

2. The system of claim 1, further comprising a memory server connected to the second interface.

3. The system of claim 2, wherein the second interface comprises a remote direct memory access interface.

4. The system of claim 2, wherein the second interface comprises a computer cluster interconnect interface.

5. The system of claim 4, wherein the computer cluster interconnect interface comprises an ethernet interface.

6. The system of claim 2, wherein the memory server is connected to the second interface by a cable having a length greater than 6 feet.

7. The system of claim 1, wherein the cache coherence interface comprises a computing quick link (CXL) interface.

8. The system of claim 1, wherein the first interface is configured to:

transmitting data to the processing circuitry in response to a load instruction executed by the processing circuitry; and is also provided with

Data is received from the processing circuitry in response to a store instruction executed by the processing circuitry.

9. The system of claim 1, further comprising: a computing fast link (CXL) root complex is coupled between the processing circuitry and the first interface.

10. A system, comprising:

an interface circuit, the interface circuit having:

a first interface configured to be connected to a processing circuit; and

a second interface configured to connect to a memory,

the first interface includes a computing quick link (CXL) interface, an

The second interface is different from the first interface.

11. The system of claim 10, further comprising a memory server connected to the second interface.

12. The system of claim 11, wherein the second interface comprises a remote direct memory access interface.

13. The system of claim 11, wherein the second interface comprises a computer cluster interconnect interface.

14. The system of claim 13, wherein the computer cluster interconnect interface comprises an ethernet interface.

15. The system of claim 13, wherein the memory server is connected to the second interface by a cable having a length greater than 6 feet.

16. The system of claim 13, wherein the CXL interface comprises a cache coherence interface.

17. The system of claim 10, wherein the first interface is configured to:

transmitting data to the processing circuitry in response to a load instruction executed by the processing circuitry; and is also provided with

Data is received from the processing circuitry in response to a store instruction executed by the processing circuitry.

18. The system of claim 10, further comprising: a CXL root complex, the CXL root complex coupled between the processing circuitry and the first interface.

19. A method, comprising:

the store instructions for storing the first value in the first memory location at the first address are executed by the central processing unit,

transmitting, by an interface circuit, a store command to a memory including the first memory location in response to executing the store instruction, the store command being a command to store the first value in the first memory location,

wherein the interface circuit has:

a first interface connected to the central processing unit; and

a second interface, said second interface being connected to said memory,

the first interface includes a computing quick link (CXL) interface, an

The second interface is different from the first interface.

20. The method of claim 19, further comprising:

a load instruction is executed by the central processing unit for loading a value in a second memory location at a second address into a register of the central processing unit,

a read command is sent by the interface circuit to the memory in response to executing the load instruction, the read command being a command to read a value in the second memory location.