CN117727813A - Solar cell and photovoltaic module - Google Patents

Abstract

The embodiment of the application relates to the field of photovoltaics, and provides a solar cell and a photovoltaic module, the solar cell includes: a substrate and a passivation layer on the substrate, the substrate having two first boundaries opposite along a first direction; first fine grids and second fine grids alternately arranged along a first direction; the main grids are arranged along the second direction, are positioned on the surface of the passivation layer and are electrically contacted with the thin grids, and comprise first main grids and second main grids which are alternately arranged along the second direction, wherein the first main grids are electrically contacted with the first thin grids, and the second main grids are electrically contacted with the second thin grids; at least one edge gate line extending along the second direction, the edge gate line being adjacent to the first boundary, the edge gate line of a partial region penetrating the passivation layer and being electrically connected to the substrate, the edge gate line being in electrical contact with the first main gate; and/or the edge gate line is in electrical contact with the second main gate. The solar cell and the photovoltaic module provided by the embodiment of the application can improve the yield of the photovoltaic module.

Description

Solar cells and photovoltaic modules

Technical field

Embodiments of the present application relate to the field of photovoltaics, and in particular to a solar cell and a photovoltaic module.

Background technique

The reasons that affect the photoelectric conversion efficiency and yield of solar cells mainly include two aspects. One is optical loss. Optical loss includes shading loss, carrier recombination loss of the substrate, carrier recombination loss of the highly doped film layer, and The refraction loss of the film layer; the second is the electrical loss. The electrical loss includes the resistance loss of the material itself, the contact loss of the electrode, the contact loss between the soldering ribbon and the solar cell, and the virtual soldering between the soldering ribbon and the solar cell.

Therefore, there is an urgent need in this field to provide a solar cell and photovoltaic module that can reduce electrical loss and optical loss, thereby improving the photoelectric conversion efficiency of the corresponding solar cell and the yield rate of the photovoltaic module.

Contents of the invention

Embodiments of the present application provide a solar cell and a photovoltaic module, which are at least beneficial to improving the yield rate of the photovoltaic module.

According to some embodiments of the present application, on the one hand, embodiments of the present application provide a solar cell, including: a substrate and a passivation layer located on the substrate, the substrate having two first boundaries facing each other along a first direction; Fine gates arranged in a first direction, the fine gates penetrating the passivation layer and electrically connected to the substrate; the fine gates include first fine gates and second fine gates alternately arranged along the first direction. Gate; a plurality of main gates arranged along the second direction, the main gates are located on the surface of the passivation layer and are in electrical contact with the fine gates, the main gates include m ₁ alternately arranged along the second direction m first main grids and m ₂ second main grids, the first main grid is in electrical contact with the first fine grid, the second main grid is in electrical contact with the second fine grid; wherein, the The first main grid is one of the positive electrode or the negative electrode, the second main grid is the other one of the positive electrode or the negative electrode; at least one edge grid line extending along the second direction, the edge grid The line is close to the first boundary, the edge gate line in a partial area penetrates the passivation layer and is electrically connected to the substrate, and the edge gate line is in electrical contact with n ₁ first main gates; and/ Or, the edge gate line is in electrical contact with n ₂ second main gates; wherein, 1<n ₁ ≤m ₁ , 1<n ₂ ≤m ₂ , n ₁ , m ₁ , n ₂ and m ₂ are all is a natural number.

In some embodiments, at least one edge gate line includes: a first edge gate line and a second edge gate line, the first edge gate line is located between the first boundary and the second fine gate, and the A first edge gate line is in electrical contact with the first main gate, the second edge gate line is located between the other first boundary and the first thin gate, and the second edge gate line is in electrical contact with the first main gate. The second busbar is electrically contacted.

In some embodiments, it includes: one edge gate line, the edge gate line is in electrical contact with the first main gate, or the edge gate line is in electrical contact with the second main gate.

In some embodiments, the first fine gate includes a plurality of first sub-gate lines arranged along the second direction, and the passivation layer between two adjacent first sub-gate lines constitutes a second fine gate. a spacer area, the second main gate is located on the first spacer area, the first main gate is in electrical contact with the first sub-gate line; the second fine gate includes rows along the second direction A plurality of second sub-gate lines are arranged, the passivation layer between two adjacent second sub-gate lines forms a second spacer area, and the first main gate is located on the second spacer area; so The second main gate is in electrical contact with the second sub-grid line.

In some embodiments, the width of the edge gate line along the first direction is greater than or equal to the width of the fine gate along the first direction.

In some embodiments, the width range of the edge gate line along the first direction includes: 10um~55um.

In some embodiments, the distance between the edge gate line and the adjacent fine gate is a first distance, and the first distance is less than or equal to the distance between the adjacent first fine gate and the second fine gate. distance.

In some embodiments, the first spacing ranges from 0.2 mm to 0.7 mm.

In some embodiments, the distance between adjacent first fine gates and second fine gates ranges from 0.3 mm to 0.8 mm.

In some embodiments, the edge gate lines are made of the same material as the thin gate.

In some embodiments, the edge gate line is in electrical contact with n ₁ first main gates; the edge gate line is in electrical contact with n ₂ second main gates; 1<n ₁ <m ₁ , 1＜n ₂ ＜m ₂ .

According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a photovoltaic module, including: a battery string connected by a plurality of solar cells as described in any one of the above embodiments; the solar cells It includes an edge grid line, a first main grid and a second main grid; a connecting component used to electrically connect the first main grid and the second main grid of two adjacent solar cells; and an encapsulating adhesive film for Covering the surface of the battery string; a cover plate used to cover the surface of the packaging film facing away from the battery string.

In some embodiments, it also includes: electrical connection lines; the edge grid lines are in electrical contact with n ₁ first main grids, and the electrical connection lines electrically connect the edge grid lines with adjacent solar cells. The second main grid; or, the edge grid line is in electrical contact with n ₂ second main grids, and the electrical connection line electrically connects the edge grid line with the first first side of the adjacent solar cell. main grid.

The technical solutions provided by the embodiments of this application have at least the following advantages:

In the solar cell provided by the embodiment of the present application, the edge grid line is in electrical contact with the first main grid, and/or the edge grid line is in electrical contact with the second main grid. One grid line is used to connect the same electrode in the solar cell. The linear grid lines (positive electrode or negative electrode) are connected in series, and a solar cell forms an integral electrode, thereby ensuring that the first main grid and each first fine grid are in a state of mutual conduction, thus It is possible to avoid the probability of a decrease in the efficiency and yield of the battery due to a problem with one of the first main grids, and when the first fine grids are all in a conductive state, the first fine grids located at the edge of the substrate can also be collected to improve the efficiency of the battery. Collection efficiency. In the same way, the battery efficiency can also be improved by improving the battery collection efficiency of the second fine grid.

In addition, since they are all in a conductive state, it is possible to avoid the problem of poor appearance between the first main gates and the first fine gates due to different preparation processes. The interconnection between the first main grids and the interconnection between the second main grids can also avoid the problem of reduced battery efficiency caused by one of the fine grids or the main grid being broken.

Description of the drawings

One or more embodiments are exemplified by the figures in the corresponding drawings. These illustrative illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the accompanying drawings do not constitute a scale limit; in order to To more clearly illustrate the technical solutions in the embodiments of the present application or traditional technologies, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic structural diagram of a solar cell provided by an embodiment of the present application;

Figure 2 is a partial structural schematic diagram of a solar cell provided by an embodiment of the present application;

Figure 3 is a schematic cross-sectional structural diagram along the A1-A2 section of Figure 2;

Figure 4 is a schematic cross-sectional structural diagram along the B1-B2 section of Figure 2;

Figure 5 is another structural schematic diagram of a solar cell provided by an embodiment of the present application;

Figure 6 is an arrangement diagram of grid lines in a solar cell provided by an embodiment of the present application;

Figure 7 is a schematic structural diagram of a photovoltaic module provided by another embodiment of the present application;

Figure 8 is a schematic cross-sectional structural diagram along the M1-M2 section of Figure 7;

FIG. 9 is a schematic structural diagram of a solar cell in a photovoltaic module provided by another embodiment of the present application.

Detailed ways

It can be known from the background art that the current yield rate of solar cells and photovoltaic modules is not good.

The analysis found that one of the reasons for the poor yield of solar cells and photovoltaic modules is that the current back contact solar cells, that is, the first electrode and the second electrode in the IBC cell are located on the back of the substrate, and also include the first electrode. The main grid and the second main grid, the first electrode is in electrical contact with the corresponding first main grid, the second electrode is in electrical contact with the corresponding second main grid, the extension direction of the first electrode intersects with the first main grid, and the second main grid is in electrical contact with the first main grid. The intersection of the extension direction of the electrode and the second main grid involves the electrical insulation between the first electrode and the second main grid with different polarity, and the electrical insulation between the second electrode and the first main grid with different polarity. There is an electrical connection between the first main grid and part of the first electrode. The first main grid is electrically insulated from the other first electrodes and the first main grid cannot collect all the carriers of the first electrode. When one of the first main grids is When there is a problem with the main grid or there is a problem of poor welding between the first main grid and the welding strip, it may cause that the multiple first electrodes connected to the first main grid cannot be collected, thus affecting the quality of solar cells and photovoltaic modules. Rate. In the same way, the second busbar also has the same problem, which affects the yield of solar cells and photovoltaic modules.

Embodiments of the present application provide a solar cell. The solar cell includes an edge grid line, electrical contact between the edge grid line and the first main grid, and/or electrical contact between the edge grid line and the second main grid. A grid is used. The lines connect the grid lines of the same polarity (positive electrode or negative electrode) in the solar cell to each other in series. One solar cell forms an overall electrode, thus ensuring that there is a gap between the first main grid and each first fine grid. The state of conduction with each other can avoid the probability of the efficiency and yield of the battery being reduced due to a problem with one of the first main gates, and the state of the first fine gates being conductive can also make the first fine gate located at the edge of the substrate Fine grid collection improves the collection efficiency of the battery. In the same way, the battery efficiency can also be improved by improving the battery collection efficiency of the second fine grid.

In addition, since they are all in a conductive state, the problem of poor appearance between the first main gates and the first fine gates due to different preparation processes can also be avoided. The interconnection between the first main grids and the interconnection between the second main grids can also avoid the problem of reduced battery efficiency caused by one of the fine grids or the main grid being broken.

Each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are provided to enable readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in this application can also be implemented.

Figure 1 is a schematic structural diagram of a solar cell provided by an embodiment of the present application; Figure 2 is a partial structural schematic diagram of a solar cell provided by an embodiment of the present application; Figure 3 is a cross-section along A1-A2 of Figure 2 Schematic cross-sectional structure diagram; Figure 4 is a schematic cross-sectional structural diagram along the B1-B2 section in Figure 2.

Referring to Figures 1 and 3, on the one hand, embodiments of the present application provide a solar cell, including: a substrate 100 and a passivation layer 102 located on the substrate 100. The substrate 100 has two first boundaries 101 opposite along the first direction Y. ; Fine gates 110 arranged along the first direction, the fine gates 110 penetrate the passivation layer 102 and are electrically connected to the substrate 100 ; The fine gates 110 include first fine gates 111 and second fine gates alternately arranged along the first direction X 112; _A plurality of main grids 120 arranged along the second direction The first main grid 121 and m ₂ second main grids 122, the first main grid 121 is in electrical contact with the first fine grid 111, and the second main grid 122 is in electrical contact with the second fine grid 112; wherein, the first main grid 121 is one of the positive electrode or the negative electrode, the second main grid 122 is the other one of the positive electrode or the negative electrode; at least one edge grid line 113 extending along the second direction X, the edge grid line 113 is close to the first boundary 101 , the edge gate line 113 in a partial area penetrates the passivation layer 102 and is electrically connected to the substrate 100. The edge gate line 113 is in electrical contact with n ₁ first main gates 121; where, 1<n ₁ ≤m ₁ , n ₁ , m ₁ is a natural number.

In some embodiments, referring to FIG. 3 , the solar cell is a back-contact solar cell, which refers to a solar cell in which electrodes of different polarities (positive electrode and negative electrode) are located on the back side of the substrate.

Referring to FIG. 3 , in some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. Among them, elemental semiconductor materials can be single crystalline, polycrystalline, amorphous or microcrystalline (having both single crystalline and amorphous states is called microcrystalline state). For example, silicon can be single crystalline silicon. , at least one of polycrystalline silicon, amorphous silicon or microcrystalline silicon.

In some embodiments, the material of the substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include but are not limited to silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenide and other materials. The substrate 100 may also be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with N-type doping elements. The N-type doping elements can be phosphorus (P) elements, bismuth (Bi) elements, antimony (Sb) elements or arsenic (As) elements among Group V elements. Any one. The P-type semiconductor substrate is doped with P-type elements. The P-type doping element can be any group III element such as boron (B) element, aluminum (Al) element, gallium (Ga) element or indium (In) element. By.

In some embodiments, the substrate 100 has a first surface 11 and a second surface 12 arranged oppositely. The first surface 11 of the substrate 100 can be a front surface, and the second surface 12 can be a back surface. The front surface can be used as a light-receiving surface for receiving light. Incident light, the back side serves as the backlight surface. Among them, the backlight surface can also receive incident light, but its efficiency in receiving incident light is weaker than that of the light-receiving surface.

It is worth mentioning that the incident light received by the light-receiving surface is directly illuminated by sunlight on the solar cell, and the incident light received by the backlight surface is reflected by the ground, other objects, and the film layer on the substrate. caused by refraction.

In some embodiments, the first surface 11 has a first suede structure 13 that includes a plurality of raised structures 105 . The first surface 11 has a front surface field (FSF), the conductivity type of its doped ions is the same as that of the substrate 100 , and the field passivation effect is used to reduce the surface minority carrier concentration, thereby reducing the surface recombination rate. , and can also reduce series resistance and improve electronic transmission capabilities.

In some embodiments, the substrate 100 has alternately arranged regions I and II. Region I is one of the P region or the N region. Region II is the other one of the P region or the N region. The P region and the N region are alternately arranged. There is a gap between the regions, the first fine gate 111 is located in region I, and the second fine gate 112 is located in region II.

In some embodiments, there is no gap between the P region and the N region, and there is an insulating film layer between the P region and the N region to achieve insulation between the P region and the N region, thereby realizing the connection between the first thin gate 111 and the first thin gate 111 . The second fine gate 112 is insulated.

In some embodiments, the substrate 100 also has a region III. The region III is located at the edge of the substrate 100. The region III has the same characteristics as the adjacent region I or II. For example, the region III is adjacent to the region I as shown in Figure 3. It is set that there is a gap between area III and area I, and the polarity of area III is the same as the polarity of area I. For example, area I is an N area, then area III is also an N area. In some embodiments, the polarity of region III is different from the polarity of region I. For example, region I is an N region, and region III is a P region. Then the edge gate line located on region III is in electrical contact with the second main gate.

In some embodiments, referring to FIG. 3 , the gap region is flush with the P region and the N region, that is, the substrate 100 is not etched, and the P region and the N region are insulated by some isolating film layers. The isolation film layer may be the passivation layer 102 .

In some embodiments, the gap region gap is lower than the P region and the gap region gap is lower than the N region. The gap region gap has a trench extending from the second surface toward the first surface. The trench is used to realize regions of different conductivity types. The automatic isolation between them can eliminate the leakage caused by the PN junction formed by the heavily doped P region and N region in the IBC battery (Interdigitated Back Contact), which affects the battery efficiency.

In some embodiments, the surface of the gap region may have a polished surface structure, and the surface of the gap region may have a second suede structure. The roughness of the first suede structure is greater than or equal to the roughness of the second suede structure.

Among them, "roughness" refers to the arithmetic mean of the absolute values of the vertical deviations of the peaks and troughs within the sampling length from the average horizontal line when an average horizontal line is set in a sampling length. Roughness can be measured by comparison method, light section method, interference method and needle drawing method.

In some embodiments, the solar cell includes a first dielectric layer 143 and a first doped semiconductor layer 144 located in region I and a second dielectric layer 153 and a second doped semiconductor layer 154 located in region II; passivation layer 102 Covering the first doped semiconductor layer 144 and the second doped semiconductor layer 154 , the first fine gate 111 penetrates the electrical contact between the passivation layer 102 and the first doped semiconductor layer 144 , and the second fine gate 112 penetrates the passivation layer 102 electrically contacts the second doped semiconductor layer 154 .

In some embodiments, the film layer arrangement on the III region is the same as the film layer arrangement on the I region, that is, there is a first dielectric layer and a first doped semiconductor layer on the III region, and the edge gate line penetrates the passivation layer and the first doped semiconductor layer. The hybrid semiconductor layer is in electrical contact. In some embodiments, the film layer arrangement in the III region is the same as that in the II region, that is, there is a second dielectric layer and a second doped semiconductor layer on the III region, and the edge gate line penetrates the passivation layer and the second doped semiconductor layer. The hybrid semiconductor layer is in electrical contact.

In some embodiments, the first doped semiconductor layer 144 is doped with one of an N-type doping element or a P-type doping element, and the second doped semiconductor layer 154 is doped with an N-type doping element or a P-type doping element. The other type of doping element.

In some embodiments, at least one of the first dielectric layer 143 or the second dielectric layer 153 may be a tunnel dielectric layer, and the material of the tunnel dielectric layer includes silicon oxide or silicon carbide.

In some embodiments, at least one of the first doped semiconductor layer 144 or the second doped semiconductor layer 154 may be a doped amorphous silicon layer, a doped polysilicon layer, a doped microcrystalline silicon layer, or a doped silicon carbide layer. layer or doped crystalline silicon layer.

In some embodiments, the solar cell may include a first intrinsic dielectric layer, a first doped amorphous silicon layer and a first transparent conductive layer located on the I region; the first intrinsic dielectric layer is located on the second surface, and the first The doped amorphous silicon layer is located on the first intrinsic dielectric layer, the first transparent conductive layer is located on the first doped amorphous silicon layer; the second intrinsic dielectric layer and the second doped amorphous silicon layer are located on the II region; The second transparent conductive layer, the second intrinsic dielectric layer is located on the second surface, the second doped amorphous silicon layer is located on the second intrinsic dielectric layer, and the second transparent conductive layer is located on the second doped amorphous silicon layer. Wherein, the first doped amorphous silicon layer is doped with one of N-type doping elements or P-type doping elements, and the second doped amorphous silicon layer is doped with N-type doping elements or P-type doping elements. Another of the doping elements.

Continuing to refer to FIG. 3 and FIG. 4 , the solar cell further includes: a front passivation layer 103 covering the front surface of the substrate 100 .

In some embodiments, the material of at least one of the front passivation layer 103 and the passivation layer 102 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, titanium oxide, hafnium oxide, aluminum oxide, etc. one or more of the materials.

In some embodiments, at least one of the front passivation layer 103 and the passivation layer 102 includes a stacked film layer, the stacked film layer includes at least a first passivation layer and a second passivation layer, the first passivation layer The material may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, titanium oxide, hafnium oxide or aluminum oxide. The material of the second passivation layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, titanium oxide, hafnium oxide or aluminum oxide.

In some embodiments, the material of the front passivation layer 103 is the same as the material of the passivation layer 102, and the front passivation layer 103 and the passivation layer 102 are prepared in the same preparation process.

In some embodiments, the first fine gate 111 , the second fine gate 112 and the edge gate line 113 are all made of burn-through slurry, wherein the first fine gate 111 burns through the passivation layer 102 and connects with the first fine gate 111 . The doped semiconductor layer 144 is in electrical contact, the second fine gate 112 burns through the passivation layer 102 and is in electrical contact with the second doped semiconductor layer 154, and the edge gate line 113 burns through the passivation layer 102 and is in electrical contact with the first doped semiconductor layer 144. touch.

For example, the method of forming the first fine gate 111 includes using a screen printing process to print metal paste on the surface of part of the passivation layer 102 . The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel.

Continuing to refer to FIG. 1 , the first fine grid 111 and the second fine grid 112 extend along the second direction X. The first direction Y and the second direction X may be perpendicular to each other, or there may be an included angle less than 90 degrees, for example, 60 degrees. , 45 degrees, 30 degrees, etc., as long as the first direction Y and the second direction X are not the same direction. In order to facilitate explanation and understanding, this embodiment takes the first direction Y and the second direction X that are perpendicular to each other as an example. In a specific application, the first direction Y and the second direction The angle setting between them is adjusted, and the embodiment of the present application does not limit this.

In some embodiments, the substrate includes two second boundaries facing each other along the second direction X. The junction of the first boundary 101 and the second boundary, the junction of the second boundary and another first boundary 101 , the junction of another first boundary 101 and the second boundary, and the junction of the second boundary and the first boundary 101 There are chamfers at the corners. The reason for the chamfers is that in conventional solar cells, due to the limitations of the single crystal silicon refining process for preparing the substrate, single crystal silicon rods can only be made into round shapes. After the silicon rods are cut out, they are sliced. The cross-section of the rod is cut into the shape of a single crystal silicon wafer (after the area is calculated, it can not only maximize the illumination area in one unit, but also save the silicon rod material to the maximum extent, and also facilitate the production of cells and components). Chamfers are provided at the junctions of the various boundaries of the substrate to reduce the stress on the outside of the silicon wafer and avoid micro damage to the corners of the silicon wafer.

In some embodiments, providing the edge gate line 113 can increase the collection rate of current generated by the substrate at the first boundary. The second is to set the edge grid line 113 to be in electrical contact with the first main grid to achieve electrical connection between all the first fine grids 111 and the first main grid 121, thereby increasing the battery collection rate and reducing the battery defective rate.

In some embodiments, setting edge grid lines 113 can increase the collection efficiency of solar cells by 1% to 5% and reduce the defective rate of cells within 5%, thereby improving the photoelectric conversion efficiency of solar cells and the cost-effectiveness of photovoltaic modules.

In some embodiments, the edge gate line 113 is a whole gate line connecting adjacent first main gates 121 , and the extension direction of the edge gate line 113 is perpendicular to the extension direction of the first main gate 121 or the edge gate line 113 The extension direction overlaps with the extension direction of the first fine grid 111. In this way, the printing screen of the existing fine grid 110 can be partially modified or the edge grid line 113 can be printed twice, thereby reducing the improvement of the current process and improving the equipment. compatibility and applicability.

In some embodiments, the edge grid line 113 is a grid line electrically connected to part of the first main grid, and part of the connection grid line is located inside the battery. The solar cell realizes the connection between the first main grid and the third main grid through the edge grid line 113 and the connection grid line. An electrical connection between fine gates 111.

In some embodiments, the edge gate line 113 is made of the same material as the thin gate 110 . The slurry of the edge gate line 113 is the same as that of the fine gate 110 , that is, the edge gate line 113 is composed of a burn-through slurry, and the edge gate line 113 also penetrates the passivation layer and is electrically connected to the corresponding first doped semiconductor layer. , in this way, the edge gate line 113 can not only realize the current penetration of the first main gate 121, but also can collect the current on the substrate surface adjacent to the first boundary 101 by itself, thereby increasing the collection path and improving the efficiency of current collection. .

In some embodiments, the slurry of the edge gate line 113 is the same as the slurry of the main gate 120 , that is, the edge gate line 113 is composed of a non-burn-through slurry, and the edge gate line 113 is located on the surface of the passivation layer. In this way, it can There is no need to lay out regions I and II on the substrate surface below the edge gate line 113 to prevent electrical contact between the edge gate line 113 and the doped region of the other polarity, resulting in a short circuit problem. In addition, the edge gate line 113 can not cause damage to the passivation layer, thereby ensuring the integrity of the passivation layer, thus improving the passivation effect of the passivation layer on the substrate, and helping to reduce the optical loss of the solar cell, thus Improve the photoelectric conversion efficiency of solar cells. In addition, since the non-burn-through slurry does not have excessive glass powder to damage the PN junction, it can effectively reduce metal recombination, increase the open circuit voltage of solar cells, and improve the conversion efficiency of solar cells.

Among them, the traditional slurry includes a mixture of metal powder, glass powder and organic carrier. Non-burn-through slurry refers to a slurry that contains lower glass powder content than traditional slurries. Its burn-through ability is weak during the sintering process and does not require or cannot burn through the passivation layer. Burn-through slurry refers to a slurry with strong burn-through ability during the sintering process and can burn through the passivation layer.

In some embodiments, referring to FIG. 2 , the first fine gate 111 includes a plurality of first sub-gate lines 1111 arranged along the second direction X, and a passivation layer between two adjacent first sub-gate lines 1111 The first spacing area 1112 is formed, the second main grid 122 is located on the first spacing area 1112, and the first main grid 121 is in electrical contact with the first sub-gate line 1111; the second fine grid 112 includes multiple gates arranged along the second direction X. second sub-gate lines 1121. The passivation layer between the two adjacent second sub-gate lines 1121 forms a second spacer region 1122. The first main gate 121 is located on the second spacer region 1122; the second main gate 122 It is in electrical contact with the second sub-gate line 1121.

In some embodiments, the width W1 of the edge gate line 113 along the first direction Y is greater than or equal to the width W2 of the thin gate 110 along the first direction Y. The width W2 of the fine grid 110 along the first direction Y may be at least one of the width of the first fine grid 111 along the first direction Y or the width of the second fine grid 112 along the second direction Y. In this way, the edge gate lines 113 have a larger width to achieve electrical connection between the first main gates 121, and the edge gate lines 113 will not have an excessive impact on the layout of the original gate lines. When the width of the edge gate line 113 is equal to the width of the fine gate 110, the edge gate line 113 can be prepared at the same time as the fine gate 110, which will not affect the original process, thus improving the compatibility of the original equipment and devices, thus reducing the cost. Solar cell preparation costs.

In some embodiments, the width of the edge gate line 113 is larger than the width of the thin gate 110 . Then having a wider edge gate line 113 can increase the collection area and collection probability near the edge of the first boundary 101 , thereby improving collection efficiency. The wider edge gate line 113 can also be used as the end point of the first main gate close to the first boundary. The higher edge gate line 113 can improve the accuracy of the first main gate overlapping the edge gate line 113. Since the edge gate The wires can share the welding pressure of the first main grid, and the first main grid 121 can also be set shorter accordingly, that is, the end of the first main grid 121 close to the first boundary 101 can be flush with or lower than the edge grid line 113 Close to the side of the first boundary 101, the distance between the welding point of the solder strip and the first main grid 121 and the first boundary 101 is relatively far, thereby reducing the probability of battery piece damage.

In some embodiments, the width W1 of the edge gate line 113 along the first direction Y ranges from 10 um to 55 um. The width W1 of the edge gate line 113 along the first direction may be 10um~16um, 16um~22um, 22um~30um, 30um~38um, 38um~46um, or 46um~55um. The width of the edge gate line 113 along the first direction is within any of the above ranges. The edge gate line 113 has a strong ability to collect carriers at the edge. There is a certain distance between the edge gate line 113 and the first boundary 101, thereby reducing the first boundary. Probability of breakage.

In some embodiments, the distance between the edge gate line 113 and the adjacent fine gate 110 is a first distance S1, and the first distance is less than or equal to the distance S2 between the adjacent first fine gate 111 and the second fine gate 112. In this way, the spacing between the edge grid lines 113 and the fine grids 110 is more appropriate. In the layout without wasting the shielding area of the edge grid lines 113 and the fine grids 110, the typesetting between the edge grid lines 113 and the fine grids 110 can realize the layout of the base. The carriers on the solar cell have the smallest migration distance and the smallest migration loss, thereby increasing the open circuit voltage of the solar cell.

It is worth noting that the first spacing shown in Figure 2 of the embodiment of the present application refers to the spacing between the area where the axis of the edge grid line is located and the axis of the adjacent fine grid. The embodiment of the present application does not specify the specific meaning of the first spacing. For limitation, for example, the first spacing can also be the distance between the side of the edge gate line close to the first boundary and the side of the adjacent fine gate away from the first boundary, or the distance between the edge gate line and the adjacent fine gate. The shortest distance is acceptable.

In some embodiments, the first spacing S1 ranges from 0.2 mm to 0.7 mm. The range of the first spacing is 0.2mm~0.35mm, 0.35mm~0.46mm, 0.46mm~0.58mm, 0.58mm~0.63mm or 0.63mm~0.7mm.

In some embodiments, the distance S2 between adjacent first fine gates 111 and second fine gates 112 ranges from 0.3 mm to 0.8 mm. The distance S2 between the adjacent first fine grid 111 and the second fine grid 112 ranges from 0.3mm~0.35mm, 0.35mm~0.43mm, 0.43mm~0.5mm, 0.5mm~0.58mm, 0.58mm~0.66mm, 0.66mm~0.72mm or 0.72mm~0.8mm.

Referring to Figure 5, Figure 5 is another schematic structural diagram of a solar cell provided by an embodiment of the present application. The edge grid line 113 is in electrical contact with the first main grid 121, and the edge grid line 113 is in contact with n ₂ second main grids 122. Electrical contact; 1<n ₂ ≤m ₂ , n ₁ , m ₁ , n ₂ and m ₂ are all natural numbers.

In some embodiments, at least one edge gate line 113 includes: a first edge gate line 1131 and a second edge gate line 1132. The first edge gate line 1131 is located between the first boundary and the second thin gate 112. The gate line 1131 is in electrical contact with the first main gate, the second edge gate line 1132 is located between the other first boundary and the first thin gate 111, and the second edge gate line 1132 is in electrical contact with the second main gate. In the embodiment of the present application, two edge grid lines 113 are provided at the two first boundaries to realize the interconnection between the first main grids and the interconnection between the second main grids, thereby improving the collection efficiency of the solar cell and the solar energy. Battery yield.

In some embodiments, setting the first edge grid lines 1131 to electrically connect each first main grid, and the second edge grid lines 1132 to electrically connect each second main grid can increase the collection efficiency of the solar cell by 3% to 10%. The defective rate of batteries is reduced by less than 8%.

In some embodiments, a grid line is used to connect grid lines of the same polarity (positive electrode or negative electrode) in the solar cell to each other in series, and one solar cell forms an integral electrode, thereby ensuring that the first main grid Each first fine gate 111 is in a mutually conductive state, thereby avoiding the possibility of a decrease in the efficiency and yield of the battery due to a problem with one of the first main gates, and the first fine gates 111 are conductive. The on state can also collect the first fine grid 111 located at the edge of the substrate to improve the collection efficiency of the battery. In the same way, the battery efficiency can also be improved by improving the battery collection efficiency of the second fine grid 112 .

In addition, since they are all in a conductive state, it can also avoid the problem of poor appearance between the first main gates 121 and the first fine gates 111 due to different manufacturing processes. The mutual communication between the first main grids 121 and the mutual communication between the second main grids 122 can also avoid the problem of reduced battery efficiency caused by one of the fine grids 110 or the main grid 120 being broken.

In some embodiments, the edge gate line 113 is in electrical contact with n ₁ first main gates 121; the edge gate line 113 is in electrical contact with n ₂ second main gates 122; 1<n ₁ <m ₁ , 1<n ₂ < m ₂ . Some of the connection grid lines are located inside the battery. The connection grid lines realize the electrical connection between the remaining first main grids 121 and the electrical connection between the remaining second main grids 122. The solar cell communicates with the connection grid lines through the edge grid lines 113. The electrical connection between the first main grid 121 and the first fine grid 111 is realized, and the solar cell realizes the electrical connection between the second main grid 122 and the second fine grid 112 through the edge grid line 113 and the connecting grid line.

In some embodiments, Figure 6 is an arrangement diagram of grid lines in a solar cell provided by an embodiment of the present application. Referring to Figure 6, m ₁ ≥ 8, m ₂ ≥ 8, the number of first main grids can be 8, the number of second main grids can be 8, and the number of main grids can be 16.

In some embodiments, the number of first busbars may be a natural number greater than 8, and the number of second busbars may be a natural number greater than 8.

The embodiment of the present application provides a solar cell. The solar cell includes an edge grid line 113, electrical contact between the edge grid line 113 and the first main grid 121, and/or electrical contact between the edge grid line 113 and the second main grid 122. , use a grid line to connect grid lines of the same polarity (positive electrode or negative electrode) in the solar cell to each other in series, and a solar cell forms an integral electrode, thus ensuring that the first main grid 121 is connected to each third main grid. The fine grids 111 are in a conductive state with each other, thereby avoiding the possibility of a decrease in the efficiency and yield of the battery due to problems with one of the first main grids 121, and the first fine grids 111 are all in a conductive state. The first fine grid 111 located at the edge of the substrate can also be collected to improve the collection efficiency of the battery. In the same way, the battery efficiency can also be improved by improving the battery collection efficiency of the second fine grid 112 .

In addition, since they are all in a conductive state, it can also avoid the problem of poor appearance between the first main gates 121 and the first fine gates 111 due to different manufacturing processes. The mutual communication between the first main grids 121 and the mutual communication between the second main grids 122 can also avoid the problem of reduced battery efficiency caused by one of the fine grids 110 or the main grid 120 being broken.

Accordingly, another aspect of the embodiment of the present application also provides a photovoltaic module, which may include the solar cell provided in the above embodiment. The same or corresponding technical features as those in the above embodiment will not be described in detail here.

Figure 7 is a schematic structural diagram of a photovoltaic module provided by another embodiment of the present application; Figure 8 is a schematic cross-sectional structural diagram along the M1-M2 section of Figure 7; Figure 9 is a schematic structural diagram of a photovoltaic module provided by another embodiment of the present application. Schematic diagram of a solar cell structure.

Referring to FIGS. 7 to 9 , according to some embodiments of the present application, another aspect of the embodiment of the present application further provides a photovoltaic module, including: a battery string connected by a plurality of solar cells 20 as in any one of the above embodiments. into; the solar cell includes an edge grid line 113, a first main grid 121 and a second main grid 122; a connecting component 209, the connecting component 209 is used to electrically connect the first main grid 121 and the second main grid of two adjacent solar cells 20. The main grid 122; the encapsulating film 27 is used to cover the surface of the battery string; the cover plate 28 is used to cover the surface of the encapsulating film facing away from the battery string.

Specifically, in some embodiments, multiple battery strings can be electrically connected through connecting components 209, and the connecting components 209 are welded to the main grids on the battery sheets. For example, one end of the connecting component is electrically connected to the first main grid of the first battery sheet, and the other end of the connecting component is electrically connected to the second main grid of the adjacent second battery sheet.

In some embodiments, there is no gap between the battery sheets, that is, the battery sheets overlap each other.

In some embodiments, the connecting component is welded to the fine grid on the cell sheet.

In some embodiments, referring to FIG. 9 , there are welding points 108 on the solar cell, and the welding points are used to realize welding between the connecting component 209 and the main grid.

In some embodiments, referring to FIG. 8 , the photovoltaic component further includes: an insulating film 206 covering part of the surface of the solar cell 20 , for example, the insulating film 206 covers part of the surface of the first main grid and the first fine grid, so as to When the connecting component is electrically connected to the second main grid, electrical insulation between the second main grid and the first main grid is achieved. The insulating film 206 exposes the surface of the welding point 108 and is also located between the connecting component 209 and the solar cell. , thereby achieving welding between the connecting component and the corresponding main grid, avoiding electrical contact between the connecting component and the main grid of another polarity, thereby improving the yield rate. For example, if the connecting component and the first main grid are welded, the insulating film realizes electrical insulation between the connecting component and the second main grid.

In some embodiments, the encapsulating adhesive film 27 includes a first encapsulating adhesive film and a second encapsulating adhesive film. The first encapsulating adhesive film covers one of the front or the back of the solar cell, and the second encapsulating adhesive film covers the front of the solar cell. Or the other one on the back. Specifically, at least one of the first encapsulation film or the second encapsulation film can be polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer ( Organic packaging films such as EVA) film, polyethylene octene co-elastomer (POE) film or polyethylene terephthalate (PET) film.

It is worth noting that there is a dividing line between the first encapsulating film and the second encapsulating film before the lamination process. After the lamination process, the photovoltaic module is formed and there will no longer be the first encapsulating film and the second encapsulating film. The concept is that the first packaging film and the second packaging film have formed an integral packaging film 27 .

In some embodiments, the cover 28 may be a glass cover, a plastic cover, or other cover with a light-transmitting function. Specifically, the surface of the cover plate 28 facing the encapsulation film 27 may be a concave and convex surface, thereby increasing the utilization rate of incident light. The cover 28 includes a first cover and a second cover. The first cover is opposite to the first encapsulation film, and the second cover is opposite to the second encapsulation film; or the first cover is opposite to one side of the solar cell. , the second cover is opposite to the other side of the solar cell.

In some embodiments, the method further includes: electrical connection lines; the edge grid lines are in electrical contact with n ₁ first main grids, and the electrical connection lines electrically connect the edge grid lines to the second main grids of adjacent solar cells; or, the edge grid lines are electrically connected to n 1 first main grids. The grid lines are in electrical contact with the n ₂ second main grids, and the electrical connection lines electrically connect the edge grid lines and the first main grids of adjacent solar cells. In this way, the electrical connection wires can be used to interconnect the two solar cells, thereby improving the yield of the photovoltaic module and effectively avoiding the problem of yield decline caused by virtual soldering of one of the connecting components.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and spirit of the present application. scope. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims (13)

1. A solar cell, characterized by comprising: A substrate and a passivation layer located on the substrate, the substrate having two first boundaries opposite along a first direction; Fine gates arranged along the first direction, the fine gates penetrating the passivation layer and electrically connected to the substrate; the fine gates include first fine gates and second fine gates alternately arranged along the first direction. fine grid; A plurality of main grids arranged along the second direction. The main grids are located on the surface of the passivation layer and are in electrical contact with the fine grids. The main grids include m _1th main grids alternately arranged along the second direction. One main grid and m ₂ second main grids, the first main grid is in electrical contact with the first fine grid, the second main grid is in electrical contact with the second fine grid; wherein, the first The main grid is one of the positive electrode or the negative electrode, and the second main grid is the other one of the positive electrode or the negative electrode; At least one edge gate line extends along the second direction, the edge gate line is close to the first boundary, and a portion of the edge gate line penetrates the passivation layer and is electrically connected to the substrate, The edge gate line is in electrical contact with n ₁ first main gates; and/or, the edge gate line is in electrical contact with n ₂ second main gates; wherein, 1<n ₁ ≤m ₁ , 1< n ₂ ≤ m ₂ , n ₁ , m ₁ , n ₂ and m ₂ are all natural numbers. 2. The solar cell according to claim 1, wherein at least one edge grid line includes: a first edge grid line and a second edge grid line, the first edge grid line is located between the first boundary and the between the second fine gates, the first edge gate line is in electrical contact with the first main gate, and the second edge gate line is located between the other first boundary and the first fine gate, The second edge gate line is in electrical contact with the second main gate. 3. The solar cell according to claim 1, comprising: one edge grid line, the edge grid line is in electrical contact with the first main grid or the edge grid line is in electrical contact with the second main grid. Main grid electrical contact. 4. The solar cell according to claim 1 or 2, wherein the first fine grid includes a plurality of first sub-grid lines arranged along the second direction, and two adjacent first sub-grid lines The passivation layer between a sub-gate line forms a first spacer area, the second main gate is located on the first spacer area, and the first main gate is in electrical contact with the first sub-gate line; The second fine gate includes a plurality of second sub-gate lines arranged along the second direction. The passivation layer between two adjacent second sub-gate lines constitutes a second spacer region. The first The main gate is located on the second spacer area; the second main gate is in electrical contact with the second sub-gate line. 5. The solar cell according to claim 1, wherein the width of the edge grid line along the first direction is greater than or equal to the width of the thin grid along the first direction. 6. The solar cell according to claim 5, wherein the width range of the edge grid line along the first direction includes: 10um~55um. 7. The solar cell according to claim 1, wherein a spacing between the edge grid lines and the adjacent fine grids is a first spacing, and the first spacing is less than or equal to the adjacent third spacing. The distance between the first fine grid and the second fine grid. 8. The solar cell according to claim 7, wherein the first spacing ranges from 0.2 mm to 0.7 mm. 9. The solar cell according to claim 7, wherein the distance between adjacent first fine grids and second fine grids ranges from 0.3 mm to 0.8 mm. 10. The solar cell according to claim 1, wherein the edge grid line is made of the same material as the thin grid. 11. The solar cell according to claim 1, wherein the edge grid line is in electrical contact with n ₁ first main grids; the edge grid line is in electrical contact with n ₂ second main grids. Contact; 1＜n ₁ ＜m ₁ , 1＜n ₂ ＜m ₂ . 12. A photovoltaic module, characterized by comprising: A battery string connected by a plurality of solar cells according to any one of claims 1 to 11; the solar cells include edge grid lines, a first main grid and a second main grid; A connecting component used to electrically connect the first main grid and the second main grid of two adjacent solar cells; An encapsulating film used to cover the surface of the battery string; A cover plate, used to cover the surface of the encapsulating film facing away from the battery string. 13. The photovoltaic module according to claim 12, further comprising: electrical connection lines; the edge grid lines are in electrical contact with n ₁ first main grids, and the electrical connection lines are electrically connected to the The edge grid line is in electrical contact with the second main grid of the adjacent solar cell; or, the edge grid line is in electrical contact with n ₂ second main grids, and the electrical connection line is electrically connected to the edge grid line and the second main grid of the adjacent solar cell. adjacent to the first main grid of solar cells.