CN117632836A - Data transmission system based on multiple FPGA chips - Google Patents
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Abstract
The invention relates to the technical field of electronic design, in particular to a data transmission system based on a plurality of FPGA chips, which comprises N interconnected FPGA chips, wherein each FPGA chip comprises a plurality of reserved I/O ports, at least one time division multiplexing transmitting end and receiving end, and the FPGA chip F i The transmitting end of the medium time division multiplexing is connected with F through I/O port j Receiving end connection of middle time division multiplexing and F j Receiving end of medium time division multiplexing through F j I/O port connection F of (1) k A receiving end of the medium time division multiplexing; at F i Through F j Forwarding signals to F k When the high-speed serial signal enters F through I/O port j After that and before the input receiving end, is divided into two paths, one path is input into F j Receiving end of middle time division multiplexing, another path directly transmits to F k The scheme disclosed by the invention not only reduces the use of cable, but also can improve the overall performance of the system due to the fact that the delay is very small when the high-speed serial signal is transmitted in a transparent way.
Description
Technical Field
The invention relates to the technical field of electronic design, in particular to a data transmission system based on multiple FPGA chips.
Background
FPGA prototype verification is a mainstream and mature chip verification method of the current prototype verification, whether the chip and system performance under the real software application condition meet the requirements of actual application scenes is simulated, and the FPGA has the characteristic of reconfigurable internal current, so that the logic design of the chip can be almost completely mapped.
Because ASIC designs are increasingly complex, for large designs, one FPGA often cannot accommodate, requiring multiple FPGAs to interconnect to verify the entire design, and therefore requiring partitioning of the large design. The partition can introduce new problems, and the biggest problem is that the partition can cause the demand on I/O ports to be increased rapidly, although the FPGA is reserved with a certain number of I/O ports, the number of interconnection signals in practice often exceeds the reserved I/O number, in order to solve the port problem, a time division multiplexing (Time Division Multiplex, TDM) technology is needed, namely, a plurality of parallel signals in the FPGA are converted into high-speed serial signals to be transmitted to another FPGA, and the signals are received by the other FPGA and then demultiplexed.
Because the number of the interconnected ports between the FPGAs is a preset fixed number, if the number of the ports between the two interconnected FPGAs is occupied or no connection exists, the corresponding signals need to be forwarded through the third FPGA as an intermediate node, and because the forwarding node needs to demultiplex the signals and re-multiplex the signals before the data are forwarded, larger delay is introduced, and therefore, the forwarding node introduces additional delay due to the demultiplexing and re-multiplexing, so that the overall performance is reduced.
Disclosure of Invention
In order to solve the technical problems, the invention aims to provide a data transmission system based on a plurality of FPGA chips, and the adopted technical scheme is as follows:
a data transmission system based on multiple FPGA chips comprises N interconnected FPGA chips { F 1 ,F 2 ,…,F N -wherein N is ≡3;
ith FPGA chip F i Including M reserved I/O portsAnd T time division multiplexing transmitting endWherein M is a positive integer, i is more than or equal to 1 and less than or equal to N, and T is more than or equal to 1 and less than or equal to M; t th sender->Transmit port of (c) and F i In (m) th reserved I/O port +.>Connecting, wherein the value range of T is 1 to T, and the value range of M is 1 to M;
jth FPGA chip F j Comprising Q reserved I/O portsAnd D time-division multiplexed receivers-> Q is a positive integer, j is more than or equal to 1 and less than or equal to N, i is not equal to j, and D is more than or equal to 1 and less than or equal to Q; f (F) j D-th receiver of (a)>Is provided with a receiving portAnd->Respectively connecting, wherein the value range of D is 1 to D, the value ranges of p and Q are 1 to Q, and p is not equal to Q;
kth FPGA chip F k Comprising G reserved I/O portsAnd W time division multiplexing transmitting terminals-> Wherein G is a positive integer, k is not less than 1 and not more than N, i is not more than k, and W is not less than 1 and not more than G; />And->Connecting, wherein the value range of G is 1 to G, and the value range of W is 1 to W;
wherein, inAnd->Connect and->And->When connected, the->Will F i Multiplexing several parallel signals into high-speed serial signal and transmitting to F j ，F j Pass the high-speed serial signals through +.>Send to->Demultiplexing, and by->Is sent toAnd (5) demultiplexing.
The invention has the following beneficial effects:
the embodiment of the invention provides a data transmission system based on multiple FPGA chips, which comprises N interconnected FPGA chips, wherein each FPGA chip comprises a plurality of reserved I/O ports, at least one time division multiplexing transmitting end and at least one receiving end, and the FPGA chip F i The transmitting end of the medium time division multiplexing is connected with F through I/O port j Receiving end connection of middle time division multiplexing and F j Receiving end of medium time division multiplexing through F j I/O port connection F of (1) k A receiving end of the medium time division multiplexing; at F i Through F j Forwarding signals to F k When the high-speed serial signal enters F through I/O port j After that and before the input receiving end, is divided into two paths, one path is input into F j Receiving end of middle time division multiplexing, another path directly transmits to F k The scheme disclosed by the invention not only reduces the use of cable, but also has very small introduced time delay due to the transparent transmission of high-speed serial signals, thereby improving the overall performance of the system and solving the problem of reduced overall performance due to additional time delay introduced again by demultiplexing and multiplexing at present. Furthermore, as the connection mode of the I/O port and the time division multiplexing receiving end is changed, the embodiment of the invention not only can transmit the signals which are directly interconnected, but also can be used as the intermediate forwarding node to directly forward the signals, so that the FPGA which is not directly connected can be communicated, the I/O port resource can be flexibly allocated according to the requirement, and the topology structure of the interconnection of the FPGA is greatly increased.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions and advantages of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a data transmission system based on multiple FPGA chips according to an embodiment of the present invention.
Detailed Description
In order to further describe the technical means and effects adopted by the present invention to achieve the preset purpose, the following detailed description refers to the specific implementation, structure, features and effects of a data transmission system based on multiple FPGA chips according to the present invention with reference to the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "another embodiment" means that the embodiments are not necessarily the same. Furthermore, the particular features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
The following specifically describes a specific scheme of the data transmission system based on the multi-FPGA chip provided by the present invention with reference to the accompanying drawings.
The invention provides a data transmission system based on multiple FPGA chips, which comprises N interconnected FPGA chips { F 1 ,F 2 ,…,F N -wherein N is ≡3; ith FPGA chip F i Comprising M reserved I/O ports Wherein i is more than or equal to 1 and less than or equal to N, and M is a positive integer. The value of N depends on the scale of the ASCI design, and the larger the scale is, the more FPGAs are required to accommodate the whole design. Because the reserved ports of the FPGA are limited, and two FPGA chips F are directly connected through the I/O ports i And F is equal to k The number of actual interconnect signals between far exceeds the reserved I/O ports. For example, M has a value of 1000, but in practice there are 3000 interconnect signals, and the reserved I/O ports are fully occupied by part of the interconnect signals, and the remaining interconnect signals are only availableThe signal is transmitted by using other FPGA chips as intermediate nodes for forwarding; or at F i Need to face F k And the signals are transmitted, and no I/O port is interconnected between the two FPGAs, so that other FPGAs are required to serve as intermediate nodes to forward the signals, and the signal transmission is realized. Thus, at least three interconnected FPGA chips are required. The number of the reserved I/O ports of the N interconnected FPGA chips can be the same or different.
F i Transmitting terminal comprising T time division multiplexingWherein T is more than or equal to 1 and less than or equal to M; t th sender->Transmit port of (c) and F i In (m) th reserved I/O port +.>And (3) connecting, wherein the value range of T is 1 to T, and the value range of M is 1 to M. Wherein the time division multiplexing module comprises a transmitting end and a receiving end, the time division multiplexing transmitting end is used for converting a plurality of input parallel signals into high-speed serial signals to be output, multiplexing F i An I/O port is reserved in the same one; after receiving the high-speed serial signal, the receiving end demultiplexes the high-speed serial signal to obtain a corresponding signal. Therefore, one reserved I/O port is connected to at most one time-division multiplexed transmitting end, and thus the number of time-division multiplexed transmitting ends is at most equal to the number of reserved I/O ports. In F i Comprises at least one time division multiplexing transmitting end and at least one time division multiplexing receiving end.
Jth FPGA chip F j Comprising Q reserved I/O portsAnd D time-division multiplexed receivers-> Q is a positive integer, j is more than or equal to 1 and less than or equal to N, i is not equal to j, and D is more than or equal to 1 and less than or equal to Q; f (F) j D-th receiver of (a)>Receiving port and F of (2) j P-th reserved I/O port +.>And the q-th reserved I/O port P j q Are respectively connected, wherein the value range of D is 1 to D, the value ranges of p and Q are 1 to Q, and p is not equal to Q. The receiving end of the time division multiplexing is used for demultiplexing the received high-speed serial signal to obtain signals in corresponding time slots. Specifically, since the receiving ends of the time division multiplexing are respectively connected with F j The high-speed serial signals enter the receiving ends of the two FPGA through the two reserved ports respectively for time division multiplexing.
Kth FPGA chip F k Comprising G reserved I/O portsAnd W time division multiplexing transmitting terminals-> Wherein G is a positive integer, k is not less than 1 and not more than N, i is not more than k, and W is not less than 1 and not more than G; />And->Connecting, wherein the value range of G is 1 to G, and the value range of W is 1 to W; wherein P is k g For the kth FPGA chip F k Reserved I/O port of g < th >, <>Is F k W time division multiplexed receiving end.
Wherein, inAnd->Connect and->And->When connected, the->Will F i Multiplexing several parallel signals into high-speed serial signal and transmitting to F j ，F j Pass the high-speed serial signals through +.>Send to->Demultiplexing, and by->Is sent toAnd (5) demultiplexing. F is also described as j Receiving terminal of medium time division multiplexing>After demultiplexing the signal, only the signals belonging to F are processed j Signals other than F j The signals of (2) are not processed; similarly, F k Receiving end->After demultiplexing the signal, only processing the signals belonging to F k Signals other than F k Is not processed. By associating F with a forwarding node k The connected I/O ports are directly connected toThe receiving end of the forwarding node is simplified, the signal forwarding flow is simplified, and the delay is reduced in the forwarding flow, because in the conventional forwarding flow, the forwarding node needs to be demultiplexed by the receiving end after receiving the corresponding high-speed serial signal, and then the signals which do not belong to the forwarding node after the demultiplexing are input into the transmitting end to be multiplexed and forwarded again, wherein a great amount of time is consumed for the demultiplexing and the re-multiplexing, and if the signal quantity is large, the delay introduced by forwarding can be serious. The method disclosed by the invention can not only finish the process of F i To F j The signal transmission can be further completed with the lowest delay, so the signal transmission is the lowest delay because the method disclosed by the invention only has the transmission delay on the connection line of the chip I/O port in the transmission process, and no delay exists in signal demultiplexing and re-multiplexing. And because the connection mode of the I/O port and the time division multiplexing receiving end is changed, the direct interconnection signal can be transmitted, and the direct interconnection signal can be directly forwarded by the intermediate forwarding node, so that communication is carried out between the FPGA without direct connection, the I/O port resource can be flexibly allocated according to the requirement, and the topology structure of the interconnection of the FPGA is greatly increased. Furthermore, as the connection between the I/O ports of the FPGA belongs to on-chip interconnection, compared with the existing interconnection mode adopting cable lines, the space layout wiring is more regular and concise.
In the embodiment of the invention, for synchronous time division multiplexing, the time slots in the channels are distributed in advance according to the preset rule, so that the receiving endAnd->Demultiplexing signals in corresponding time slots according to the preset time slots in a targeted manner; for asynchronous time division multiplexing, the signals in the time slots are marked with corresponding tags in advance, the receiving end +.>And->Demultiplexing signals belonging to the current node according to the labels respectively; in other embodiments, multiplexing and demultiplexing in other time division multiplexing manners may also be employed.
Preferably, inAnd->When connected, the head is attached>And->Not interconnected, and->And->Not interconnected, g+.x and q+.y, wherein +.>Is F k Reserved I/O port of x < th >, < >>Is F j In y-th reservation I-And an O port.
Preferably, the saidAnd->When connected, the head is attached>And->Not interconnected, and->And->Not interconnected, m not equal to v and c not equal to p, wherein,is F j In c reserved I/O port, < ->Is F i The v-th reserved I/O port.
Preferably, m=q and q=g.
For further clarity of the invention, the invention is described below by taking a small number of I/O ports and time division multiplexing modules as examples.
Referring to fig. 1, taking three interconnected FPGA chips and one path of time-division multiplexing transmitting end and receiving end as an example, for the three interconnected FPGA chips { F 1 ,F 2 ,F 3 10I/O ports are reserved for each FPGA chip, F 1 And F 2 、F 2 And F 3 、F 1 And F 3 Are respectively connected with each other through 5I/O ports, and are respectively connected with each other in F 1 And F 2 When the I/O ports in between are occupied, F is needed to be used 1 Transmitted byThe signal passing through intermediate node F 3 Forward to F 2 . At F 1 Comprising a time division multiplexed transmitting terminalAnd (3) andconnected I/O port->At F 2 Comprising a time division multiplexed receiving end->And->Connected I/O port->At F 3 Comprising a time division multiplexed receiving end->And (4) respectively and->Connected I/O port->And->For F 3 For the rest of the other reserved I/O ports, +.>And->Is the sum of reserved I/OTotal number of ports>Is F 1 And F 3 One of the I/O ports interconnected between,/-and>is F 3 And F 2 One of the I/O ports interconnected therebetween. At->And->Connect and->And->When connecting, F 1 Passing a plurality of parallel signals { A, B, C, D }, through->Is converted into a high-speed serial signal X, wherein the time slot of { A, B } is preassigned to F 3 The time slot in which the, { C, D } is used is pre-assigned to F 2 Use; passing the high-speed serial signal X through +.>Is transmitted to->At F 3 The high-speed serial signal X is divided into two paths, one path passes through the high-speed serial signal X +.>The receiving port of (1) inputs the receiving end to be demultiplexed to obtain { A, B }, and the other path passes the high-speed serial signal X +.>Output to F 2 A kind of electronic deviceVia->Input->The receiving port input receiving end of (C) is demultiplexed to obtain { C, D }. Since the high-speed serial signal is input directly via the physical connection>Does not pass through forwarding node F 3 The complex process of demultiplexing and then multiplexing can greatly reduce the delay of the forwarded signal.
In summary, the embodiment of the invention provides a data transmission system based on multiple FPGA chips, which includes N interconnected FPGA chips, each FPGA includes a plurality of reserved I/O ports, at least one time-division multiplexing transmitting end and receiving end, and FPGA chip F i The transmitting end of the medium time division multiplexing is connected with F through the corresponding I/O port j Receiving end connection of middle time division multiplexing and F j The receiving end of the medium time division multiplexing is connected with F through the corresponding I/O port k A receiving end of the medium time division multiplexing; at F i Through F j Forwarding signals to F k When the high-speed serial signal enters F through I/O port j Before the input of the receiving end of the time division multiplexing, the signal is divided into two paths, one path is input into F j The other path of the receiving end of the middle time division multiplexing is directly forwarded to F without demultiplexing k The scheme disclosed by the invention can flexibly allocate the I/O port resources among the FPGA chips, greatly increase the topological structure possibility of FPGA interconnection and reduce the use of physical connection lines; because of the transparent transmission of the high-speed serial signal, the introduced delay is very small, thereby improving the integrity of the systemCan be used.
It should be noted that: the sequence of the embodiments of the present invention is only for description, and does not represent the advantages and disadvantages of the embodiments. And the foregoing description has been directed to specific embodiments of this specification. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (8)
1. A data transmission system based on multiple FPGA chips, wherein the system comprises N interconnected FPGA chips { F 1 ,F 2 ,…,F N -wherein N is ≡3;
ith FPGA chip F i Including M reserved I/O portsAnd T time division multiplexing transmitting endWherein M is a positive integer, i is more than or equal to 1 and less than or equal to N, and T is more than or equal to 1 and less than or equal to M; t th sender->Transmit port of (c) and F i In (m) th reserved I/O port +.>Connecting, wherein the value range of T is 1 to T, and the value range of M is 1 to M;
jth FPGA chip F j Comprising Q reserved I/O portsAnd D time-division multiplexed receivers-> Q is a positive integer, j is more than or equal to 1 and less than or equal to N, i is not equal to j, and D is more than or equal to 1 and less than or equal to Q; f (F) j D-th receiver of (a)>Receiving port and->And->Respectively connecting, wherein the value range of D is 1 to D, the value ranges of p and Q are 1 to Q, and p is not equal to Q;
kth FPGA chip F k Comprising G reserved I/O portsAnd W time division multiplexing transmitting terminals-> Wherein G is a positive integer, k is not less than 1 and not more than N, and i is not equal to k,1≤W≤G；/>and->Connecting, wherein the value range of G is 1 to G, and the value range of W is 1 to W;
wherein, inAnd->Connect and->And->When connected, the->Will F i Multiplexing several parallel signals into high-speed serial signal and transmitting to F j ，F j Pass the high-speed serial signals through +.>Send to->Demultiplexing, and by->Send to->And (5) demultiplexing.
2. The data transmission system based on multiple FPGA chips as defined in claim 1, wherein said at least one ofAnd->When connected, the head is attached>And->Not interconnected, and->And->Not interconnected, g+.x and q+.y, wherein +.>Is F k Reserved I/O port of x < th >, < >>Is F j I/O ports are reserved for the y-th of (b).
3. The multi-FPGA chip-based data transmission system of claim 1, wherein theAnd (3) withWhen connected, the head is attached>And->Not interconnected, and->And->Not interconnected, m+.v and c+.p, wherein +.>Is F j The c-th reserved I/O port in (c),is F i The v-th reserved I/O port.
4. The data transmission system based on multiple FPGA chips as defined in claim 1, wherein said time division multiplexing is synchronous time division multiplexing, and the receiving endAnd->Signals in corresponding time slots are demultiplexed according to the pre-designated time slots.
5. The data transmission system based on multiple FPGA chips as defined in claim 1, wherein said time division multiplexing is asynchronous time division multiplexing, and the receiving endAnd->And demultiplexing signals belonging to the current node according to the labels respectively.
6. The data transmission system based on multiple FPGA chips as defined in claim 1, wherein said F i And F is equal to k Interconnected by I/O ports.
7. The data transmission system based on multiple FPGA chips as defined in claim 1, wherein said F i And F is equal to k There is no I/O port interconnection between.
8. The multi-FPGA chip based data transmission system of claim 1, wherein M = Q and Q = G.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118245434A (en) * | 2024-04-16 | 2024-06-25 | 上海合见工业软件集团有限公司 | Signal TDM distribution method, electronic device and medium based on FPGA |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5847578A (en) * | 1994-11-01 | 1998-12-08 | Virtual Machine Works | Programmable multiplexing input/output port |
| US7268581B1 (en) * | 2005-04-21 | 2007-09-11 | Xilinx, Inc. | FPGA with time-multiplexed interconnect |
| WO2009022817A1 (en) * | 2007-08-10 | 2009-02-19 | Electronics And Telecommunications Research Institute | Time division multiplexing communication system with parallel structure and method for the same |
| CN101833502A (en) * | 2010-04-15 | 2010-09-15 | 上海华为技术有限公司 | ASIC Chip Verification Method and Programmable Gate Array |
| US20150135147A1 (en) * | 2013-11-08 | 2015-05-14 | Synopsys, Inc. | Generating a Circuit Description for a Multi-die Field-programmable Gate Array |
| CN105429764A (en) * | 2015-11-05 | 2016-03-23 | 山东超越数控电子有限公司 | FPGA chip, and remote transmission system and method |
| CN111061662A (en) * | 2019-12-06 | 2020-04-24 | 思尔芯(上海)信息科技有限公司 | Compiling system and method for expanding FPGA (field programmable Gate array) interconnected IO (input/output) based on connector |
| CN112347721A (en) * | 2020-10-29 | 2021-02-09 | 北京长焜科技有限公司 | System for realizing data processing acceleration based on FPGA and acceleration method thereof |
| CN113326227A (en) * | 2021-08-03 | 2021-08-31 | 上海国微思尔芯技术股份有限公司 | Link multiplexing method, system and prototype verification method |
| CN113434456A (en) * | 2021-06-22 | 2021-09-24 | 上海新致华桑电子有限公司 | Time-sharing multiplexing data transmission device, method and system |
-
2022
- 2022-08-17 CN CN202210985665.7A patent/CN117632836B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5847578A (en) * | 1994-11-01 | 1998-12-08 | Virtual Machine Works | Programmable multiplexing input/output port |
| US7268581B1 (en) * | 2005-04-21 | 2007-09-11 | Xilinx, Inc. | FPGA with time-multiplexed interconnect |
| WO2009022817A1 (en) * | 2007-08-10 | 2009-02-19 | Electronics And Telecommunications Research Institute | Time division multiplexing communication system with parallel structure and method for the same |
| CN101833502A (en) * | 2010-04-15 | 2010-09-15 | 上海华为技术有限公司 | ASIC Chip Verification Method and Programmable Gate Array |
| US20150135147A1 (en) * | 2013-11-08 | 2015-05-14 | Synopsys, Inc. | Generating a Circuit Description for a Multi-die Field-programmable Gate Array |
| CN105429764A (en) * | 2015-11-05 | 2016-03-23 | 山东超越数控电子有限公司 | FPGA chip, and remote transmission system and method |
| CN111061662A (en) * | 2019-12-06 | 2020-04-24 | 思尔芯(上海)信息科技有限公司 | Compiling system and method for expanding FPGA (field programmable Gate array) interconnected IO (input/output) based on connector |
| CN112347721A (en) * | 2020-10-29 | 2021-02-09 | 北京长焜科技有限公司 | System for realizing data processing acceleration based on FPGA and acceleration method thereof |
| CN113434456A (en) * | 2021-06-22 | 2021-09-24 | 上海新致华桑电子有限公司 | Time-sharing multiplexing data transmission device, method and system |
| CN113326227A (en) * | 2021-08-03 | 2021-08-31 | 上海国微思尔芯技术股份有限公司 | Link multiplexing method, system and prototype verification method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118245434A (en) * | 2024-04-16 | 2024-06-25 | 上海合见工业软件集团有限公司 | Signal TDM distribution method, electronic device and medium based on FPGA |
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