CN117639742A - Overshoot prevention method and circuit for power switch circuit - Google Patents

Abstract

The invention discloses a power switch circuit overshoot prevention method and a circuit, wherein the power switch circuit comprises a transistor and a switch connected with a grid electrode of the transistor, and the method comprises the following steps: the switch is controlled to be alternately closed and opened through a pulse signal; the closing duration and the opening duration of the switch are controlled by adjusting the pulse width of the pulse signal, so that the drain voltage of the transistor is controlled to be changed to a target value. The invention realizes slow power-down or slow power-up through the pulse signal, and avoids overshoot or ringing of the drain end of the transistor, which causes the risk of overvoltage of the power switch circuit or a load circuit connected with the power switch circuit, and causes breakdown of the transistor or damage of the load circuit. The invention generates the pulse signal through the PWM control module, realizes simple power-on and power-off control, does not need a large-area analog circuit, has higher design flexibility, reduces the design cost, design complexity and manufacturing cost of the circuit, and is suitable for large-scale SOC chips.

Description

Overshoot prevention method and circuit for power switch circuit

Technical Field

The present invention relates to the field of switch control technologies, and in particular, to a method and a circuit for preventing overshoot of a power switch circuit.

Background

When the power switch circuit is turned on or turned off, overshoot or ringing may occur at the switch end due to abrupt change of impedance and influence of capacitive inductive load, which results in overvoltage risk of the switch or the load circuit of the switch, and breakdown of the switch or damage of the load circuit. If the switch is turned off directly, the abrupt change of resistance may cause overshoot at the switch end due to the influence of the load capacitance and inductance, as shown in fig. 1, resulting in damage to the device caused by overvoltage of the relevant circuit. Therefore, it is necessary to reduce or avoid overshoot when the power switch is turned on or off.

Normally, the on or off overshoot of the power switch circuit can be controlled by controlling the gate terminal of the power tube, and a relatively complex slow power-down control and a relatively large-area analog circuit are required. Taking a low-side switch as an example, as shown in fig. 2 (1), the conventional low-side switch circuit is turned off, and the switch is controlled to be turned off directly by the conventional power-down control module, so that the voltage of a switch end of the power switch is suddenly changed, and overshoot and oscillation are generated. The turn-off mode of the traditional low-side switch circuit for inhibiting turn-off overshoot is shown in fig. 2 (2), the switch is controlled to be turned off directly by the traditional power-down control module, the grid capacitor of the power tube is discharged step by small current, the control and the power-down of the grid voltage of the power tube are realized, the traditional power-down control module adopts an analog circuit with a larger area, and the manufacturing cost and the design complexity are further increased by the arrangement of the small current.

In a large-scale SOC chip, the implementation cost of the digital circuit is lower than that of the analog circuit, and there is a high design flexibility. Digital implementation of the on-off overshoot avoidance circuit is further advantageous when the SOC chip is integrated with a power switching circuit.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide an overshoot prevention method and an overshoot prevention circuit for a power switch circuit, which can realize that the voltage of a switch end changes slowly when the power switch circuit is turned on or turned off through a pulse signal, so that overshoot is avoided.

To achieve the above object, an embodiment of the present invention provides a power switching circuit overshoot prevention method, the power switching circuit including a transistor and a switch connected to a gate of the transistor, the method including:

the switch is controlled to be alternately closed and opened through a pulse signal;

the closing duration and the opening duration of the switch are controlled by adjusting the pulse width of the pulse signal, so that the drain voltage of the transistor is controlled to be changed to a target value.

In one or more embodiments of the present invention, a pulse signal is generated by a PWM control module to control a switching action;

the switch is controlled to be alternately closed and opened by a pulse signal so as to control the voltage of the drain terminal of the transistor to rise or fall;

after the drain terminal voltage of the transistor rises or falls to a target value, the pulse signal maintains a high level or a low level.

In one or more embodiments of the invention, the method comprises: the accumulated closing duration of the switch is controlled to be larger than the accumulated opening duration so as to enable the drain voltage to be changed to the target value.

In one or more embodiments of the invention, the method comprises: the pulse signal is high-level control switch closed, and the pulse signal is low-level control switch open.

In one or more embodiments of the invention, the method comprises: the pulse signal is a low-level control switch which is closed, and the pulse signal is a high-level control switch which is opened.

In one or more embodiments of the present invention, the high level pulse width is greater than the low level pulse width in all pulse periods or the high level pulse width is greater than the low level pulse width in part of pulse periods before the drain voltage is changed to the target value.

In one or more embodiments of the present invention, the low level pulse width is greater than the high level pulse width in all pulse periods or the low level pulse width is greater than the high level pulse width in part of pulse periods before the drain voltage is changed to the target value.

In one or more embodiments of the present invention, the high level pulse width of the pulse signal is the same or gradually increases, and the low level pulse width of the pulse signal is gradually reduced or the same.

In one or more embodiments of the present invention, the pulse width of the low level of the pulse signal is the same or gradually increases, and the pulse width of the high level of the pulse signal is the same or gradually decreases.

The invention provides a power switch circuit for realizing the overshoot prevention method of the power switch circuit, which is characterized in that the circuit comprises a transistor, a switch and a PWM control module,

the source electrode of the transistor is connected with ground potential or power supply voltage, and the drain electrode of the transistor is connected with a load;

one end of the switch is connected with the grid electrode of the transistor, one end of the switch is connected with the ground potential or the power supply voltage, and the switch is used for controlling the transistor to be turned on or turned off;

the PWM control module is used for generating pulse signals to control the switching action.

Compared with the prior art, according to the overshoot prevention method and the overshoot prevention circuit for the power switch circuit, the switch is controlled to be repeatedly and alternately turned on and turned off through the pulse signal, so that the drain terminal voltage of the transistor is controlled to be repeatedly increased and decreased and then progressively changed to the target value, slow power down or slow power up is realized, when the power switch circuit is turned on or off, the overshoot or ringing of the switch end, namely the drain end, of the transistor is avoided due to the sudden change of impedance and the influence of capacitive inductance load, and the overvoltage risk of the power switch circuit or a load circuit connected with the power switch circuit is caused, so that the transistor breaks down or the load circuit is damaged.

The invention constructs the PWM control module through the digital circuit to generate the pulse signal, realizes simple power-on and power-off control, does not need a large-area analog circuit, has higher design flexibility, reduces the design cost, design complexity and manufacturing cost of the circuit, and is suitable for a large-scale SOC chip. The on-resistance of the power switch circuit is finely and slowly controlled through the pulse signal, and the grid end capacitance of the power switch circuit can be further reduced, so that the design and manufacturing cost is saved.

Drawings

FIG. 1 is a diagram of a switch-side voltage variation for a conventional low-side switching circuit in the prior art with direct power down;

FIG. 2 is a schematic diagram of a conventional low-side switching circuit of the prior art;

fig. 3 is a schematic circuit configuration diagram for implementing the overshoot prevention method of the power switch circuit according to embodiment 1 of the present invention;

fig. 4 is a control flow chart of a PWM control module of the power switching circuit overshoot prevention method according to embodiment 1 of the present invention;

fig. 5 is a slow-down electrical waveform diagram of a power switch circuit overshoot prevention method according to embodiment 1 of the present invention;

fig. 6 is a slow-down electrical waveform diagram of a power switch circuit overshoot prevention method according to embodiment 2 of the present invention;

fig. 7 is a schematic circuit configuration diagram for realizing the overshoot prevention method of the power switch circuit according to embodiment 3 of the invention;

fig. 8 is a slow-rise electrical waveform diagram of a power switch circuit overshoot prevention method according to embodiment 3 of the present invention;

fig. 9 is a slow-rise electrical waveform diagram of a power switch circuit overshoot prevention method according to embodiment 4 of the present invention;

fig. 10 is a schematic circuit configuration diagram for realizing the overshoot prevention method of the power switch circuit according to embodiment 5 of the invention;

fig. 11 is a slow-down electrical waveform diagram of a power switch circuit overshoot prevention method according to embodiment 5 of the present invention;

fig. 12 is a slow-down electrical waveform diagram of a power switch circuit overshoot prevention method according to embodiment 6 of the present invention;

fig. 13 is a schematic circuit configuration diagram for realizing the overshoot prevention method of the power switch circuit according to embodiment 7 of the invention;

fig. 14 is a slow-rise electrical waveform diagram of a power switch circuit overshoot prevention method according to embodiment 7 of the present invention;

fig. 15 is a slow-rise electrical waveform diagram of a power switch circuit overshoot prevention method according to embodiment 8 of the present invention.

Detailed Description

The following detailed description of embodiments of the invention is, therefore, to be taken in conjunction with the accompanying drawings, and it is to be understood that the scope of the invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.

The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.

Example 1

As shown in fig. 3, the present invention provides a power switching circuit for implementing the overshoot prevention method of the power switching circuit provided by the present invention, where the power switching circuit includes a transistor M1, a switch S1 connected to a gate M1 of the transistor, and a PWM control module. Where PWM, pulse width modulation is pulse width modulation. The power-down control module of the conventional control switch shown in fig. 2 adopts a large-area analog circuit. Compared with an analog circuit which requires more manufacturing cost and design complexity, the PWM control module provided by the invention adopts a digital circuit to generate a pulse signal for controlling a switch, so that the circuit area is reduced, and meanwhile, the design difficulty is reduced.

In one embodiment, the drain of the transistor M1 is connected to the load circuit, and the source of the transistor M1 is connected to the ground potential VSS, i.e., the power switch circuit is a low-side switch circuit. One end of the switch S1 is connected with the grid electrode of the transistor M1, one end of the switch S1 is connected with the ground potential VSS, the switch S1 is used for controlling the transistor M1 to be turned on or turned off, and the PWM control module is used for generating a pulse signal to control the switch S1 to act. Further, the power switch circuit includes a capacitor C, a first end of the capacitor C is connected to the gate of the transistor M1, and a second end of the capacitor C is connected to the ground potential VSS. It is understood that the capacitor C may be a parasitic capacitor at the gate terminal of the transistor or a gate terminal capacitor provided.

Further, the transistor M1 of the power switch circuit is an N-channel MOS transistor, and the switch S1 is a pull-down switch.

The embodiment provides a power switch circuit overshoot prevention method, which is used for realizing slow power down of a power switch circuit, and comprises the following steps: the pull-down switch S1 is controlled to be alternately closed and opened through a pulse signal; the pulse width of the pulse signal is adjusted to control the closing duration and the opening duration of the pull-down switch S1, so as to control the drain voltage of the N-channel MOS tube M1 to change to a target value.

It can be understood that, for a power switch circuit using an N-channel MOS transistor, the power-down process of the power switch circuit refers to the change of the drain voltage of the N-channel MOS transistor from 0 to high potential, and the power-up process of the power switch circuit refers to the change of the drain voltage of the N-channel MOS transistor from high potential to 0.

Further, a pulse signal is generated through the PWM control module to control the pull-down switch S1 to act, specifically, when the pulse signal is at a high level, the pull-down switch S1 is closed, and the N-channel MOS tube M1 starts to be powered down; when the pulse signal is at a low level, the pull-down switch S1 is turned off, and the N-channel MOS transistor M1 is suspended from power down.

In an embodiment, in the power-down process of the power switch circuit, the accumulated high level pulse width of the pulse signal is greater than the accumulated low level pulse width, that is, the accumulated closing duration of the pull-down switch S1 is greater than the accumulated opening duration, that is, the accumulated power-down time of the N-channel MOS transistor M1 is greater than the accumulated power-up time, so that the drain voltage of the N-channel MOS transistor M1 is changed to the target value.

As shown in fig. 4, in one embodiment, the control flow of the PWM control module for generating the pulse signal includes:

in step 401, the switch initial open duration NP is set to N and the switch initial close duration NM is set to 1.

Step 402, time nf=0 for the on-off on-period, and time no=0 for the on-off on-period.

In step 403, the pulse signal output by the pwm control module is at a low level to control the switch to be turned off.

Step 404, controlling nf to gradually increase by the clock signal until nf is greater than the initial turn-off duration NP of the switch, and at this time, controlling the turn-off duration NP of the switch to NP-1, and resetting the turn-off period timing. At this time, the pulse signal output by the PWM control module is at a high level to control the switch to be turned on.

Step 405, the clock signal is used to control no to gradually increase until no is greater than the initial closing duration NM of the switch, at this time, the closing duration NM of the switch is controlled to be nm+1, it is determined whether the closing duration NM of the switch is greater than the initial opening duration N of the switch, if yes, the control is ended, the PWM control module outputs a continuous high level signal, otherwise, the closing period timing is cleared, and step 403 is circularly executed.

In this embodiment, the PWM control module generates a pulse signal with a high-level pulse width gradually increasing and a low-level pulse width gradually decreasing, and in other embodiments, the PWM control module may generate a pulse signal with a high-level pulse width gradually increasing and a low-level pulse width identical to each other, or a pulse signal with a high-level pulse width identical to each other and a low-level pulse width gradually decreasing. The power switch circuit composed of the N channel MOS tube M1 and the pull-down switch S1 realizes slow power down.

As shown in fig. 5, the pull-down switch S1 is controlled to be turned on and off alternately by a pulse signal to control the drain voltage of the N-channel MOS transistor M1 to rise progressively.

In the first pulse signal period, the pulse signal is high-level pull-down switch S1 is closed, the drain end voltage of the N-channel MOS tube M1 is increased from the initial voltage to the first voltage, the pulse signal is low-level pull-down switch S1 is opened, and the drain end voltage of the N-channel MOS tube M1 is reduced from the first voltage to the second voltage, wherein the first voltage is larger than the initial voltage. Because the high-level pulse width of the pulse signal is larger than the low-level pulse width of the pulse signal, the second voltage is smaller than the first voltage and larger than the initial voltage, after the period of the first pulse signal, the drain end voltage of the N-channel MOS tube M1 is raised and lowered, and then the progressive rise is realized relative to the initial voltage.

In the next pulse signal period, the drain end voltage of the N-channel MOS tube M1 is changed from the second voltage to a third voltage after rising and falling, wherein the third voltage is larger than the first voltage; after a plurality of pulse signal periods, the drain voltage of the N-channel MOS transistor M1 rises to the target value, the pulse signal maintains a high level, and the pull-down switch S1 remains closed.

In one embodiment, during the power-down process of the power switch circuit, the high-level pulse width is greater than the low-level pulse width in all pulse periods. In other embodiments, the high pulse width is greater than the low pulse width during a portion of the pulse period.

By the overshoot prevention method for the power switch circuit, the switch end voltage of the power switch circuit, namely the drain end voltage of the transistor, can change to the designated potential at a gentle speed, and overshoot is avoided. The pulse signal output by the PWM control module controls the pull-down switch S1, so that the average on-resistance of the power switch circuit is changed, the on-resistance is reduced slowly, and finally, strong pull-down is realized, and the slow power-down of the power switch circuit is realized. Meanwhile, the on-resistance is finely and slowly controlled through the pulse signal, the grid end capacitance of the power switch can be further reduced, and the design and manufacturing cost is saved.

Example 2

As shown in fig. 6, the difference between the present embodiment and embodiment 1 is that, for the power switch circuit shown in fig. 3, when the pulse signal is at low level, the pull-down switch S1 is closed to control the N-channel MOS transistor M1 to start powering down; when the pulse signal is at a high level, the pull-down switch S1 is turned off to control the N-channel MOS transistor M1 to stop powering down.

It can be understood that, in the power-down process of the power switch circuit, the accumulated closing duration of the pull-down switch S1 is controlled to be greater than the accumulated opening duration, that is, the accumulated high-level pulse width of the pulse signal is smaller than the accumulated low-level pulse width, that is, the accumulated power-down time in the power-down process of the N-channel MOS tube M1 is greater than the power-up time, so that the drain voltage of the N-channel MOS tube M1 is changed to the target value.

In an embodiment, in the power-down process of the power switch circuit using the N-channel MOS transistor M1, the low-level pulse width is greater than the high-level pulse width in all pulse periods, or the low-level pulse width is greater than the high-level pulse width in part of the pulse periods.

In a preferred but non-limiting embodiment of the present invention, as the pulse timing is changed, the low-level pulse width in a plurality of periods is kept the same, the high-level pulse width is gradually reduced, or the low-level pulse width is gradually increased, and the high-level pulse width is kept the same, or the low-level pulse width is gradually increased, and the high-level pulse width is gradually reduced, so that the power switch circuit formed by the N-channel MOS transistor M1 and the pull-down switch S1 realizes slow power down.

Example 3

As shown in fig. 7, the difference between this embodiment and embodiment 1 is that the switch S1 of the power switch circuit is a pull-up switch, the gate of the N-channel MOS transistor M1 is connected to the second end of the pull-up switch S1, and the first end of the pull-up switch S1 is connected to the power supply voltage VDD, i.e., the power switch circuit is a low-side switch circuit, and the pull-up switch S1 is used for controlling the power switch circuit to power up.

The embodiment provides a power switch circuit overshoot prevention method, which is used for realizing slow power-up of a power switch circuit, and comprises the following steps: the pull-up switch S1 is controlled to be alternately closed and opened through a pulse signal; the pulse width of the pulse signal is adjusted to control the closing duration and the opening duration of the pull-up switch S1, so as to control the drain voltage of the transistor M1 to be changed to the target value.

Further, the PWM control module generates a pulse signal to control the pull-up switch S1 to operate, specifically, when the pulse signal is at a high level, the pull-up switch S1 is closed, and when the pulse signal is at a low level, the pull-up switch S1 is opened. In an embodiment, in the power-up process of the N-channel MOS transistor M1, the accumulated closing duration of the pull-up switch S1 is controlled to be longer than the accumulated opening duration, i.e., the accumulated high-level pulse width of the pulse signal is longer than the accumulated low-level pulse width, i.e., the accumulated power-up time of the N-channel MOS transistor M1 in the power-up process is longer than the accumulated power-down time, so that the drain voltage of the N-channel MOS transistor M1 is changed to the target value.

As shown in fig. 8, the pull-up switch S1 is controlled to be turned on and off alternately by a pulse signal to control the drain voltage of the N-channel MOS transistor M1 to drop slowly.

In the first pulse signal period, the pull-up switch S1 is closed when the pulse signal is at a high level, the drain voltage of the N-channel MOS tube M1 is reduced from an initial voltage to a first voltage, the pull-up switch S1 is opened when the pulse signal is at a low level, and the drain voltage of the N-channel MOS tube M1 is increased from the first voltage to a second voltage, wherein the first voltage is smaller than the initial voltage. Because the high-level pulse width of the pulse signal is larger than the low-level pulse width of the pulse signal, the second voltage is larger than the first voltage and smaller than the initial voltage, and after the period of the first pulse signal, the drain end voltage of the N-channel MOS tube M1 is reduced and increased, and then the progressive reduction is realized relative to the initial voltage.

In the next pulse signal period, the drain end voltage of the N-channel MOS tube M1 is changed from the second voltage to a third voltage after falling and rising, wherein the third voltage is smaller than the first voltage; after the drain voltage of the N-channel MOS transistor M1 drops to the target value after a plurality of pulse signal periods, the pulse signal maintains a high level, and the pull-up switch S1 remains closed.

In a preferred but non-limiting embodiment of the present invention, as the pulse timing is changed, the high level pulse width in a plurality of periods is kept the same, the low level pulse width is gradually decreased, or the high level pulse width is gradually increased, the low level pulse width is kept the same, or the high level pulse width is gradually increased, the low level pulse width is gradually decreased, and the power switch circuit formed by the N-channel MOS transistor M1 and the pull-up switch S1 is powered on slowly in a short time.

In one embodiment, in the power-on process of the power switch circuit using the N-channel MOS transistor M1, the high-level pulse width is greater than the low-level pulse width in all pulse periods. In other alternative embodiments, the high level pulse width is greater than the low level pulse width during a portion of the pulse period.

Example 4

As shown in fig. 9, the difference between the present embodiment and embodiment 3 is that, for the power switch circuit shown in fig. 7, when the pulse signal is at a low level, the pull-up switch S1 is turned on to control the N-channel MOS transistor M1 to be turned on, so that the power switch circuit starts to be powered on; when the pulse signal is at a high level, the pull-up switch S1 is disconnected to control the N-channel MOS transistor M1 to be turned off, so that the power switch circuit is stopped from being electrified.

It can be understood that, in the power-up process of the power switch circuit adopting the N-channel MOS transistor M1, the accumulated closing duration of the pull-up switch S1 is controlled to be longer than the accumulated opening duration, i.e., the accumulated low-level pulse width of the pulse signal is longer than the accumulated high-level pulse width, i.e., the accumulated power-up time length in the power-up process of the N-channel MOS transistor M1 is longer than the accumulated power-down time length, so that the drain voltage of the N-channel MOS transistor M1 is changed to the target value.

In one embodiment, in the power-on process of the power switch circuit using the N-channel MOS transistor M1, the low-level pulse width is greater than the high-level pulse width in all pulse periods. In other alternative embodiments, the low level pulse width is greater than the high level pulse width during a portion of the pulse period.

In a preferred but non-limiting embodiment of the present invention, as the pulse timing is changed, the low level pulse width in a plurality of periods is kept the same, the high level pulse width is gradually decreased, or the low level pulse width is gradually increased, the high level pulse width is kept the same, or the low level pulse width is gradually increased, the high level pulse width is gradually decreased, and the power switch circuit composed of the N-channel MOS transistor M1 and the pull-up switch S1 is powered on slowly.

Example 5

As shown in fig. 10, the present embodiment is different from embodiment 1 in that the switch S1 of the power switch circuit is a pull-up switch, and the transistor M2 is a P-channel MOS transistor. The source electrode of the P channel MOS tube M2 is connected with the power supply voltage VDD, the grid electrode of the P channel MOS tube M2 is connected with the second end of the pull-up switch S1, the first end of the pull-up switch S1 is connected with the power supply voltage VDD, namely, the power switch circuit is a high-side switch circuit.

Further, the power switch circuit comprises a capacitor C, a first end of the capacitor C is connected with the grid electrode of the P-channel MOS tube M2, and a second end of the capacitor C is connected with the power supply voltage VDD. It is understood that the capacitor C may be a parasitic capacitor at the gate terminal of the transistor or a gate terminal capacitor provided.

The embodiment provides a power switch circuit overshoot prevention method, which is used for realizing slow power down of a power switch circuit, and comprises the following steps: the pull-up switch S1 is controlled to be alternately closed and opened through a pulse signal; the pulse width of the pulse signal is regulated to control the closing duration and the opening duration of the pull-up switch S1, so that the drain terminal voltage of the P-channel MOS tube M2 is controlled to be changed to a target value, and the slow power-down of the power switch circuit is realized. It can be understood that, for the power switch circuit adopting the P-channel MOS transistor, the power-on process of the power switch circuit refers to the change of the drain voltage of the P-channel MOS transistor from 0 to high potential, and the power-off process of the power switch circuit refers to the change of the drain voltage of the P-channel MOS transistor from high potential to 0.

Further, the PWM control module generates a pulse signal to control the pull-up switch S1 to operate, specifically, when the pulse signal is at a high level, the pull-up switch S1 is closed, and when the pulse signal is at a low level, the pull-up switch S1 is opened.

As shown in fig. 11, the pull-up switch S1 is controlled to be turned on and off alternately by a pulse signal to control the drain voltage of the P-channel MOS transistor M2 to rise slowly.

In the first pulse signal period, the pull-up switch S1 is closed when the pulse signal is at a high level, the drain terminal voltage of the P-channel MOS tube M2 is reduced from an initial voltage to a first voltage, the pull-up switch is opened when the pulse signal is at a low level, and the drain terminal voltage of the P-channel MOS tube M2 is increased from the first voltage to a second voltage, wherein the first voltage is smaller than the initial voltage. Because the high-level pulse width of the pulse signal is larger than the low-level pulse width of the pulse signal, the second voltage is larger than the first voltage and smaller than the initial voltage, after the period of the first pulse signal, the drain end voltage of the P-channel MOS tube M2 is reduced and increased, and then the progressive reduction is realized relative to the initial voltage.

In the next pulse signal period, the drain end voltage of the P-channel MOS tube M2 is changed from the second voltage to a third voltage after falling and rising, wherein the third voltage is smaller than the first voltage; after the drain voltage of the P-channel MOS transistor M2 drops to the target value after a plurality of pulse signal periods, the pulse signal maintains a high level, and the pull-up switch S1 remains closed.

In an embodiment, during the power-down process of the P-channel MOS transistor M2, the accumulated closing duration of the pull-up switch S1 is controlled to be longer than the accumulated opening duration, i.e., the accumulated high-level pulse width of the pulse signal is longer than the accumulated low-level pulse width, i.e., the accumulated power-down time of the P-channel MOS transistor M2 during the power-up process is longer than the accumulated power-up time, so that the drain voltage of the P-channel MOS transistor M2 is changed to the target value.

In one embodiment, in the power-down process of the power switch circuit using the P-channel MOS transistor M2, the high-level pulse width is greater than the low-level pulse width in all pulse periods. In other alternative embodiments, the high level pulse width is greater than the low level pulse width during a portion of the pulse period.

In a preferred but non-limiting embodiment of the present invention, as the pulse timing is changed, the high level pulse width in a plurality of periods is kept the same, the low level pulse width is gradually decreased, or the high level pulse width is gradually increased, the low level pulse width is kept the same, or the high level pulse width is gradually increased, the low level pulse width is gradually decreased, and the power switch circuit composed of the P-channel MOS transistor M2 and the pull-up switch S1 achieves slow power down.

Example 6

As shown in fig. 12, the difference between the present embodiment and embodiment 5 is that, for the power switch circuit shown in fig. 10, when the pulse signal is at a low level, the pull-up switch S1 is closed to control the P-channel MOS transistor M2 to start power-down; when the pulse signal is at a high level, the pull-up switch S1 is turned off to control the P-channel MOS transistor M2 to stop powering down. It can be understood that, in the power-down process of the P-channel MOS transistor M2, the accumulated low-level pulse width of the pulse signal is greater than the accumulated high-level pulse width, i.e., the accumulated power-down time length in the power-down process of the P-channel MOS transistor M2 is greater than the accumulated power-up time length.

In an embodiment, in the power-down process of the power switch circuit using the P-channel MOS transistor M2, the low-level pulse width is greater than the high-level pulse width in all pulse periods. In other alternative embodiments, during the power-down process of the P-channel MOS transistor M2, the low-level pulse width is greater than the high-level pulse width during a part of the pulse period.

In a preferred but non-limiting embodiment of the present invention, as the pulse timing is changed, the low-level pulse width in a plurality of periods is kept the same, the high-level pulse width is gradually reduced, or the low-level pulse width is gradually increased, and the high-level pulse width is kept the same, or the low-level pulse width is gradually increased, and the high-level pulse width is gradually reduced, so that the power switch circuit formed by the P-channel MOS transistor M2 and the pull-up switch S1 realizes slow power down.

Example 7

As shown in fig. 13, in this embodiment, the power switch circuit is a high-side switch circuit, and is different from embodiment 5 in that the switch S1 of the power switch circuit is a pull-down switch, the gate of the P-channel MOS transistor M2 is connected to the first end of the pull-down switch S1, and the second end of the pull-down switch S1 is connected to the ground potential VSS.

The embodiment provides a power switch circuit overshoot prevention method, which is used for realizing slow power-up of a power switch circuit, and comprises the following steps:

the pull-down switch S1 is controlled to be alternately closed and opened through a pulse signal; the pulse width of the pulse signal is adjusted to control the closing duration and the opening duration of the pull-down switch S1, so as to control the drain voltage of the P-channel MOS tube M2 to change to a target value.

Further, the PWM control module generates a pulse signal to control the pull-down switch S1 to operate, specifically, when the pulse signal is at a high level, the pull-down switch S1 is closed, and when the pulse signal is at a low level, the pull-down switch S1 is opened.

As shown in fig. 14, the pull-down switch S1 is controlled to be turned on and off alternately by a pulse signal to control the drain voltage of the P-channel MOS transistor M2 to rise progressively.

In the first pulse signal period, the pulse signal is high-level pull-down switch S1 is closed, the drain end voltage of the P-channel MOS tube M2 is increased from the initial voltage to the first voltage, the pulse signal is low-level pull-down switch S1 is opened, and the drain end voltage of the P-channel MOS tube M2 is reduced from the first voltage to the second voltage, wherein the first voltage is larger than the initial voltage. Because the high-level pulse width of the pulse signal is larger than the low-level pulse width of the pulse signal, the second voltage is smaller than the first voltage and larger than the initial voltage, after the period of the first pulse signal, the drain end voltage of the P-channel MOS tube M2 is raised and lowered, and then the progressive rise is realized relative to the initial voltage.

In the next pulse signal period, the drain end voltage of the P-channel MOS tube M2 is changed from the second voltage to a third voltage after rising and falling, wherein the third voltage is larger than the first voltage; after the drain voltage of the P-channel MOS transistor M2 rises to the target value after a plurality of pulse signal periods, the pulse signal maintains a high level, and the pull-down switch S1 remains closed.

In an embodiment, in the power-up process of the power switch circuit using the P-channel MOS transistor M2, the accumulated closing duration of the pull-down switch S1 is controlled to be longer than the accumulated opening duration, i.e., the accumulated high-level pulse width of the pulse signal is longer than the accumulated low-level pulse width, i.e., the accumulated power-up time period in the power-up process of the P-channel MOS transistor M2 is longer than the accumulated power-down time period, so that the drain voltage of the P-channel MOS transistor M2 is changed to the target value.

In an embodiment, in the power-on process of the power switch circuit using the P-channel MOS transistor M2, the high-level pulse width is greater than the low-level pulse width in all pulse periods. In other embodiments, the high pulse width is greater than the low pulse width during a portion of the pulse period.

In a preferred but non-limiting embodiment of the present invention, as the pulse timing is changed, the high level pulse width in a plurality of periods is kept the same, the low level pulse width is gradually decreased, or the high level pulse width is gradually increased, the low level pulse width is kept the same, or the high level pulse width is gradually increased, the low level pulse width is gradually decreased, and the power switch circuit composed of the P-channel MOS transistor M2 and the pull-down switch S1 is powered up slowly.

Example 8

As shown in fig. 15, the difference between the present embodiment and embodiment 7 is that, for the power switch circuit shown in fig. 13, when the pulse signal is at low level, the pull-down switch S1 is turned on to control the P-channel MOS transistor M2 to be turned on, so that the power switch circuit starts to be powered on; when the pulse signal is at a high level, the pull-down switch S1 is turned off to control the P-channel MOS transistor M2 to be turned off, so that the power switch circuit starts to be powered down.

The accumulated closing duration time of the pull-down switch S1 is controlled to be larger than the accumulated opening duration time, namely the accumulated low-level pulse width of the pulse signal is larger than the accumulated high-level pulse width, namely the accumulated power-on time length in the power-on process of the P-channel MOS tube M2 is larger than the accumulated power-off time length, so that the drain end voltage of the P-channel MOS tube M2 is changed to a target value.

In an embodiment, in the power-on process of the power switch circuit using the P-channel MOS transistor M2, the low-level pulse width is greater than the high-level pulse width in all pulse periods. In other embodiments, the low level pulse width is greater than the high level pulse width during a portion of the pulse period.

In a preferred but non-limiting embodiment of the present invention, as the pulse timing is changed, the low level pulse width in a plurality of periods is kept the same, the high level pulse width is gradually decreased, or the low level pulse width is gradually increased, the high level pulse width is kept the same, or the low level pulse width is gradually increased, the high level pulse width is gradually decreased, and the power switch circuit composed of the P-channel MOS transistor M2 and the pull-down switch S1 is powered up slowly.

The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (10)

1. A method of preventing overshoot in a power switching circuit comprising a transistor and a switch connected to a gate of the transistor, the method comprising:

the switch is controlled to be alternately closed and opened through a pulse signal;

the closing duration and the opening duration of the switch are controlled by adjusting the pulse width of the pulse signal, so that the drain voltage of the transistor is controlled to be changed to a target value.

2. The power switching circuit overshoot prevention method of claim 1, said method comprising:

generating a pulse signal through a PWM control module to control the switching action;

the switch is controlled to be alternately closed and opened by a pulse signal so as to control the voltage of the drain terminal of the transistor to rise or fall;

after the drain terminal voltage of the transistor rises or falls to a target value, the pulse signal maintains a high level or a low level.

3. The power switching circuit overshoot prevention method of claim 1, said method comprising: the accumulated closing duration of the switch is controlled to be larger than the accumulated opening duration so as to enable the drain voltage to be changed to the target value.

4. The power switching circuit overshoot prevention method of claim 2, said method comprising: the pulse signal is high-level control switch closed, and the pulse signal is low-level control switch open.

5. The power switching circuit overshoot prevention method of claim 2, said method comprising: the pulse signal is a low-level control switch which is closed, and the pulse signal is a high-level control switch which is opened.

6. The method of claim 4, wherein the high-level pulse width is greater than the low-level pulse width during all pulse periods or the high-level pulse width is greater than the low-level pulse width during part of the pulse periods before the drain voltage is changed to the target value.

7. The method of claim 5, wherein the low-level pulse width is greater than the high-level pulse width during all pulse periods or the low-level pulse width is greater than the high-level pulse width during part of the pulse periods before the drain voltage is changed to the target value.

8. The overshoot prevention method of a power switching circuit according to claim 4, wherein a high level pulse width of said pulse signal is the same or gradually increases, and a low level pulse width of said pulse signal is gradually decreased or the same.

9. The overshoot prevention method of a power switching circuit according to claim 5, wherein a low level pulse width of said pulse signal is the same or gradually increases, and a high level pulse width of said pulse signal is the same or gradually decreases.

10. A power switching circuit for implementing the power switching circuit overshoot prevention method according to any one of claims 1 to 9, wherein the circuit includes a transistor, a switch and a PWM control module,

the source electrode of the transistor is connected with ground potential or power supply voltage, and the drain electrode of the transistor is connected with a load;

one end of the switch is connected with the grid electrode of the transistor, one end of the switch is connected with the ground potential or the power supply voltage, and the switch is used for controlling the transistor to be turned on or turned off;

the PWM control module is used for generating pulse signals to control the switching action.