CN117637816A - Semiconductor device and manufacturing method - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The device includes: a substrate having a channel region; a MOS transistor including a gate located above the channel region; in the length direction of the gate A first isolation structure and a second isolation structure located on both sides of the channel region. The first isolation structure has a first protrusion located at the top and protruding toward the channel region. The second isolation structure has a first isolation structure located at the top and protruding toward the channel region. A second convex portion with a top end protruding toward the channel region. Compared with the prior art, the present invention forms a groove at the edge of the channel, and the insulating layer forms a corresponding protrusion at the groove, so that the thickness of the insulating material between the channel edge and the gate is increased. Such a structure increases the threshold voltage at the edge of the channel, which offsets the effect of reducing the threshold voltage caused by the edge electric field, thus improving the reverse narrow channel effect of the MOS device.

Description

Semiconductor device and manufacturing method

This application is a divisional application for a patent with a filing date of May 31, 2018, an application number of 201810550170.5, and an invention titled semiconductor devices and manufacturing methods thereof.

Technical field

The present invention mainly relates to the field of semiconductor technology, and in particular, to a semiconductor device that improves the reverse narrow channel effect of a MOS transistor.

Background technique

In the metal-oxide semiconductor (MOS) structure of Shallow Trench Isolation (STI), in the width direction of the MOS device, the gates on both sides of the channel cover part of the insulating isolation layer. When the gate voltage is applied, since the electric field at the gate edge terminates at the side of the channel, the electric field in the area near the channel edge close to the STI increases. This electric field makes the depletion layer at the edge deeper and makes the channel edge The surface potential increases, allowing the edge position to reverse shape earlier. Therefore, the threshold voltage (Threshold Voltage) at the edge of the channel is lower than the threshold voltage at the middle of the channel. This is called the reverse narrow channel effect.

When the width of the MOS device is large, the edge portion accounts for a small proportion, and the reverse narrow channel effect can be ignored. However, as the width of the MOS device decreases, the edge portion accounts for an increasing amount, which will reduce the threshold voltage of the entire MOS device.

With the development of integrated circuit technology, the size of devices is getting smaller and smaller, and the impact of the anti-narrow channel effect in shallow trench isolation MOS devices is becoming more and more significant.

Currently, methods to improve the reverse narrow channel effect require additional photomasks or process steps, which are costly and have limited effects.

Contents of the invention

The technical problem to be solved by the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the reverse narrow channel effect of MOS transistors without increasing process complexity and cost.

In order to solve the above technical problems, the present invention provides a semiconductor device, including: a substrate having a channel region; a MOS transistor including a gate located above the channel region; in the length direction of the gate A first isolation structure and a second isolation structure located on both sides of the channel region. The first isolation structure has a first protrusion located at the top and protruding toward the channel region. The second isolation structure has a first isolation structure located at the top and protruding toward the channel region. A second convex portion protruding from the top end toward the channel region.

In an embodiment of the present invention, two ends of the gate in the length direction are respectively located on the first convex portion and the second convex portion.

In an embodiment of the present invention, the boundary between the first protrusion and the channel region and/or the boundary between the second protrusion and the channel region is smooth.

In an embodiment of the present invention, the first convex part and/or the second convex part have a sector-shaped cross section in the length direction of the gate electrode.

In an embodiment of the present invention, the size of the first protrusion and/or the second protrusion in a direction perpendicular to the substrate is 1/5 to 1/3 of the width of the gate electrode. .

In an embodiment of the present invention, a linear oxide layer is formed between the first protrusion and the channel region, and/or between the second protrusion and the channel region.

In an embodiment of the present invention, the density of the linear oxide layer is greater than the density of the first convex portion or the second convex portion.

The invention also provides a method for manufacturing a semiconductor device, which includes the following steps: providing a substrate; forming a channel region in the substrate; and forming a first isolation structure located on both sides of the channel region in a set direction. and a second isolation structure. The first isolation structure has a first protrusion located at the top and protruding toward the channel region. The second isolation structure has a second protrusion located at the top and protruding toward the channel region. Part; forming a MOS transistor, the MOS transistor including a gate located above the channel region; wherein the setting direction is the length direction of the gate.

In an embodiment of the present invention, the step of forming a channel region in the substrate includes etching the substrate to correspond to the first isolation structure and the second isolation structure in the substrate. The positions of the structures form first trenches and second trenches respectively, and the substrate between the first trench and the second trench serves as the channel region; the first trench and the second trench are A first groove and a second groove that are recessed toward the channel region are respectively formed on the top of the side wall, so that the tops of the first groove and the second groove protrude toward the channel region.

In an embodiment of the present invention, the method of forming the first trench and the second trench includes: using an isotropic etching process to etch the substrate in the passive region to a first depth, and using an anisotropic etching process to etch the substrate in the passive area to a first depth. The etching process etches the substrate of the passive area to a second depth to form first trenches and second trenches.

In an embodiment of the present invention, the step of forming the first isolation structure and the second isolation structure located on both sides of the channel region in a set direction includes: Filling the insulating layer to form the first isolation structure and the second isolation structure respectively; the insulating layer filled in the first groove constitutes the first convex part; the insulating layer filled in the second groove The layers constitute the second protrusion.

In an embodiment of the present invention, two ends of the gate in the length direction are respectively located on the first convex portion and the second convex portion.

In an embodiment of the present invention, the boundary between the first protrusion and the channel region and/or the boundary between the second protrusion and the channel region is smooth.

In an embodiment of the present invention, the first convex part and/or the second convex part have a sector-shaped cross section in the length direction of the gate electrode.

In an embodiment of the present invention, a size of the first protrusion and/or the second protrusion in a direction perpendicular to the substrate is 1/5 to 1/5 of the width of the gate. /3.

In an embodiment of the present invention, after forming the first groove and the second groove, the method further includes: thermally growing a linear oxide layer on the first groove and/or the second groove.

In an embodiment of the present invention, the thickness of the linear oxide layer is 1-5 nm.

In an embodiment of the present invention, the step of forming the first isolation structure and the second isolation structure in the first trench and the second trench respectively includes: covering the substrate with an insulating layer; planarizing ize the substrate surface.

The invention also provides a semiconductor device, including: a substrate having a channel region; a MOS transistor including a gate located above the channel region; and located in the channel region in the length direction of the gate. The first isolation structure and the second isolation structure on both sides; the top of the first side wall of the channel area adjacent to the first isolation structure has a first groove, and the first isolation structure has a protrusion extending to The first convex part of the first groove, the top of the second side wall of the channel area adjacent to the second isolation structure has a second groove, the second isolation structure has a protrusion extending to the first The second convex portion of the two grooves.

In an embodiment of the present invention, two ends of the gate in the length direction are respectively located on the first convex portion and the second convex portion.

Compared with the existing technology, the present invention has the following advantages: The present invention provides a semiconductor device that improves the reverse narrow channel effect of a MOS transistor and a manufacturing method thereof. A groove is formed at the edge of the channel, and an insulating layer is formed at the groove. Protrusions are formed correspondingly, so that the thickness of the insulating material between the channel edge and the gate electrode is increased. Such a structure increases the threshold voltage at the edge of the channel, which offsets the effect of reducing the threshold voltage caused by the edge electric field, thereby improving the reverse narrow channel effect of the MOS device.

Description of drawings

Figure 1 is a top view of a semiconductor device with a MOS transistor;

Figure 2 is an A-A cross-sectional view of the semiconductor device having a MOS transistor in Figure 1;

Figure 3 is a B-B cross-sectional view of the semiconductor device having a MOS transistor in Figure 1;

Figure 4 is a schematic cross-sectional view of a semiconductor device with a MOS transistor according to an embodiment of the present invention;

Figure 5 is a schematic cross-sectional view of a semiconductor device having a MOS transistor according to another embodiment of the present invention;

Figure 6 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;

7A-7H are cross-sectional schematic diagrams of an exemplary process of forming a semiconductor device according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of results of semiconductor process device simulation according to an embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more obvious and understandable, specific implementation modes of the present invention are described in detail below with reference to the accompanying drawings.

Many specific details are set forth in the following description to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, so the present invention is not limited to the specific embodiments disclosed below.

As shown in this application and claims, words such as "a", "an", "an" and/or "the" do not specifically refer to the singular and may include the plural unless the context clearly indicates an exception. Generally speaking, the terms "comprising" and "comprising" only imply the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or apparatus may also include other steps or elements.

When describing the embodiments of the present invention in detail, for convenience of explanation, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual production.

For convenience of description, spatial relationship words such as "below", "below", "below", "below", "above", "on", etc. may be used herein to describe an element shown in the drawings or the relationship of a feature to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "below" can encompass both upper and lower directions. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, structures described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features. Embodiments between second features such that the first and second features may not be in direct contact.

FIG. 1 is a top view of a semiconductor device 10 having a MOS transistor. As shown in FIG. 1 , a semiconductor device 10 having one or more MOS transistors (one example is shown in the figure) includes a shallow trench isolation structure STI 101 , an active region 102 and a gate 103 . The semiconductor device 10 is divided into A-A direction and B-B direction, where the B-B direction refers to the length direction along the MOS transistor gate, the A-A direction refers to the width direction along the MOS transistor gate, and the A-A direction is perpendicular to the B-B direction. The shallow trench isolation structure STI101 is located outside the active area 102 and surrounds the active area 102 . The semiconductor device 10 having a MOS transistor can be applied to various fields such as power devices and circuit control.

FIG. 2 is an A-A cross-sectional view of the semiconductor device 10 including the MOS transistor in FIG. 1 . As shown in FIG. 2 , the substrate 104 has an active area and a passive area. A shallow channel isolation structure STI 101 is formed in the passive area, and the STI 101 defines the active area. MOS transistors are formed in the active area. The MOS transistor includes a gate 103, a source region 105, a drain region 106, a channel region 107 and a well region 108. The channel region 107 is located between the source region 105 and the drain region 106 , and the gate 103 is located above the channel 107 . The structure of MOS transistors is known in the art and will not be described in detail in the present invention.

FIG. 3 is a B-B cross-sectional view of the semiconductor device 10 including the MOS transistor in FIG. 1 . As shown in FIG. 3 , in the MOS transistor structure of the shallow trench isolation STI 101 , in the width direction of the MOS device, the gates 103 on both sides of the channel 107 cover part of the insulating isolation layer. When the gate voltage is applied, since the electric field at the gate edge terminates at the side of the channel 107, the electric field in the area near the edge of the channel 107 close to the STI 101 increases. This electric field makes the depletion layer at the edge deeper and makes the trench The surface potential at the edge of the track increases, allowing the edge to reverse shape earlier. Therefore, the threshold voltage at the edge of the channel 107 is lower than the threshold voltage at the middle of the channel, which is called the inverse narrow channel effect.

When the width of the MOS device is large, the edge portion accounts for a small proportion, and the reverse narrow channel effect can be ignored. However, as the width of the MOS device decreases, the edge portion accounts for an increasing amount, which will reduce the threshold voltage of the entire MOS device. With the development of integrated circuit technology, the size of devices is getting smaller and smaller, and the impact of the anti-narrow channel effect in shallow trench isolation MOS devices is becoming more and more significant. Therefore, there is a need to provide an improved semiconductor device to improve the reverse narrow channel effect.

FIG. 4 is a schematic cross-sectional view of a semiconductor device 20 having a MOS transistor according to an embodiment of the present invention. This schematic cross-sectional view is a schematic cross-sectional view in the length direction of the gate of the MOS transistor. The semiconductor device 20 includes a MOS transistor 21 and a first isolation structure 205 and a second isolation structure 206 that isolate the MOS transistor. Although one MOS transistor is illustrated in FIG. 4 , it can be understood that the semiconductor device 20 may include multiple MOS transistors. These MOS transistors are isolated by the first isolation structure 205 and the second isolation structure 206 .

Referring to FIG. 4, the MOS transistor 21 is located in the active area. It can be understood that the MOS transistor 21 may include typical structures such as a source region, a drain region, and a gate as shown in FIG. 2 . FIG. 4 is a cross-sectional view along the length direction of the gate of the MOS transistor, so the source region and the drain region are not shown in FIG. 4 .

Semiconductor device 20 includes substrate 201. Substrate 201 has channel region 202. Source and drain regions are formed in substrate 201 . Channel region 202 is formed between the source region and the drain region. The channel region 202 may be doped to adjust the threshold voltage of the MOS transistor. P-type impurities can be doped for increasing the threshold voltage of the n-MOSFET. N-type impurities can also be added to obtain depletion-mode MOSFETs.

The MOS transistor 21 includes a gate electrode 203 located above the channel region 202 . Both ends of the gate 203 in the length direction are respectively located on the first convex portion 209 and the second convex portion 210 described below. A gate oxide layer 204 is included between the gate electrode 203 and the channel region 202 to prevent the gate electrode 203 from destructive breakdown. The material of the gate oxide layer 204 may be silicon oxide (SiO ₂ ) or the like.

The semiconductor device 20 also includes a first isolation structure 205 and a second isolation structure 206 respectively located on both sides of the channel region 202 in the length direction of the gate of each MOS transistor. The first isolation structure 205 and the second isolation structure 206 form a shallow trench isolation structure. Shallow trench isolation structures define active areas. The area on the substrate 201 other than the shallow trench isolation structure is the active area. The first isolation structure 205 and the second isolation structure 206 are made of insulating materials. Examples of insulating materials include silicon oxide, silicon nitride, silicon oxynitride, and the like. In one embodiment, the first isolation structure 205 and the second isolation structure 206 may be the same material as the gate oxide layer 204, such as silicon oxide _SiO2 .

The top of the first sidewall of the channel region 202 adjacent to the first isolation structure 205 has a first groove 207 , and the top of the second sidewall of the channel region 202 adjacent to the second isolation structure 206 has a second groove 208 . The first groove 207 and/or the second groove 208 may be smooth or non-smooth. Here, smooth grooves help to improve the uniformity of the electric field compared to uneven grooves. For example, the cross section of the first groove 207 and/or the second groove 208 in the length direction of the gate may be an arc shape, such as a circular arc shape or an elliptical arc shape. It is understood that the shapes recited here are approximate and the shapes of grooves 207 and/or 208 may be varied for various purposes. For example, the intersection between the arc-shaped groove and the sidewall and/or top surface of the channel region 202 may also have a smooth profile, thereby further improving the uniformity of the electric field. At this time, the grooves 207 and/or 208 are approximately arc-shaped.

The size of the first groove 207 and/or the second groove 208 in a direction perpendicular to the substrate 201 may be related to the width of the gate of the MOS transistor. For example, the size of the first groove 207 and/or the second groove 208 in a direction perpendicular to the substrate 201 may be 1/5 to 1/3 of the width of the gate of the corresponding MOS transistor.

The first isolation structure 205 has a first protrusion 209 located at the top and protruding toward the channel region 202 , and the second isolation structure 206 has a second protrusion 210 located at the top and protruding toward the channel region 202 . The first protrusion 209 is formed by the first isolation structure 205 protruding into the first groove 207 , and the second protrusion 210 is formed by the second isolation structure 206 protruding into the second groove 208 . Since the first protrusion 209 is formed by the first isolation structure 205 protruding into the first groove 207, the structures of the first protrusion 209 and the first groove 207 are complementary. Since the second protrusion 210 is formed by the second isolation structure 206 protruding into the second groove 208, the structures of the second protrusion 210 and the second groove 208 are also complementary. The boundary between the first convex part 209 and the channel region 202 and/or the boundary between the second convex part 210 and the channel region 202 is smooth. The cross-section of the first protrusion 209 and/or the second protrusion 210 in the length direction of the gate may be fan-shaped or a variation thereof. The size of the first protrusion 209 and/or the second protrusion 210 in a direction perpendicular to the substrate 201 may be related to the width of the gate of the MOS transistor. For example, the size of the first protrusion 209 and/or the second protrusion 220 in a direction perpendicular to the substrate 201 may be 1/5 to 1/3 of the width of the gate of the MOS transistor.

Since the first groove 207 and the second groove 208 are provided at the top of the sidewalls of the channel region 202 adjacent to the first isolation structure 205 and the second isolation structure 206, the first isolation structure 205 and the second isolation structure 206 accordingly The formation of the first convex part 209 and the second convex part 210 increases the thickness of the gate oxide layer at the channel edge and increases the threshold voltage at the channel edge position, which offsets the effect of reducing the threshold voltage caused by the edge electric field, thereby improving the Inverse narrow channel effect of MOS devices.

In another embodiment of the present invention, referring to FIG. 5 , a linear oxide layer (linear oxide layer) is formed between the first convex part 209 and the channel region 202 and/or between the second convex part 209 and the channel region 202 )211. The thickness of the linear oxide layer 211 is 1-5 nm.

The linear oxide layer 211 may be obtained by oxidizing the material on the first groove 207 and/or the second groove 208, thereby changing the contours of the first groove 207 and/or the second groove 208.

In one example, linear oxide layer 211 is formed by thermal growth. The density of the linear oxide layer 211 is greater than the density of the first convex portion 209 or the second convex portion 210 in the corresponding groove.

Since the formation process of the linear oxide layer 211 changes the contours of the first groove 207 and/or the second groove 208, the contours of the first groove 207 and/or the second groove 208 are smoother, thereby improving the electric field in local uniformity.

FIG. 6 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention. 7A-7H are cross-sectional schematic diagrams of an exemplary process of forming a semiconductor device according to an embodiment of the present invention. The method of forming the semiconductor device of this embodiment will be described below with reference to FIGS. 6-7H. The method of forming a semiconductor device according to this embodiment of the invention includes:

Step 302: Provide a substrate.

Provide a substrate that provides support and good electrical properties for subsequent steps. The material of the substrate can be silicon carbide (SiC), silicon (Si), etc. The substrate generally requires pretreatment to improve the adhesion ability of the substrate surface. Methods to improve substrate surface adhesion include evaporating moisture from the substrate surface and applying compounds to the substrate surface. The smeared compound can be hexa-methyl-disilazane (HMDS), tri-methyl-silyl-diethyl-amime (TMSDEA), etc.

Step 304: Form a channel region in the substrate.

The step of forming the channel region in the substrate includes: etching the substrate to form first trenches and second trenches respectively at positions corresponding to the first isolation structure and the second isolation structure in the substrate. The substrate between the trench and the second trench serves as the channel region.

Forming the channel region in the substrate can be seen in the exemplary process of Figures 7A-7E.

In the cross-sectional view of the semiconductor structure illustrated in FIG. 7A , an etch stop layer 402 is formed on a substrate 401 . For example only, the etch stop layer 402 may include a pad oxide layer (Pad Oxide) and a silicon nitride (SiN) layer. The pad oxide layer is located on the substrate 401, and the silicon nitride layer is located on the pad oxide layer. The pad oxide layer is used to provide a buffer for the etching barrier layer 402 to prevent the substrate 401 from being subjected to large stress and causing mechanical damage. Those skilled in the art can understand that the etching barrier layer 402 may be other structures or materials. For example, the etch stop layer 402 includes a photoresist layer and a silicon oxide layer.

Figure 7B shows the etch barrier layer after patterning. As shown in FIG. 7B , after the etching barrier layer 402 is patterned, part of the substrate 401 is exposed. The exposed substrate 401 forms a passive area, and the substrate 401 covered by the etching barrier layer 402 forms an active area. district. A method of patterning the etch barrier layer 402 includes photolithography using a photomask. Using a photomask to perform photolithography is a known technology and will not be described in detail this time.

Reference is made below to Figures 7C-7D. 7C-7D illustrate an exemplary process of forming first trenches and second trenches.

After etching the etch stop layer, the exposed substrate is etched using an isotropic etching process. Isotropic etching means that the etching rate in all directions is consistent. In this embodiment, each direction refers to the lateral and vertical directions. Specifically, referring to FIG. 7C , an isotropic etching process is used to longitudinally etch the substrate 401 in the passive region to a first depth. Since the etching rate in each direction in the isotropic etching is consistent, the substrate 401 is The sides are also etched. Isotropic etching can be wet chemical etching. As just one example of isotropic etching, the substrate 401 may be isotropically etched using hydrofluoric acid HF and nitric acid HNO ₃ as etchants.

Then, as shown in FIG. 7D , an anisotropic etching process is used to etch the substrate of the passive region to a second depth to form a first trench and a second trench.

Anisotropic etching means that the etching rate in each direction is different and can be etched to a greater depth. Perfect anisotropic etching means that the etching is only in one direction. In this embodiment, the etching rate in the vertical direction is greater than the etching rate in the lateral direction. Referring to FIG. 7D , anisotropic etching is used to longitudinally etch the substrate 401 of the passive region to a second depth. The second depth is greater than the first depth because the etching rate in the vertical direction is greater than the etching rate in the lateral direction. rate, the substrate 401 is subjected to little or no etching in the lateral direction. The value of the second depth can be controlled by parameters of anisotropic etching, such as etching time, etchant temperature, etc. Anisotropic etching may be dry plasma etching. After isotropic etching and anisotropic etching, a first trench 403 and a second trench 404 are formed on the substrate 401. The substrate between the first trench 403 and the second trench 404 forms a channel region.

The tops of the side walls of the first trench 403 and the second trench 404 are respectively formed with a first groove 405 and a second groove 406 that are recessed toward the channel area, so that the tops of the first trench 403 and the second trench 404 protrudes toward the channel area. The shapes of the first groove 405 and the second groove 406 in the length direction of the gate may be arc-shaped or other shapes. The shapes of the first groove 405 and the second groove 406 can be controlled by adjusting parameters of isotropic etching, such as etchant concentration, etching time, etchant temperature, etc. When the isotropy of etching is good, the shapes of the first groove 405 and the second groove 406 may be arc shapes.

After the channel region is formed in the substrate 401, the etching barrier layer 402 needs to be removed. The structure of the substrate after removing the etching barrier layer 402 is shown in FIG. 7E. The etching barrier layer 402 can be removed by cleaning using a cleaning agent. The cleaning agent can be phosphoric acid and other types of cleaning agents. After removing the etching barrier layer 402 , the method may further include thermally growing a linear oxide layer on the first groove 405 and/or the second groove 406 . Thermal growth will erode away the tip portion of the groove. The thickness of the linear oxide layer can be 1-5nm.

Step 306: Form a first isolation structure and a second isolation structure located on both sides of the channel region in a set direction.

The method for forming the first isolation structure and the second isolation structure on both sides of the channel region in a set direction may be deposition. The setting direction refers to the length direction of the gate of the MOS transistor. The first trench 403 and the second trench 404 are filled with an insulating layer to form a first isolation structure and a second isolation structure respectively. The insulating layer filled in the first groove 405 forms the first protrusion 407 . The insulating layer filled in the second groove 406 forms the second protrusion 408 . The boundary between the first protrusion 407 and the channel region and/or the boundary between the second protrusion 408 and the channel region may be smooth. The cross section of the first convex part 407 and/or the second convex part 408 in the length direction of the gate is fan-shaped. The size of the first protrusion 407 and/or the second protrusion 408 in a direction perpendicular to the substrate is 1/5 to 1/3 of the width of the gate. The formation of the first isolation structure and the second isolation structure is shown in Figures 7F-7G. In FIG. 7F , the substrate 401 is covered with an insulating layer 409. Due to the existence of the first trench 403 and the second trench 404, the surface of the insulating layer 409 is not flat. Then, the surface of the substrate 401 is planarized, and the insulating layer 409 in the trench in the passive area is retained. The surface of the substrate 401 after the planarization process is shown in FIG. 7G , in which the insulating layer 409 and the substrate 401 in the active area are on the same plane. The insulating layer 409 located in the first trench 403 forms a first isolation structure 410 , and the insulating layer 409 located in the second trench 404 forms a second isolation structure 411 .

Step 308: Form MOS transistors.

After steps 302-306, the first isolation structure 410 and the second isolation structure 411 have been formed, and then the MOS transistor is formed. Forming a MOS transistor involves channel doping. Channel doping refers to implanting a small amount of donor or acceptor impurity ions into the channel area through ion implantation technology to adjust the threshold voltage of the MOS transistor. P-type impurities can be doped for increasing the threshold voltage of the n-MOSFET. N-type impurities can also be added to obtain depletion-mode MOSFETs. Those skilled in the art can understand that channel doping does not necessarily have to be performed after the shallow trench isolation structure is formed, but can also be performed at other appropriate times. For example, channel doping can be performed during the well making process on the substrate 401 before forming the shallow channel isolation structure.

FIG. 7H shows the semiconductor structure after gate formation. Referring to Figure 7H, gate 412 is formed over the channel region. Both ends of the gate 412 in the length direction are respectively located on the first convex portion 407 and the second convex portion 408 . A gate oxide layer may also be included between the channel region and the gate 412 to prevent destructive breakdown of the gate 412 . Forming the gate oxide layer over the channel may be performed after forming the shallow trench isolation structure. The material of the gate oxide layer may be the same material as the first isolation structure and the second isolation structure, such as silicon oxide SiO ₂ or the like.

A MOS transistor includes a gate, source and drain regions. After the gate is formed, the next step is to form the source and drain regions of the MOS transistor. The source region and the drain region are located on both sides of the channel along the width direction of the gate 412 . Those skilled in the art can understand that the method is not limited to forming the gate electrode first, and then forming the source region and drain region. The source region and drain region may also be formed first, and then the gate electrode is formed.

Since the first groove 405 and the second groove 406 are provided at the top of the sidewall of the channel area adjacent to the first isolation structure 410 and the second isolation structure 411, the first isolation structure 410 and the second isolation structure 411 are formed accordingly. The first convex part 407 and the second convex part 408 are added, so that the thickness of the gate oxide layer at the channel edge is increased, and the threshold voltage at the channel edge position is increased, which offsets the effect of reducing the threshold voltage caused by the edge electric field, thereby improving the MOS The inverse narrow channel effect of the device.

FIG. 8 is a schematic diagram of the results of semiconductor process device simulation. The abscissa is the characteristic size of the semiconductor device, in microns. The ordinate is the threshold voltage in volts. Among the three isotropic etching depths, isotropic etching depth 1 < isotropic etching depth 2 < isotropic etching depth 3. The isotropic etching depth 1 can be 0. It can be seen from Figure 8 that in the low feature size W range, as the isotropic etching depth increases, the threshold voltage decreases slowly, which shows that the reverse narrow channel effect of the MOS device has been improved.

This application uses specific words to describe embodiments of the application. For example, "one embodiment", "an embodiment", and/or "some embodiments" means a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that “one embodiment” or “an embodiment” or “an alternative embodiment” mentioned twice or more at different places in this specification does not necessarily refer to the same embodiment. . In addition, certain features, structures or characteristics in one or more embodiments of the present application may be appropriately combined.

Although the present invention has been described with reference to the present specific embodiments, those of ordinary skill in the art will realize that the above embodiments are only used to illustrate the present invention, and may also be made without departing from the spirit of the invention. Various equivalent changes or substitutions are made. Therefore, as long as the changes and modifications to the above-described embodiments are within the scope of the essential spirit of the present invention, they will fall within the scope of the claims of the present application.

Claims (38)

1. A semiconductor device, comprising: a substrate having a channel region; A gate electrode located on the channel region; The channel region includes a first sidewall and a second sidewall that are oppositely arranged in the length direction of the gate. The first sidewall has a first recess at one end close to the gate, and the second sidewall is disposed oppositely in the length direction of the gate. One end of the side wall close to the gate has a second recess. 2. The semiconductor device according to claim 1, wherein the semiconductor device further comprises an insulating material, the insulating material being disposed in the first recessed portion and the second recessed portion. 3. The semiconductor device according to claim 1, further comprising a first isolation structure and a second isolation structure located on both sides of the channel region in the length direction of the gate electrode. structure, the first isolation structure has a first convex part protruding to the first recessed part, and the second isolation structure has a second convex part protruding to the second recessed part. 4. The semiconductor device according to claim 3, wherein the semiconductor device further comprises a gate oxide layer, the gate oxide layer being located between the gate electrode and the channel region. 5. The semiconductor device according to claim 1, wherein both ends of the gate in the length direction are respectively located above the first recess and the second recess. 6. The semiconductor device according to claim 5, wherein in a direction perpendicular to the substrate, the projection of the gate electrode on the substrate is consistent with the first recess and the second recess. The recesses overlap. 7. The semiconductor device according to claim 1, wherein the first recessed portion and the second recessed portion are arc-shaped. 8. The semiconductor device according to claim 1, wherein the first recessed portion and the second recessed portion are smooth. 9. The semiconductor device according to claim 1, wherein the cross-section of the first recess and/or the second recess in the length direction of the gate is sector-shaped. 10. The semiconductor device according to claim 1, wherein a size of the first recess and/or the second recess in a direction perpendicular to the substrate is 1/ of the width of the gate. 5 to 1/3. 11. The semiconductor device according to claim 3, wherein a gap is provided between the first convex part and the first recessed part and/or between the second convex part and the second recessed part. Linear oxide layer. 12. The semiconductor device according to claim 11, wherein the density of the linear oxide layer is greater than the density of the first convex portion or the second convex portion. 13. The semiconductor device according to claim 11, wherein the linear oxide layer has a thickness of 1-5 nm. 14. A semiconductor device, comprising: a substrate having a channel region; a gate electrode located on the channel region; and An insulating structure includes a first protrusion and a second protrusion protruding toward the channel region, and the first protrusion and the second protrusion are connected to the channel region. 15. The semiconductor device according to claim 14, wherein the first convex portion and the second convex portion are arranged opposite to each other in the length direction of the gate electrode. 16. The semiconductor device according to claim 14, wherein the channel region includes a first sidewall and a second sidewall that are oppositely arranged in a length direction of the gate electrode, and the first sidewall One end of the second side wall is close to the gate and has a first recess. One end of the second side wall is close to the gate and has a second recess. The first protrusion extends to the first recess. The second protrusion The portion protrudes to the second concave portion. 17. The semiconductor device according to claim 14, wherein the insulating structure includes: A first isolation structure and a second isolation structure located on both sides of the channel region in the length direction of the gate electrode, the first isolation structure includes the first protrusion, and the second isolation structure includes the The second convex portion; A gate oxide layer is located between the gate electrode and the channel region. 18. The semiconductor device according to claim 17, wherein the first protrusion and the second protrusion are connected to the gate oxide layer. 19. The semiconductor device according to claim 14, wherein both ends of the gate electrode in the length direction are respectively located on the first convex portion and the second convex portion. 20. The semiconductor device according to claim 19, wherein in a direction perpendicular to the substrate, the projection of the gate electrode on the substrate is consistent with the first protrusion and the third The projections of the two protrusions on the substrate overlap. 21. The semiconductor device according to claim 16, wherein the first convex portion and the second convex portion are arc-shaped. 22. The semiconductor device according to claim 16, wherein the first convex portion and the second convex portion are smooth. 23. The semiconductor device according to claim 14, wherein the first protrusion and/or the second protrusion have a sector-shaped cross section in the length direction of the gate electrode. 24. The semiconductor device according to claim 14, wherein a size of the first protrusion and/or the second protrusion in a direction perpendicular to the substrate is a width of the gate electrode. 1/5 to 1/3. 25. The semiconductor device according to claim 14, wherein a gap is provided between the first protrusion and the channel region, and/or between the second protrusion and the channel region. Linear oxide layer. 26. The semiconductor device according to claim 25, wherein the density of the linear oxide layer is greater than the density of the first convex portion or the second convex portion. 27. The semiconductor device according to claim 25, wherein the linear oxide layer has a thickness of 1-5 nm. 28. A semiconductor device, comprising: a substrate having a channel region; a gate electrode located on the channel region; and Insulating structure, the insulating structure includes a first convex portion and a second convex portion protruding toward the channel region, and the first convex portion and the second convex portion are opposite to each other in the length direction of the gate electrode. set up; Wherein, the channel region includes a first sidewall and a second sidewall that are oppositely arranged in the length direction of the gate, and an end of the first sidewall close to the gate has a first recess, and the An end of the second side wall close to the gate has a second recessed portion, the first convex portion protrudes to the first recessed portion, and the second convex portion protrudes to the second recessed portion. 29. The semiconductor device according to claim 28, wherein the insulating structure includes: A first isolation structure and a second isolation structure located on both sides of the channel region in the length direction of the gate, the first isolation structure including the first protrusion, and the second isolation structure including the second convex portion; A gate oxide layer is located between the gate electrode and the channel region. 30. The semiconductor device according to claim 29, wherein the first protrusion and the second protrusion are connected to the gate oxide layer. 31. The semiconductor device according to claim 28, wherein both ends of the gate in the length direction are respectively located above the first recess and the second recess. 32. The semiconductor device according to claim 31, wherein in a direction perpendicular to the substrate, the projection of the gate electrode on the substrate is consistent with the first recess and the second recess. The recesses overlap. 33. The semiconductor device according to claim 28, wherein the first recessed portion and the second recessed portion are arc-shaped. 34. The semiconductor device according to claim 28, wherein the first recessed portion and the second recessed portion are smooth. 35. The semiconductor device according to claim 28, wherein the cross section of the first recess and/or the second recess in the length direction of the gate is fan-shaped. 36. The semiconductor device according to claim 28, wherein a gap is provided between the first convex part and the first recessed part and/or between the second convex part and the second recessed part. Linear oxide layer. 37. The semiconductor device according to claim 36, wherein the density of the linear oxide layer is greater than the density of the first convex portion or the second convex portion. 38. The semiconductor device according to claim 36, wherein the thickness of the linear oxide layer is 1-5 nm.