CN117579189B

CN117579189B - Measurement and control communication ground comprehensive tester

Info

Publication number: CN117579189B
Application number: CN202311441772.4A
Authority: CN
Inventors: 刘迪; 王竹刚; 韩霜雪; 王静; 陈轩; 杜家昊
Original assignee: National Space Science Center of CAS
Current assignee: National Space Science Center of CAS
Priority date: 2023-11-01
Filing date: 2023-11-01
Publication date: 2024-12-24
Anticipated expiration: 2043-11-01
Also published as: CN117579189A

Abstract

The invention provides a ground comprehensive tester for measurement and control communication, which comprises an upper computer, a FPGA platform, a radio frequency integrated platform and an automatic gain control, wherein the upper computer is used for carrying out modulation and demodulation parameter configuration and output signal power adjustment on the FPGA platform, is used for sending a baseband data stream to the FPGA platform and receiving and storing the baseband data stream from the FPGA platform, and is also used for monitoring and displaying the real-time state of the tester, the FPGA platform is used for completing the processing and modulation and demodulation of the baseband data stream, the radio frequency integrated platform is used for carrying out configuration and link state monitoring, and the radio frequency integrated platform is used for completing up/down frequency conversion, filtering, low noise amplification and automatic gain control of signals. The tester provided by the invention has the advantages of high integration level, strong portability and high reusability, and can meet the requirements of subsequent models only by simple increase, decrease or change, thereby reducing the design difficulty and the time cost.

Description

Measurement and control communication ground comprehensive tester

Technical Field

The invention belongs to the technical field of electronics, measurement and control communication, and particularly relates to a measurement and control communication ground comprehensive tester.

Background

While on-board equipment development is advanced, ground detection equipment (ground detection for short) is often required to be designed or purchased to cooperate with debugging, testing, acceptance and other works of on-board equipment.

In the measurement and control communication task, the data format protocol, the modulation mode, the data rate, the signal characteristics and the like of each task are different, and even one task comprises a plurality of modes.

The conventional measurement and control communication ground comprehensive tester has the defects of large volume, inconvenience in carrying, inconvenience in field test and field maintenance, more complex operation, and capability of mastering a use method through professional training, thereby increasing the use cost to a certain extent, and certain limitation in data processing, and difficulty in meeting the requirements of complex test tasks. The cost is too high when the conventional measurement and control communication ground comprehensive tester is used for testing, and once the project requirement changes, the workload of ground test developers is greatly increased. Therefore, it is necessary to design a flexible, highly integrated and highly portable ground comprehensive tester for measurement and control communication to adapt to the tasks of various types in the field of measurement and control communication.

Disclosure of Invention

The invention aims to overcome the defects of inflexible configuration, poor universality, weak portability, high cost and the like of the conventional tester.

In order to achieve the aim, the invention provides a ground comprehensive tester for measurement and control communication, which comprises an upper computer, an FPGA platform and a radio frequency integrated platform, wherein,

The upper computer is used for carrying out modulation-demodulation parameter configuration and output signal power adjustment on the FPGA platform, sending a baseband data stream to the FPGA platform, receiving the baseband data stream from the FPGA platform and storing the baseband data stream, and monitoring and displaying the real-time state of the tester;

The FPGA platform is used for completing the processing and modulation demodulation of the baseband data stream, configuring the radio frequency integrated platform and monitoring the link state;

The radio frequency integrated platform is used for receiving the baseband data stream output by the FPGA platform, finishing filtering, quadrature up-conversion and generating radio frequency analog signals, and also used for finishing low-noise amplification, quadrature down-conversion, filtering and automatic gain control after receiving the radio frequency signals, generating digital intermediate frequency signals and outputting the digital intermediate frequency signals to the FPGA platform.

As an improvement of the tester, the FPGA platform comprises a PS end and a PL end;

The PS terminal comprises data transmission modules DMA 0 and DMA 1, buffer memory FIFO 0 and FIFO 1 and GPIO, wherein,

The data transmission module DMA 0 is used for receiving a baseband data stream from the upper computer and outputting the baseband data stream to the cache FIFO 0;

The buffer FIFO 0 is configured to buffer a baseband data stream received by the data transmission module DMA 0;

The data transmission module DMA 1 is used for acquiring a baseband data stream from the FIFO 1 and outputting the baseband data stream to the upper computer;

the buffer FIFO 1 is configured to buffer a baseband data stream output by the receiving subsystem;

the GPIO is used for exchanging data between the upper computer and the FPGA platform;

the PL end comprises a transmit subsystem and a receive subsystem, wherein,

The transmitting terminal system is used for acquiring a baseband data stream from the buffer FIFO 0, and outputting the baseband data stream to the radio frequency integrated platform after frame synchronization, frame reorganization, encoding, scrambling and modulation;

the receiving terminal system is used for receiving the digital intermediate frequency signal sent by the radio frequency integrated platform, demodulating, synchronizing frames, descrambling and decoding the digital intermediate frequency signal, and outputting the digital intermediate frequency signal to the cache FIFO 1.

As an improvement of the above tester, the transmitting terminal system includes:

The frame synchronization module is used for receiving the baseband data stream sent by the PS end, finishing the fixed frame length frame synchronization of the intra-frame shielding frame head, and sending the processed baseband data stream to the reorganization frame module;

the frame reorganizing module is used for identifying the VCID of the current frame according to the frame format, counting the current frame, filling the frame count into the corresponding position in the current frame, and outputting a frame enabling signal, a mark to be coded and a reorganized frame to the coding module;

The coding module is used for finishing coding the recombined frame and outputting the coded recombined frame to the scrambling module;

A scrambling module for scrambling the encoded reorganized frame in frame unit and outputting the scrambled data to the modulation module, and

And the modulation module is used for completing modulation of different modulation modes and different data rates under corresponding modes for the scrambled data according to the modulation mode instruction sent by the upper computer.

As an improvement of the tester, the modulation module is also used for acquiring calibrated frequency offset, frequency sweep range, frequency sweep speed, frequency sweep zeroing and frequency sweep start-stop parameters from the PS end to finish frequency offset and frequency sweep setting of data.

As an improvement of the above tester, the receiving terminal system includes:

the demodulation module is used for receiving the digital intermediate frequency signal sent by the radio frequency integrated platform, demodulating the digital intermediate frequency signal, generating remote control log likelihood ratio soft decision information and outputting the remote control log likelihood ratio soft decision information to the frame synchronization module;

the frame synchronization module is used for configuring different frame synchronization parameters according to the demodulation mode provided by the upper computer, carrying out fixed-length frame synchronization on the remote control log likelihood ratio soft decision information, giving out a frame synchronization identifier, and outputting data after the frame synchronization to the descrambling module;

the descrambling module is used for descrambling a scrambling area of the frame-synchronized data and outputting the descrambled data to the pre-decoding processing module;

The decoding pre-processing module is used for removing frame heads from the effective frames of the descrambled data to generate frames with fixed length, performing setting processing, and outputting the frames to the decoding module after serial-parallel conversion;

The decoding module is used for decoding the data according to a decoding rule and outputting the decoded data and a state indication of a decoding result to the post-decoding processing module;

And the post-decoding processing module is used for carrying out parallel-to-serial conversion on the decoded data, adding a frame header according to a data frame format after setting processing, forming a transmission frame with a fixed length and outputting the transmission frame to the PS end.

As an improvement of the tester, when the decoding module decodes, if the decoding is correct, the decoding frame is counted, the good frame count is displayed on the upper computer in real time, if the decoding is incorrect, the bad frame count is displayed on the upper computer in real time, and if the decoding is correct, the data frame type is the remote control receiving count, the remote control frame is counted.

As an improvement of the tester, the demodulation module is also used for outputting telemetry quantity reflecting the current signal quality to the PS end and displaying the telemetry quantity in real time by an upper computer, wherein the telemetry quantity comprises frequency offset telemetry, a numerical value of locking judgment, demodulation locking indication, AGC gain and Eb/N0.

As an improvement of the above tester, the FPGA platform performs radio frequency integrated platform configuration, including:

when the tester is powered on, the FPGA platform firstly completes one-time configuration of the radio frequency integrated platform;

In the working process of the tester, the FPGA platform receives the dynamic parameter configuration sent by the upper computer and dynamically configures the parameters of the radio frequency integrated platform.

The main configuration parameters comprise modulation/demodulation mode, frequency sweep range, frequency sweep rate, frequency sweep zeroing/start-stop, frequency offset setting and AD9364 insertion loss setting.

As an improvement of the tester, the upper computer supports reading file import data and field configuration data.

As an improvement of the above-mentioned tester, the tester supports selecting different baseband data sources, and supports transmitting data simultaneously by a single baseband data source or multiple baseband data sources.

As an improvement of the tester, the upper computer is communicated with the FPGA platform through an Ethernet interface, and the FPGA platform and the radio frequency integrated platform are connected through an interconnection interface between FMC high-speed boards.

Compared with the prior art, the invention has the advantages that:

1. The invention has high integration level and strong flexibility. The method can support the reading of file (single file or multiple files) import data and field configuration data, has a real-time storage function, has a mode switching function, can perform mode switching (multiple modulation and demodulation modes and multiple data rates) through manual configuration, has a function of displaying telemetry description of each state of a current link in real time, has a function of dynamically configuring parameters (frequency sweeping range, frequency sweeping speed, frequency offset setting, frequency sweeping return to zero/start-stop and the like), has a function of setting signal output power in real time, has power stepping of 0.25dB, has an attenuation range of 0-89.75 dB, and is default to be-40 dB when the system is started.

2. The invention has strong portability and high reusability, and the IP of the functional module can meet the task demands of subsequent models only by simple increase, decrease or change, thereby greatly reducing the design difficulty and time cost of developers.

3. The hardware adopted by the invention is based on the ZYNQ+AD9364 platform, and has the advantages of low cost, small volume, light weight and convenience for carrying and transporting in the processes of butt joint test and the like.

Drawings

FIG. 1 is a block diagram showing the system structure of a ground comprehensive tester for measurement and control communication;

FIG. 2 shows the definition of the AOS frame format of the measurement and control communication ground comprehensive tester;

FIG. 3 shows an upper computer operation interface of the measurement and control communication ground comprehensive tester;

FIG. 4 is a flow chart of the software operation of the test and control communication ground comprehensive tester.

Detailed Description

The technical scheme of the invention is described in detail below with reference to the accompanying drawings.

The invention provides a ground comprehensive tester for measurement and control communication, which can simulate the single machine characteristic and behavior of communication with a communication subsystem in an inter-satellite link, can simulate the channel characteristic of a radio frequency link, and can be used for universal detection of measurement and control communication type tasks. The tester is connected with the communication subsystem in a radio frequency wired mode, and wireless connection comprising an antenna is not involved.

The ground comprehensive tester comprises a FPGA platform, an upper computer and a radio frequency integrated platform, wherein the FPGA platform is used for completing functions of baseband data stream processing (frame synchronization, encoding and decoding, scrambling and descrambling, framing and de-framing), modulation and demodulation, ethernet communication, radio frequency integrated platform configuration, link state monitoring and the like, the upper computer is used for completing functions of modulation and demodulation parameter configuration, output signal power adjustment, baseband data source sending and receiving storage, ethernet communication, system state real-time monitoring and displaying and the like, and the radio frequency integrated platform is used for completing functions of up/down frequency conversion, filtering, low Noise Amplification (LNA), automatic Gain Control (AGC) and the like.

At the transmitting end, the FPGA receives data sent by the upper computer, the data transmission module DMA0 takes out the data in the ARM of the PS end, the data is buffered through the first-in first-out buffer FIFO 0, continuous data is output, and baseband data output by the FIFO 0 is output to the modulating end for processing. The baseband data firstly pass through a frame synchronization module, a frame reorganization module, a coding module and a scrambling module to finish the processing of a data link layer.

The frame synchronization module receives the data stream (in bytes) sent by the ARM end, and completes the fixed frame length frame synchronization of the frame header of the intra-frame shielding, wherein the frame header is 1ACFFC D, and the frame length is 1024B. Consecutive frames starting with the frame header are output.

The reorganization frame module identifies the VCID of the current frame according to the frame format, counts the current frame, and fills the frame count into the corresponding position in the current frame. The recombined frame outputs a frame enabling signal, a mark to be coded and the like through parallel-serial conversion of 8 bits to 1 bit. And receiving a sequence number corresponding to the VCID identification sent to the ARM end by the upper computer, returning the frame count of the type of frames to GPIO (General Purpose Input/Output general input/Output) 18 of the upper computer by the ARM end, and displaying the frames in real time by the upper computer.

The encoding module completes encoding the reorganized frame.

The scrambling module scrambles the encoded data in units of frames, and the frame format is scrambled except for the synchronous head.

The scrambled data are sent to a modulation module, the modulation module is divided into a task mode and a non-task mode, and the modulation module completes modulation algorithms of different modulation modes and different data rates under corresponding modes according to a modulation mode instruction sent by an upper computer.

At the receiving end, the FPGA receives a digital intermediate frequency signal received by a data interface at the Rx end of the radio frequency integrated platform, and the signal is demodulated by a demodulation module. The demodulation module is divided into a task mode and a non-task mode, and the demodulation module completes demodulation algorithms of different modulation modes and different data rates under corresponding modes according to demodulation mode instructions sent by the upper computer. And outputs telemetry quantities reflecting the current signal quality, such as Eb/N0, AGC gain, frequency offset telemetry, etc.

The demodulated baseband data is processed by a frame synchronization module, a descrambling module, a pre-decoding processing module, a decoding module and a post-decoding processing module to finish the processing of a data link layer.

The frame synchronization module receives remote control log likelihood ratio soft decision information (remote control data stream) output by the demodulation module, performs fixed length frame synchronization on the remote control data stream, and gives out a frame synchronization identifier. Different frame synchronization parameters (fault-tolerant bit number, check times and synchronization out-of-step times) are configured according to the demodulation mode of the ARM end switching sent by the upper computer. Besides, the frame synchronization module can adapt to the condition that the remote control data stream is inverted in I/Q, and carries out phase ambiguity correction on the frames with phase ambiguity.

The descrambling module receives the data transmission frame sent by the frame synchronization module and descrambles the original scrambling region.

The effective frame after descrambling is removed by the pre-decoding processing module, the frame head of 32 bits is changed into a frame with the length of 8160, and the frame is processed and then is transmitted to the decoding module through serial-parallel conversion.

The decoding module decodes according to the decoding rule, outputs the decoded data, and gives out the state indication of the decoding result, namely idle state, correct decoding and error decoding.

The decoding post-processing module performs parallel-to-serial conversion on the decoded data, and adds a 32-bit frame header according to a data frame format after processing to form a 8192-bit transmission frame. The transmission frame is sent to the FIFO 1 for buffering after serial-parallel conversion of 1bit to 8bit, then sent to the ARM of the PS end through the DMA 1 of the data transmission module, and finally the upper computer receives the data for completing storage. The decoding post-processing module gives out state information such as good frame count, bad frame count, and remote control receiving frame count.

And the FPGA sends various working state information of the current link to the GPIO of the ARM end, and finally the information is displayed on the upper computer.

The FPGA completes the configuration, transmission and reception of the AD 9364. When the equipment is powered on, a state machine in the FPGA firstly completes one-time configuration of the AD9364, and configuration information is stored in coe files in the ROM. coe the file contains configuration information for all registers of the AD9364 and actions (read, write, read-back verification, monitoring) of the state machine. Besides the one-time configuration of power on, the FPGA supports receiving the parameter of 'AD 9364 insertion loss setting' sent by the upper computer, and completes the dynamic configuration of the power of the transmitting signal. According to the AD9364 interface and the characteristics, the time sequence control of the transmitting end/receiving end/SPI interface is completed, and the signal transmission and the signal reception are completed.

The upper computer supports dynamic parameter configuration, and main configuration parameters comprise a modulation/demodulation mode, a frequency sweep range, a frequency sweep rate, frequency sweep zeroing/starting and stopping, frequency offset setting, AD9364 insertion loss setting and the like. The parameters are transmitted to the FPGA through GPIO of ARM, and the FPGA completes corresponding configuration according to a pre-agreed protocol.

The upper computer supports reading file import data and field configuration data, and various data sources can be sent independently or simultaneously.

The host computer supports processing, detecting, storing and displaying of the transmitted/received data VCID (virtual channel identifier) distinction. The upper computer supports real-time display explanation of state telemetry, and monitors the state of the current link.

The connection relation among all the constituent modules of the measurement and control communication ground comprehensive tester is that the upper computer communicates with the FPGA platform through an Ethernet interface, and transmits the baseband data of remote control/remote measurement, parameter configuration and monitoring system state. The FPGA platform and the radio frequency integrated platform are connected through an interconnection interface between FMC (FPGAMezzanine Card) high-speed boards.

The host computer may be any PC or laptop that includes an ethernet interface.

The FPGA platform adopts the solution of an XILINX Zynq7000 SOC chip XC7Z045, and adopts ARM+FPGA SOC technology to integrate dual-core ARM Cortex-A9 and FPGA programmable logic on one chip. The entire FPGA includes the PS portion of ARM and the conventional programmable logic PL portion.

The system comprises a FPGA platform, a radio frequency integrated platform, a low-noise amplification, quadrature down-conversion, filtering and automatic gain control, wherein the radio frequency integrated platform is used for receiving a baseband data stream output by the FPGA platform, completing filtering, quadrature up-conversion and generating a radio frequency analog signal, and also used for completing low-noise amplification, quadrature down-conversion, filtering and automatic gain control after receiving the radio frequency signal, generating a digital intermediate frequency signal and outputting the digital intermediate frequency signal to the FPGA platform.

The main chip of the radio frequency integrated platform is AD9364, and the AD9364 is a Radio Frequency (RF) AGILE TRANSCEIVER agile transceiver with high performance and high integration level. The device integrates an RF front end with a flexible mixed signal baseband section, integrating a frequency synthesizer. The AD9364 operating frequency range is 70MHz to 6.0GHz. The supported channel bandwidth ranges from below 200kHz to 56MHz.

The technical scheme of the invention is described in detail below with reference to the accompanying drawings and examples.

Fig. 1 shows a system structure block diagram of a measurement and control communication ground comprehensive tester, which shows the connection relation between each component module and the connection relation between each functional module.

In fig. 1, the FPGA platform includes a PS side and a PL side. The ARM at the PS end directly has hardware to support the AXI interface, while the PL end needs to use logic to realize the corresponding AXI protocol. Xilinx provides ready-made IP such as AXI-DMA in the Vivado development environment, AXI-GPIO realizes the corresponding interface, and when in use, the Xilinx can be directly added from the IP list of the Vivado to realize the corresponding function. The DMA, FIFO and GPIO in the figure are IP cores directly called by the PL side, but the interconnection of the PS side and the PL side is realized through the AXI interface.

At the transmitting end, the upper computer firstly configures necessary parameters and selects a baseband data source to be transmitted.

(1) In order to detect the frequency offset adaptive capacity received by the on-board equipment, the output frequency of the ground comprehensive tester is required to be adjustable, and the ideal output frequency is determined, so that the output frequency can be changed into the output frequency offset.

The parameters configured by the upper computer comprise frequency offset setting and frequency offset after calibration.

And when the value of the pre-calibration frequency offset changes each time, the upper computer needs to store the value in a parameter configuration file, loads the pre-calibration frequency offset when the power is started each time, displays the value in a pre-calibration frequency offset value input box, and sets the value to 0 if the value is not detected in the parameter configuration file.

And (3) starting the upper computer every time, and setting the default value of frequency offset to be 0. And starting or calculating the 'frequency offset after calibration' = 'frequency offset after calibration' - 'frequency offset before calibration' by the upper computer every time the 'frequency offset setting' value changes. The frequency offset after calibration is a 16-bit signed integer, the value is transmitted to the ARM end of the ZYNQ development board, and the ARM end receives the value and then transmits the value to a modulation module at the PL end through the GPIO 13.

(2) The on-board equipment needs to be able to accommodate the rate of change of frequency offset of a certain capacity (the source of the rate of change of frequency offset is the relative motion between two stars and the change of the reference source), and the ground integrated tester needs to provide such test capability.

The parameters configured by the upper computer comprise a frequency sweep rate, a frequency sweep range, frequency sweep zeroing and frequency sweep start-stop.

The frequency sweep range is the effective range of the numerical value of 0-10 kHz, 1Hz step by step, 16bit, unsigned integer.

Sweep rate: numerical value effective range: 0-100 Hz, stepping by 0.1Hz,10bit, unsigned integer.

Sweep frequency is reset to 1bit, and an upper computer interface is represented by a control similar to a switch. If 0, the normal frequency sweep is indicated, and if 1, the frequency offset is returned to 0, and then the frequency sweep is stopped.

The sweep frequency is started and stopped by 1bit, and the upper computer interface is represented by a control similar to a switch. If the frequency is 1, the normal frequency sweep is indicated, and if the frequency is 0, the frequency sweep is stopped, and the frequency offset is fixed.

The current frequency offset is 16 bits, and the number of symbol integer is present. The method comprises the following steps of setting fixed frequency offset and current frequency sweep frequency offset.

The ARM end transmits the sweep frequency parameters to a modulation module of the PL end through GPIO 22-GPIO 25, and simultaneously transmits the current frequency offset to GPIO 21, and the current frequency offset is transmitted to the upper computer for real-time display by the ARM.

(3) The measurement and control communication ground comprehensive tester supports selection of a baseband data source and supports simultaneous transmission of a single data source or a plurality of data sources.

Assuming that the selected data sources are A1, A2 and A3, the transmitting end transmits data in the format of A1 st frame, A2 st frame, A3 st frame, A1 st frame, A2 nd frame and A3 nd frame.

Table 1 gives an example of a specific baseband data source type, which can be increased or decreased and changed according to project requirements.

Table 1 description of transmitting-side baseband data source types

(4) The measurement and control communication ground comprehensive tester supports manual adjustment of output signal power.

The parameters of the upper computer configuration comprise AD9364 insertion loss setting.

The AD9364 configuration insertion loss register address is 0x74/0x73. The combination of 0x74[0] (TxAtten [8 ]) and 0x73[7:0] (TxAtten [7:0 ]) is a 9bit value TxAtten [8:0]. The upper computer outputs the 9bit value to the ARM end through the GPIO 20, and the ARM end transmits the value to the AD9364 configuration module of the PL end. After detecting that the spin_done signal after the configuration of the boot-up one-time ROM is pulled high, the state machine of the AD9364 configuration module detects the change of the GPIO 20 value, and if the change is detected, the configuration insertion loss is started. The configuration flow is that AD9364 register 0x14 is written into 0x05, AD9364 register 0x74 is written into GPIO 20[8], AD9364 register 0x73 is written into GPIO 20[7:0], and AD9364 register 0x14 is written into 0x20.

The legal range of the AD9364 insertion loss value is 0-359 (decimit), the corresponding attenuation amount is-Tx Atten [8:0]/4 (dB), and the attenuation range is 0-89.75 dB. For example TxAtten [8:0] = 359, indicating an internal attenuation of AD9364 of-89.75 dB. The insertion loss defaults to-40 dB when the comprehensive tester is started, and the numerical value when the program exits is used as the default value of the next starting.

(5) And setting a transmitting end modulation mode, supporting different modulation modes and data rates, and manually switching the working mode. An example of a specific modulation scheme is given in table 2, which can be increased or decreased and changed according to project requirements.

TABLE 2 transmitting end modulation modes

Mode code	Modulation scheme	Rate of speed	Task/non-task mode
				0	QPSK	40Mbps	Task mode
1	QPSK	20Mbps	Task mode
				2	QPSK	2.5Mbps	Task mode
3	SingleTone	——	——
				4	BPSK	16Kbps	Non-task mode
5	BPSK	125bps	Non-task mode

And the transmitting end and the baseband data source output by the upper computer finish buffering through DMA 0 and FIFO 0 of the ARM end, so that the data continuity is ensured. And outputting the baseband data output by the FIFO 0 to a modulation end for processing. The baseband data firstly pass through a frame synchronization module, a frame reorganization module, a coding module and a scrambling module to finish the processing of a data link layer.

The frame synchronization module receives the data stream sent by the ARM end, the bit width is 8 bits, and the frame length is 1024B. Because the frame length is fixed and the base band data has no error code, the frame synchronization module completes the frame synchronization of the fixed frame length of the frame header of the intra-frame mask in byte units, namely after the frame header 1ACFFC D is detected, the frame header is not searched any more in the frame, and the frame header is continuously detected at the frame header position of the next frame.

The baseband data source sent by the upper computer accords with an AOS frame format, and the AOS frame format is shown in figure 2.

And the frame count in the AOS frame of the baseband data source sent by the upper computer is filled with all 0, and after the frame synchronization frame is received by the frame reorganization module, the VCID is identified and the frame of the VCID is counted. And filling the frame count into the corresponding position of the current frame type to complete the frame reorganization function. The reassembled frame module also monitors the frame count of the corresponding channel (VCID). For example, when the GPIO 19 is detected to be changed and the changed value is 4'b0001, the current baseband data source type is data 1 (as shown in table 1), the frame count with VCID of 6' b000101 is returned to the GPIO 18, and the count value of the current type frame is displayed in real time by the ARM terminal to the upper computer. Thus, by comparing the frame type and frame count sent by the ground comprehensive tester with the frame type and frame count received by the communication subsystem, whether the communication subsystem has frame loss behavior can be judged.

The encoding module completes encoding of the LDPC (8160,7136) of the reassembled frame.

The scrambling module scrambles the encoded information bits and check bits in units of frames according to a scrambling polynomial, and scrambles all the information bits except for the synchronization header in the AOS frame format.

The modulation module receives a modulation mode control instruction GPIO 3 of the upper computer and completes the modulation function of the scrambled data stream. The modulation module receives parameters, namely, frequency offset (GPIO 13), frequency sweep range (GPIO 22), frequency sweep rate (GPIO 23), frequency sweep return to zero (GPIO 24) and frequency sweep start-stop (GPIO 25) after calibration, and then frequency offset and frequency sweep setting of signals are completed.

The I/Q baseband data output by the modulation module is sent to a sending module of the AD9364, and the AD9364 completes the transmission of radio frequency signals after filtering and quadrature up-conversion.

And the upper computer sets a demodulation mode of the receiving end, supports different demodulation modes and data rates, and can manually switch the working modes. Table 3 shows a specific example of the increase, decrease and change of the demodulation mode according to the project requirement.

TABLE 3 demodulation mode at receiver

The radio frequency signal is output to the Rx module of AD9364 after LNA, quadrature down-conversion, filtering and AGC of AD 9364.

The digital intermediate frequency signal is sent to a demodulation module, and the demodulation function is completed according to a demodulation mode instruction GPIO 2 sent by the upper computer. The demodulation module outputs telemetry quantity reflecting the current signal quality, including frequency offset telemetry, a value of locking judgment, demodulation locking indication, AGC gain and Eb/N0, which are respectively sent to GPIO 4, GPIO 5, GPIO 6, GPIO 7 and GPIO 8 of ARM, and then sent to the upper computer for real-time display.

The frame synchronization module receives the remote control log likelihood ratio soft decision information output by the demodulation module, and carries out fixed length frame synchronization on the remote control data stream, wherein the frame length is 8192.

In order to obtain better performance, the search frame head of the frame synchronization module is 1ACFFC D with 32 bits, and a frame protection mechanism is set. The frame protection mechanism is realized by a state machine and is divided into a search state S0, a check state S1 and a synchronous state S2. The frame synchronous working state is sent to GPIO 14 and sent to the upper computer for real-time display through ARM.

The searching state S0 is that the most significant bit of the remote control log likelihood information is shifted and registered in a 32bit shift register, and when the 32bit shift register detects that a frame head exists, the searching state is entered;

In the checking state S1, the frame head is continuously detected N times, and the upper frame and the lower frame are consistent (the phase and the I/Q relation are consistent), the same gait is entered, and otherwise, the searching state is returned. I.e., the n+1 frames are co-detected in the search state + the check state.

And S2, if the synchronous state is in continuous M times of desynchronization, returning to the searching state, otherwise, keeping the synchronous state. I.e. M times of synchronous acknowledgements.

Because the data rate is different from the demodulation mode, the frame synchronization module receives the demodulation mode control (GPIO 2), and configures different frame synchronization parameters (fault-tolerant bit number, check frequency and synchronization out-of-step frequency) according to the current demodulation mode.

Since BPSK (Binary PHASE SHIFT KEYING Binary phase shift keying) and QPSK (Quadrature PHASE SHIFT KEYING Quadrature phase shift keying) have phase ambiguity at the time of demodulation, BPSK has 2 kinds of ambiguous phases in total and QPSK has 4 kinds of ambiguous phases in total, the frame synchronization module performs phase ambiguity correction for a frame where phase ambiguity occurs. In addition, the frame synchronization module can adapt to the condition that the remote control data stream is inverted in I/Q.

And the descrambling module receives the transmission frame sent by the frame synchronization module and descrambles the original scrambling region.

The pre-decoding processing module removes 32bit frame heads from the descrambled frame to be changed into a frame with the length of 8160, removes 2 clk data at the tail of the frame with the length of 8160, adds 180 at the frame head, and finally forms the frame with the frame length of 8176. To adapt to the decoding module interface, 7 paths of parallel conversion needs to be performed on the frame with 8176 length, so as to obtain 7 paths of parallel data to be decoded with 1168 length.

The decoding module decodes according to the decoding rule of LDPC (8160,7136), outputs decoded data, and gives out state indication of decoding result, namely idle state, correct decoding and decoding error.

The decoding post-processing module performs parallel-serial conversion (7 bit to 1 bit) on the parallel 7-path decoded data output by the LDPC decoding module, and the frame length after the parallel-serial conversion is 8176bit. The 18bit 0 at the beginning of 8176bit frame is removed and a 2bit 0 is added at the end of the frame. And finally, adding a 32-bit frame header according to a data frame format to form a 8192-bit transmission frame. The transmission frame is sent to the FIFO 1 for buffering after serial-parallel conversion of 1bit to 8bit, then sent to the ARM of the PS end through the DMA 1, and finally the upper computer receives the data to finish real-time storage. If the decoding is correct, the frame which is decoded correctly is counted and sent to the GPIO 15, the frame which is decoded incorrectly is displayed in real time on the upper computer, if the decoding is incorrect, the frame which is decoded incorrectly is counted and sent to the GPIO 16, the bad frame count is displayed in real time on the upper computer, and if the decoding is correct and the data frame type is the remote control receiving count of the remote control of the transmission, the frame which is transmitted in the remote control of the transmission is counted and sent to the GPIO 17.

Table 4 shows the GPIO meanings of the measurement and control communication ground comprehensive tester of the invention, which is 26 GPIOs in total. The GPIO sequence numbers correspond one-to-one to the GPIO sequence numbers in fig. 1.

TABLE 4GPIO meanings of description

Fig. 3 shows an operation interface of an upper computer of the measurement and control communication ground comprehensive tester, which comprises a device starting function, an instruction and parameter configuration function, a baseband data source selecting and transmitting function, a baseband data real-time storage function, a system state real-time monitoring function and an interpretation function, wherein the upper computer displays in real time every about 1 s.

Clicking the upper computer interface for software start, namely initiating TCP/IP connection to the ARM end, changing an indicator light in the interface into a green light if the connection is successful, and keeping the indicator light as a red light if the connection is failed. Clicking the upper computer interface to send data can observe the change of the telemetry amount, so that the device is successfully started.

FIG. 4 is a flow chart showing the software operation of the measurement and control communication ground comprehensive tester of the invention. After the equipment is started, waiting for 1min, starting the upper computer software, and after the equipment is successfully started, completing the function and performance test of the single-machine subsystem according to the requirement of the single-machine subsystem and the test flow. After the test is completed, the connection is disconnected, and the test is ended.

Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and are not limiting. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the appended claims.

Claims

1. A ground comprehensive tester for measurement and control communication is characterized by comprising an upper computer, an FPGA platform and a radio frequency integrated platform, wherein,

The radio frequency integrated platform is used for receiving a baseband data stream output by the FPGA platform, finishing filtering, quadrature up-conversion and generating a radio frequency analog signal, and also used for finishing low-noise amplification, quadrature down-conversion, filtering and automatic gain control after receiving the radio frequency signal, generating a digital intermediate frequency signal and outputting the digital intermediate frequency signal to the FPGA platform;

the FPGA platform comprises a PS end and a PL end;

The PS terminal comprises data transmission modules DMA0 and DMA 1, buffer memory FIFO 0 and FIFO 1 and GPIO, wherein,

The data transmission module DMA0 is used for receiving a baseband data stream from the upper computer and outputting the baseband data stream to the cache FIFO 0;

the buffer FIFO 0 is configured to buffer the baseband data stream received by the data transmission module DMA 0;

the PL end comprises a transmit subsystem and a receive subsystem, wherein,

The receiving terminal system is used for receiving the digital intermediate frequency signal sent by the radio frequency integrated platform, demodulating, synchronizing frames, descrambling and decoding the digital intermediate frequency signal and outputting the digital intermediate frequency signal to the cache FIFO 1;

The transmitting terminal system includes:

The coding module is used for finishing coding the recombined frame and outputting the coded recombined frame to the scrambling module, wherein a coding and decoding mode supports LDPC (8160,7136) codes;

The modulation module is used for completing modulation of different modulation modes and different data rates under corresponding modes for the scrambled data according to the modulation mode instruction sent by the upper computer, wherein the modulation and demodulation mode supports BPSK and QPSK, and the communication rate coverage range supports from 125bps to 40Mbps;

The modulation module is also used for acquiring calibrated frequency offset, frequency sweep range, frequency sweep rate, frequency sweep zeroing and frequency sweep start-stop parameters from the PS end to finish frequency offset and frequency sweep setting of data;

The receiving terminal system includes:

The system comprises a remote control log likelihood ratio soft decision information, a frame synchronization module, a descrambling module, a phase ambiguity correction module and a phase ambiguity correction module, wherein the remote control log likelihood ratio soft decision information is used for providing a demodulation mode for a host computer;

a decoding module for decoding the data according to the decoding rule and outputting the decoded data and the state indication of the decoding result to the post-decoding processing module, and

The post-decoding processing module is used for carrying out parallel-to-serial conversion on decoded data, adding frame heads according to a data frame format after setting processing, forming a transmission frame with a fixed length and outputting the transmission frame to the PS end;

The upper computer supports reading file import data and field configuration data.

2. The measurement and control communication ground comprehensive tester according to claim 1, wherein,

When the decoding module decodes, if the decoding is correct, the frame with correct decoding is counted, the frame with correct decoding is displayed on the upper computer in real time, if the decoding is wrong, the frame with wrong decoding is counted, the bad frame is displayed on the upper computer in real time, and if the decoding is correct, the frame with remote control is counted when the data frame type is the remote control receiving count.

3. The measurement and control communication ground comprehensive tester according to claim 1, wherein,

The demodulation module is also used for outputting telemetry quantity reflecting the current signal quality to the PS end and displaying the telemetry quantity in real time by an upper computer, wherein the telemetry quantity comprises frequency offset telemetry, a numerical value of locking judgment, demodulation locking indication, AGC gain and Eb/N0.

4. The measurement and control communication ground comprehensive tester according to claim 1, wherein the FPGA platform performs radio frequency integrated platform configuration, comprising:

In the working process of the tester, the FPGA platform receives dynamic parameter configuration sent by the upper computer and dynamically configures parameters of the radio frequency integrated platform;

5. The measurement and control communication ground integrated tester according to claim 1, wherein the tester supports selecting different baseband data sources, and supports transmitting data simultaneously by a single baseband data source or multiple baseband data sources.

6. The measurement and control communication ground comprehensive tester according to claim 1, wherein,

The upper computer is communicated with the FPGA platform through an Ethernet interface, and the FPGA platform and the radio frequency integrated platform are connected through an interconnection interface between FMC high-speed boards.