CN117560003A

CN117560003A - Comparator offset calibration device and analog-to-digital converter

Info

Publication number: CN117560003A
Application number: CN202311661672.2A
Authority: CN
Inventors: 丁泽莹; 吴新宇; 李建忠; 何蔼; 王治安; 李彬鸿; 王云; 叶甜春
Original assignee: Guangdong Greater Bay Area Institute of Integrated Circuit and System
Current assignee: Guangdong Greater Bay Area Institute of Integrated Circuit and System
Priority date: 2023-12-05
Filing date: 2023-12-05
Publication date: 2024-02-13

Abstract

A comparator offset calibration device and an analog-to-digital converter. The comparator offset calibration device calibrates a logic control unit, a calibration DAC unit and a comparator control unit; wherein: the calibration logic control unit is connected to the comparator to be calibrated, and is used to generate when the comparator to be calibrated is out of tune. Calibration code and storage; the calibration DAC unit is connected to the logic control unit, used to obtain the calibration code generated by the logic control unit, and generate a calibration signal based on the calibration code, using the calibration signal to The comparator to be calibrated is calibrated; the comparator control unit is connected to the calibration logic control unit and is used to detect in real time whether the preset calibration end condition is met, and when the preset calibration end condition is met, generate a detection result signal to turn off the comparator calibration device. Using the above solution, calibration power consumption can be reduced.

Description

Comparator offset calibration device and analog-to-digital converter

Technical Field

The invention relates to the technical field of analog integrated circuits, in particular to a comparator offset calibration device and an analog-to-digital converter.

Background

Comparators are an important component of Analog-to-Digital Converter (ADC) converters and are one of the more widely used devices in electronic systems. The performance of the comparator, in particular the power consumption, has a crucial influence on the power consumption of the entire analog-to-digital converter.

From the power consumption point of view, comparators can be classified into static comparators and dynamic comparators, and the main difference between them is that: the static comparator consumes a certain static power consumption, while the static power consumption of the dynamic comparator is zero, and only the dynamic power consumption is generated.

A dynamic differential comparator belongs to a relatively common type of dynamic comparator. The dynamic differential comparator is provided with a differential input end and a differential output end, differential signals can be input through the differential input end, the dynamic differential comparator can compare voltages among the input differential signals, and a differential comparison result is output through the differential output end.

In the actual production process, due to the problems of process, manufacture and the like, the two differential input ends of the dynamic differential comparator may have different degrees of deviation, so that the input differential signals cannot be compared under the same condition, namely the dynamic differential comparator has offset, and in order to ensure the performance of the dynamic differential comparator, the offset of the dynamic differential comparator needs to be calibrated.

However, the existing scheme for calibrating the dynamic differential comparator offset has higher power consumption, and is difficult to meet the requirement of power consumption.

Disclosure of Invention

The invention aims to solve the problems that: the calibration power consumption is reduced.

In order to solve the above problems, an embodiment of the present invention provides a comparator offset calibration device for offset calibration of a dynamic differential comparator; the comparator offset calibration device includes: the calibration logic control unit, the calibration DAC unit and the comparator control unit; wherein: the calibration logic control unit is connected with the comparator to be calibrated and is used for generating and storing a calibration code when the comparator to be calibrated is out of order;

the calibration DAC unit is connected with the logic control unit and is used for acquiring the calibration code generated by the logic control unit, generating a calibration signal based on the calibration code and calibrating the comparator to be calibrated by using the calibration signal;

the comparator control unit is connected with the calibration logic control unit and is used for detecting whether a preset calibration ending condition is met in real time and generating a detection result signal when the preset calibration ending condition is met so as to close the comparator calibration device.

The embodiment of the invention also provides an analog-to-digital converter, which comprises the comparator calibration device of any one of the above.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

by adopting the scheme of the invention, the comparator control unit can detect whether the calibration is finished in real time, and further can close the comparator calibration device when the preset calibration ending condition is met, so that the power consumption of the comparator calibration device can be reduced.

Drawings

FIG. 1 is a schematic diagram of a successive approximation type analog-to-digital converter;

FIG. 2 is a schematic diagram of a comparator offset calibration device according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another offset calibration device for a comparator according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a calibration code generating circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a path selection circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a calibration code memory circuit according to an embodiment of the invention;

FIG. 7 is a schematic diagram of a comparator control unit according to an embodiment of the present invention;

FIG. 8 is a timing diagram of a comparator to be calibrated according to an embodiment of the present invention after calibration;

FIG. 9 is a schematic diagram of a calibration initiation circuit according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a memory clock generation circuit according to an embodiment of the present invention;

FIG. 11 is a timing diagram of a first clock signal and a calibration code memory clock signal according to an embodiment of the invention;

FIG. 12 is a schematic diagram of a switch control module according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a resistor unit according to an embodiment of the present invention;

FIG. 14 is a schematic diagram of a resistor DAC according to an embodiment of the present invention;

FIG. 15 is a schematic diagram of a p-way resistor DAC subunit according to an embodiment of the present invention;

fig. 16 is a schematic circuit diagram of a dynamic differential comparator according to an embodiment of the present invention.

Detailed Description

The analog-to-digital converter is used for converting the continuous analog signal into a binary digital signal. With decades of developments, the application fields of ADCs are becoming more and more widespread, mainly including wireless communication, audio processing, medical facilities, etc. Meanwhile, there is an increasing demand for the performance of ADCs, which are gradually advancing toward high speed, high resolution and low power consumption.

In the ADC circuit, a dynamic differential comparator is required to convert an analog signal into a digital signal. The dynamic differential comparator is used as a key structure of the ADC and is provided with two differential input ends, and the comparator can convert differential signals input by the two differential input ends into digital signals, so that the performance of the dynamic differential comparator can directly influence the overall performance of the ADC.

Fig. 1 is a schematic diagram of a successive approximation analog-to-digital converter (SAR ADC). Referring to fig. 1, the SAR ADC may include: a digital-to-analog conversion circuit 11, a comparator 12, a data storage circuit 13, and a sampling circuit 14.

The externally input differential signal is sampled by the sampling circuit 14 and then output to the comparator 12 via the digital-to-analog conversion circuit 11. The comparator 12 has differential inputs for inputting differential signals inp and inn. The comparator 12 may compare the differential signals inp and inn and output a differential comparison result. The differential comparison result is stored in the data storage circuit 13. The differential input end of the digital-to-analog conversion circuit 11 is coupled to the data storage circuit 13, and is adapted to read the differential comparison result from the data storage circuit 13, perform digital-to-analog conversion, and superimpose the converted signals with differential signals inp and inn, respectively, and compare the superimposed input signals again by the comparator 12. The above-described signal processing procedure is repeated, so that the differential signals input from the comparator 12 can be made close to each other.

However, in the actual production process, due to the problems of process, manufacturing and the like, the two differential input ends of the dynamic differential comparator have different degrees of deviation, so that the input differential signals cannot be compared under the same condition, namely, the dynamic differential comparator has offset. To guarantee the performance of the ADC, the offset of the dynamic differential comparator needs to be calibrated.

The existing scheme for calibrating the offset of the dynamic differential comparator is to calibrate the differential input signal of the dynamic differential comparator after the dynamic differential comparator is powered on. When the differential input signal of the dynamic differential comparator changes, calibration is needed, so that the differential input signal needs to be calibrated continuously after the dynamic differential comparator is powered on, and the power consumption required by the calibration is high.

In order to solve the problem, the invention provides a comparator offset calibration device, which is provided with a comparator control unit, wherein the comparator control unit can detect whether a preset calibration ending condition is met in real time, and a detection result signal is generated to close the comparator calibration device once the preset calibration ending condition is met. At this time, the comparator offset calibration device can end calibration in advance, so that the power consumption required for calibration can be reduced.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 2, an embodiment of the present invention provides a comparator offset calibration device 20 for offset calibration of a dynamic differential comparator. Specifically, the comparator offset calibration device 20 includes: a calibration logic control unit 21, a calibration DAC unit 22, and a comparator control unit 23. Wherein:

the calibration logic control unit 21 is connected with the comparator 10 to be calibrated, and is used for generating and storing a calibration code when the comparator 10 to be calibrated is out of order;

the calibration DAC unit 22 is connected to the logic control unit 21, and is configured to obtain a calibration code generated by the logic control unit, generate a calibration signal based on the calibration code, and calibrate the comparator 10 to be calibrated using the calibration signal;

the comparator control unit 23 is connected to the calibration logic control unit 22, and is configured to detect whether a preset calibration end condition is satisfied in real time, and generate a detection result signal to turn off the comparator calibration device 20 when the preset calibration end condition is satisfied.

By providing the comparator control unit 23 it is thus possible to detect in real time whether the calibration is finished during the calibration phase and when the calibration is detected, i.e. the comparator calibration means are turned off, without waiting for all calibration codes to be completely generated, whereby the power consumption can be reduced.

Fig. 3 is a schematic structural diagram of a comparator offset calibration device according to an embodiment of the invention. Referring to fig. 3, the comparator to be calibrated 10 has differential inputs and differential outputs. The differential input end comprises two paths, namely p paths and n paths. The p-way input signal inp of the differential input end and the n-way input signal inn of the differential input end. The signal inp and the signal inn are differential signals.

The differential output terminal also comprises p paths and n paths, wherein the p paths of the differential output terminal generate an output signal outp, and the n paths of the differential output terminal generate an output signal outn. The output signals outp and outn constitute the differential output result of the comparator 10 to be calibrated.

A first switch sw1 is arranged between two paths of the differential input end. When the first switch sw1 is closed, the differential inputs of the comparator to be calibrated 10 are input with a common mode voltage vcm. At this time, the calibration logic control unit 21 may acquire the differential output result of the comparator 10 to be calibrated, and determine whether the comparator 10 to be calibrated is out of order, and calibrate the comparator 10 to be calibrated when the comparator 10 to be calibrated is out of order.

In a specific implementation, the comparator offset calibration device may calibrate the comparator to be calibrated in a sampling phase of the comparator to be calibrated. At this time, the comparator to be calibrated can compare the common mode signal for calibration in the sampling stage, and output the differential output result to the comparator offset calibration device, and the comparator offset calibration device generates the calibration code and the corresponding calibration signal.

The comparator to be calibrated does not need to compare the differential signals which are normally input in the sampling stage, and is in an idle state, so that the comparator offset calibration device is controlled to calibrate the comparator to be calibrated in the sampling stage of the comparator to be calibrated, and the time utilization rate can be improved.

In other embodiments, after the comparator to be calibrated is powered on, one end of idle time is reserved, a calibration code and a corresponding calibration signal are generated, and the comparator to be calibrated is calibrated.

In an embodiment of the present invention, the calibration logic control unit 21 may include: a calibration code generation circuit 211, a path selection circuit 212, and a calibration code storage circuit 213. Wherein:

the calibration code generating circuit 211 is connected to the to-be-calibrated comparator 10, and is configured to generate a pair of candidate calibration code signals based on a differential output result of the to-be-calibrated differential comparator 10 when the to-be-calibrated comparator 10 is out of order; the pair of candidate calibration code signals is used for representing two one-bit candidate calibration codes;

The path selection circuit 212 is connected to the calibration code generation circuit 211, and is configured to determine an offset direction of the comparator 10 to be calibrated using the candidate calibration code signal, and generate a corresponding path selection signal based on the determined offset direction;

the calibration code storage circuit 213 is connected to the path selection circuit 212 and the calibration code generation circuit 211, and is configured to select and store a corresponding one of the candidate calibration code signals by using the path selection signal.

In implementations, the calibration code generation circuit 211 may generate candidate calibration code signals in a variety of ways.

In an embodiment of the present invention, the calibration code generating circuit 211 is configured to continuously obtain K differential output results of the comparator 10 to be calibrated, determine whether the comparator 10 to be calibrated is out of order based on the K differential output results, and generate a pair of candidate calibration code signals when determining that the comparator 10 to be calibrated is out of order; k is more than or equal to 2, and K is an integer.

For example, k=6 may be set, where the comparator to be calibrated continuously performs 6 comparisons, the calibration code generating circuit 211 continuously acquires 6 differential output results of the comparator to be calibrated 10, determines whether the comparator to be calibrated 10 is out of order based on the 6 differential output results, and generates a pair of candidate calibration code signals when determining that the comparator to be calibrated 10 is out of order.

In a specific implementation, the calibration code generating circuit 211 may determine whether the comparator 10 to be calibrated is out of order in various manners based on the K differential output results.

In an embodiment of the present invention, the calibration code generating circuit 211 may determine whether the comparator 10 to be calibrated is out of order for 6 differential output results of any path. For example, for 6 p-way output signals acquired in succession, when two p-way output signals are inconsistent with the remaining four p-way output signals, it is determined that the comparator 10 to be calibrated is not detuned. When only one p-way output signal is inconsistent with the rest p-way output signals or all 6 p-way output signals are consistent, the offset of the comparator 10 to be calibrated is judged.

In a specific implementation, when it is determined that the comparator 10 to be calibrated is out of order, the calibration code generating circuit 211 may generate a pair of candidate calibration code signals based on K differential output results. Specifically, when more than two output signals are high level in one output signal of the differential output end of the comparator to be calibrated 10, a high-level candidate calibration code signal is generated, otherwise, a low-level candidate calibration code signal is generated.

Taking k=6 as an example, when there are two or more p output signals as high level in the 6 p output signals of the differential output terminal of the comparator 10 to be calibrated, the p candidate calibration code signals of high level can be generated. When two or more n output signals are high level in the 6 n output signals of the differential output end of the comparator 10 to be calibrated, n candidate calibration code signals of high level can be generated.

In an embodiment of the present invention, referring to fig. 4, the calibration code generating circuit 211 may include: the first calibration code generation sub-circuit and the second calibration code generation sub-circuit. Wherein:

the first calibration code generation sub-circuit includes: a first inverter 41p, a first logic circuit 42p, a first selector MUXp, and a first shift register 43p connected in this order;

the second calibration code generation sub-circuit includes: a second inverter 41n, a second logic circuit 42n, a second selector MUXn, and a second shift register 43n connected in this order;

the input end of the first inverter 41p is connected with the first output end of the comparator to be calibrated, and the input end of the second inverter 41n is connected with the second output end of the comparator to be calibrated; the first selector MUXp and the second selector MUXn are used for storing the output of the connected inverter in the connected shift register before calibration is not completed;

the first shift register 43p and the second shift register 43n are configured to store K output results of the corresponding inverters and generate a one-bit candidate calibration code signal.

Specifically, referring to fig. 4, the p-way output signal outp of the comparator to be calibrated is inverted by the first inverter 41p and then input to the first logic circuit 42p. The first logic circuit 42p may invert the output of the first inverter 41p to obtain the p-output signal outp and input the p-output signal outp to an input terminal of the first selector MUXp. The other input terminal of the first selector MUXp is grounded. The first selector MUXp may gate the p-way output signal outp and store in the first shift register 43p during the calibration phase. The first selector MUXp may be grounded during the non-calibration phase, so that the first shift register 43p may be turned off.

The n output signals outn of the comparator to be calibrated are inverted by the second inverter 41n and then input to the second logic circuit 42n. The second logic circuit 42n may invert the output of the second inverter 41n to obtain n output signals outn and input the n output signals to an input terminal of the second selector MUXn. The other input terminal of the second selector MUXn is grounded. The second selector MUXn may gate the n-way output signal outn during the calibration phase and stored in the second shift register 43n. The first selector MUXn may be grounded during the non-calibration phase, so that the second shift register 43n may be turned off.

In an implementation, the first logic circuit 42p and the second logic circuit 42n may further receive an enable signal, where the enable signal is used to enable the first logic circuit 42p and the second logic circuit 42n, so that the calibration code generating circuit 211 starts to operate.

In an implementation, the first logic circuit 42p and the second logic circuit 42n may further receive a calibration code reset signal rst, where the calibration code reset signal rst is used to reset the first logic circuit 42p and the second logic circuit 42n to perform logic conversion on the next differential output result again.

In an implementation, the first selector MUXp and the second selector MUXn have selection signal inputs, and the selection signals input by the selection signal inputs are the same.

When the calibration code generating circuit 211 is controlled to generate calibration candidate calibration code signals in the sampling phase of the comparator to be calibrated, the selection signal input terminals of the first selector MUXp and the second selector MUXn may input a sampling clock signal and a detection result signal, so as to input signals and be turned on during calibration and turn off signal input during non-calibration. At the same time, the output of only one of the first and second selectors MUXp and MUXn is stored in the first calibration code memory as the final calibration code.

For example, when the detection result signal is at a low level and the sampling clock signal is at a high level, the first selector MUXp may store the output of the first logic circuit 42p in the first shift register 43p, and the second selector MUXn may store the output of the second logic circuit 42n in the second shift register 43 n.

In an implementation, the first shift register 43p may include a first D flip-flop DFF1 and a second D flip-flop DFF2. The enable (En) end of the first D flip-flop DFF1 and the enable (En) end of the second D flip-flop DFF2 may both be connected to the first enable signal, so that both are turned on and reset at the same time. Wherein the first enable signal may be generated by a third shift register output of the memory clock circuit. By the first enable signal, the first shift register 43p can be caused to generate the p-way candidate calibration code signal cal_p after obtaining K differential output results.

In an implementation, the second shift register 43n may include a third D flip-flop DFF3 and a fourth D flip-flop DFF4. The enable (En) end of the third D flip-flop DFF3 and the enable (En) end of the fourth D flip-flop DFF4 are also connected to the first enable signal, so that the first shift register 43p can generate n paths of candidate calibration code signals cal_n after obtaining K differential output results through the first enable signal.

In a specific implementation, the first shift register 43p and the second shift register 43n may generate high-level candidate calibration code signals when two or more output results of the K output results of the corresponding inverters are high-level, or generate low-level candidate calibration code signals.

Specifically, taking k=6 as an example, when more than two high level signals exist in the 6 p output signals outp, the generated p candidate calibration code signal cal_p is at a high level, otherwise the generated p candidate calibration code signal cal_p is at a low level. When more than two high-level signals exist in the 6 n-way output signals outn, the generated n-way candidate calibration code signals cal_n are high-level, otherwise, the generated n-way candidate calibration code signals cal_n are low-level.

In implementations, the path selection circuit 212 is used to select either the pass p path or the pass n path. Specifically, at power-up initiation, the path selection circuit 212 detects the offset direction of the differential two ends of the comparator to be calibrated. If the voltage of the p-path candidate calibration code signals is higher than the voltage of the n-path candidate calibration code signals in the differential output end of the comparator to be calibrated, the n-path is conducted, and the n-path candidate calibration code signals cal_n are used as first calibration code signals. Conversely, the p-path is turned on, and the p-path candidate calibration code signal cal_p is used as the first calibration code signal.

In one embodiment of the present invention, referring to fig. 5, the path selection circuit 212 may include: a third inverter 51, a nand gate 52 and a second latch 53. The third inverter 51 inverts the n-way candidate calibration code signal cal_n and inputs the n-way candidate calibration code signal cal_n to the nand gate 52 together with the p-way candidate calibration code signal cal_p. The nand gate circuit 52 performs a nand operation on the n-way candidate calibration code signal cal_n and the p-way candidate calibration code signal cal_p, and then latches the nand operation result in the second latch 53.

Specifically, when the n-way candidate calibration code signals cal_n and the p-way candidate calibration code signals cal_p are both at high level, the detection circuit may be started at this time to determine that the comparator is not detuned, so that the comparator detuning calibration device may be turned off.

When the p-path candidate calibration code signal cal_p is high and the n-path candidate calibration code signal cal_n is low, the path selection signal is high, and the n-path is gated. When the p-way candidate calibration code signal cal_p is low and the n-way candidate calibration code signal cal_n is high, the path selection signal is low, and the p-way is gated.

In an implementation, the calibration code storage circuit 213 stores the candidate calibration code signals of the path switched on by the path selection circuit 212, and then sends the stored subsequent calibration code signals as final calibration code signals to the calibration DAC unit 22.

In an embodiment of the present invention, referring to fig. 6, the calibration code storage circuit 213 may include:

an or circuit 61, a third selector MUX3, and a fourth selector MUX4 connected to the calibration code generation circuit;

a first latch 62 connected to the or circuit 61;

a first calibration code register 63 connected to the third selector MUX3 and the first latch 62;

and a second calibration code register 64 connected to the fourth selector MUX4 and the first latch 62;

wherein the first latch 62 is used for enabling the first calibration code register 63 and the second calibration code register 64; the first calibration code register 63 and the second calibration code register 64 are used for storing corresponding candidate calibration code signals based on the path selection signal.

In an embodiment, after the first bit p candidate calibration code signal cal_p and the first bit n candidate calibration code signal cal_n generate output results, the first calibration code register 63 and the second calibration code register 64 are turned on. The third selector MUX3 and the fourth selector MUX4 are respectively used for the p candidate calibration code signal cal_p and the n candidate calibration code signal cal_n.

When the initial p-candidate calibration code signal cal_p is at a high level, the third selector MUX3 selects the n-way candidate calibration code signal cal_n, the first calibration code register 63 stores the n-way candidate calibration code signal cal_n, and at the same time, the fourth selector MUX4 selects the p-candidate calibration code signal cal_p, and the second calibration code register 64 stores the p-candidate calibration code signal cal_p as the first calibration code signal CAL <8:0>.

If the initial n-way candidate calibration code signal cal_n is at a high level, the third selector MUX3 selects the p-way candidate calibration code signal cal_p, the first calibration code register 63 stores the p-way candidate calibration code signal cal_p, and the fourth selector MUX4 selects the n-way candidate calibration code signal cal_n, and the second calibration code register 64 stores the n-way candidate calibration code signal cal_n as the second calibration code signal CAL' <8:0>.

In the existing scheme for calibrating offset of a comparator, the calibration voltage is regulated through a plurality of groups of capacitors and inverters, the calibration voltage is stored on the calibration capacitor in a form of electric charge, and the calibration voltage is output to a comparator calibration tube through the capacitor to regulate offset. The calibration voltage is stored in the form of charge on the calibration capacitor, the stability of the capacitor is poor, and the calibration is easy to lose efficacy due to charge leakage and even larger error is introduced

By adopting the scheme of the invention, the candidate calibration code signals are stored in the corresponding calibration code registers, and the stability of the calibration code registers is higher, so that the calibration code registers can be refreshed at regular time to stably update the calibration code registers, thereby realizing multiple times of calibration, and the stability of the whole calibration is higher.

In a specific implementation, referring to fig. 7, the comparator control unit 23 may include: a detection circuit 231. The detection circuit 231 may be connected to the calibration code generation circuit, and configured to obtain the candidate calibration code signal, and determine whether the preset calibration end condition is satisfied based on the candidate calibration code signal.

By setting the preset calibration ending condition, calibration can be ended in advance without waiting for all calibration codes to be completely generated, so that the power consumption of the offset calibration device of the comparator can be reduced.

In an embodiment of the present invention, the preset calibration end condition includes: in the K differential output results, the times of high level and low level are simultaneously more than preset times. The K differential output results may be K differential output results for generating any pair of candidate calibration code signals.

Taking k=6 as an example, the preset number of times may be two. Specifically, when the second pair of candidate calibration code signals is generated, if 3 p-path candidate calibration code signals in the 6 p-path candidate calibration code signals are at high level, 3 n-path candidate calibration code signals in the 6 n-path candidate calibration code signals are at low level, and 2 n-path candidate calibration code signals in the 6 n-path candidate calibration code signals are at low level, a preset calibration end condition is satisfied, and calibration is judged to be ended. If only 1 p-way candidate calibration code signal in the 6 p-way candidate calibration code signals is high level and 6 n-way candidate calibration code signals in the 6 n-way candidate calibration code signals are low level, the preset calibration ending condition is not met, and the calibration is judged not to be ended.

When it is determined that the calibration is ended, the detection circuit 231 may generate a detection result signal by which other functional units of the comparator offset calibration device are controlled to end the operation.

In an embodiment of the present invention, referring to fig. 7, the comparator control unit 23 may further include: the clock logic 232 and clock generation 233. Wherein:

the clock logic 232 is configured to receive a calibration clock signal and a calibration clock reset signal, and provide a signal at a high level in the calibration clock signal and the calibration clock reset signal to the clock generating circuit 233;

the clock generating circuit 233 is connected to the clock logic circuit 232 and the detecting circuit 231, and is configured to generate the working clock signal of the comparator to be calibrated by using the calibration clock signal, the calibration clock reset signal, the detection result signal and the internal circulation clock signal; the internal circulation clock signal is used for controlling the comparator to be calibrated to be in a normal working mode.

FIG. 8 is a timing diagram of the correlation signals of the comparator to be calibrated during the calibration phase and after the calibration is completed. Referring to fig. 8, the comparator to be calibrated is in the sampling phase when the sampling clock signal is at a high level, and in the comparison phase when the sampling clock signal is at a low level. In the comparison stage, the clock of the comparator to be calibrated is an internal circulation clock signal generated by an internal circulation clock module, and the internal circulation clock signal is an asynchronous clock, namely, the working clock of the comparator to be calibrated.

Specifically, in the sampling stage, when the sampling clock signal is at a high level, a calibration clock signal of a high level is generated, so that the comparator to be calibrated compares the common mode signal to obtain a differential output result, and the comparator to be calibrated is calibrated. The calibration clock signal is low level, calibration is completed, the sampling clock signal is used for stopping generating square wave pulse signals, and the comparator to be calibrated enters a normal working state.

In implementations, the clock logic 232 is used to provide a calibration clock signal or a calibration clock reset signal. The calibration clock signal generates a square wave during the sampling phase to enable the comparator to be calibrated to operate. After the comparator to be calibrated generates a calibration result, the calibration time Zhong Fuwei signal is set high so that the calibration clock signal is reset, thereby turning off the comparator to be calibrated.

In an implementation, the clock generation circuit 233 is used to generate a global operating clock signal clk for the comparator to be calibrated. The calibration clock signal generates a square wave during the sampling phase and the internal circulation clock signal generates a square wave during the comparison phase. In the calibration process, the clock generating circuit 233 superimposes the internal circulation clock signal and the calibration clock signal to generate the working clock signal clk in the process that the calibration clock signal is at a high level and the detection result signal is at a low level. When calibration is completed, that is, the detection result signal is at a high level, the clock generation circuit 233 takes the internal circulation clock signal as the operation clock signal, that is, directly outputs the internal circulation clock signal. And after the comparator generates a calibration result, the calibration clock reset signal is changed to a high level, and the calibration clock signal is reset, so that the comparator to be calibrated is closed.

In an embodiment of the present invention, referring to fig. 3, the calibration logic control unit 21 may further include: calibration initiation circuit 214. The calibration start circuit 214 is connected to the output end of the to-be-calibrated comparator 10, the calibration code generation circuit 211 and the comparator control unit 23, and is configured to generate a start signal to the calibration code generation circuit 211 to enable the calibration code generation circuit 211 when detecting a differential output result of the to-be-calibrated comparator 10; and generates the calibration clock reset signal to the comparator control unit 23.

In particular implementations, the calibration initiation circuit 214 initiates the entire comparator offset calibration device after the comparator to be calibrated generates the first comparison result, and shuts down the entire comparator offset calibration device after calibration is completed by the calibration clock reset signal.

In one embodiment of the present invention, referring to fig. 9, the calibration initiation circuit 214 may include: a first nor gate 91 and a first register 92. Wherein:

the input end of the first nor gate circuit 91 is connected with the output end of the comparator to be calibrated, and the output end of the first nor gate circuit is connected with the calibration code generating circuit and is used for generating a starting signal to the calibration code generating circuit when the differential output result of the comparator to be calibrated is detected;

The first register 92 is connected to the output end of the first nor gate 71 and the detection circuit, and is configured to be turned on when the start signal is received, generate the calibration clock reset signal based on the sampling clock signal when the detection result signal does not arrive, and set the calibration clock reset signal to a high level when the detection result signal arrives.

Specifically, the first nor gate 91 generates a start signal for turning on the calibration code generation circuit when detecting the differential output result of the comparator to be calibrated. The first register 92 generates a calibration clock reset signal based on the sampling clock signal, the enable signal, and the detection result signal. The start signal is used to start the first register 92, and when the detection result signal does not reach (i.e. changes from low level to high level) in the sampling stage, the calibration clock reset signal determines whether to be high level according to the sampling clock signal, specifically, the calibration clock reset signal may be set to be low level in the sampling stage, and when the detection result signal reaches, it indicates that calibration is finished, the calibration clock reset signal may be set to be high level, and the circuit ends calibration. In the compare phase, the calibrate clock reset signal may be set high, calibrating Zhong Fuwei.

In an embodiment of the present invention, referring to fig. 3, the calibration logic control unit 21 may further include: the clock generation circuit 215 is stored. The storage clock generating circuit 215 is connected to the calibration code storing circuit 213 and the calibration code generating circuit 211, and is configured to generate a calibration code storage clock signal and a calibration code reset signal rst based on a first clock signal with a preset frequency, where the calibration code storage clock signal is used to control the calibration code storing circuit to store a calibration code, and the calibration code reset signal rst is used to reset the calibration code generating circuit.

In an implementation, the memory clock generation circuit 215 is configured to generate the calibration code memory clock signal, and generate the calibration code reset signal rst after each bit of the calibration code is generated, and reset the calibration code generation circuit 211.

In an embodiment of the present invention, referring to fig. 10, the storage clock generating circuit 215 may include a third shift register 101 and a fourth shift register 102. Wherein:

the third shift register 101 is configured to receive the first clock signal cal_clk and a sampling clock signal, and generate the calibration code reset signal rst after K rising edges of the first clock signal cal_clk when the sampling clock signal is at a high level;

The fourth shift register 102 is connected to the third shift register 101, and is configured to generate a bit of the calibration code storage clock signal cal_clk <8:0> when receiving the calibration code reset signal rst.

FIG. 11 is a timing diagram of the first clock signal CAL_CLK and the calibration code storage clock signal cal_clk <8:0>. Referring to fig. 10 and 11, specifically, the third shift register 101 may be a K-bit shift register. For example, when k=6, the third shift register 101 may be a 6-bit shift register, the first clock signal cal_clk is used as a clock signal, the calibration code reset signal rst is generated after six rising edges of the first clock signal cal_clk, and is output to the fourth shift register 102 at the same time as a rising pulse, and the fourth shift register 102 generates a calibration code storage clock signal.

In an implementation, the fourth shift register 102 may be an N-bit shift register for generating N calibration code storage clock signals, where N is greater than or equal to 2 and N is an integer. For example, the fourth shift register 102 may be configured as a 9-bit shift register, thereby generating nine calibration code storage clock signals, respectively, a first calibration code storage clock signal cal_clk <0>, a second calibration code storage clock signal cal_clk <1>, … …, and a ninth calibration code storage clock signal cal_clk <8>. And each calibration code storage clock signal is sequentially input to the calibration code storage circuit. The calibration code storage circuit stores a candidate calibration code signal each time a calibration code storage clock signal is received.

In implementations, the sampling clock signal is used to control the switching of the memory clock generation circuit 215. Specifically, the memory clock generation circuit 215 may be turned on during the sampling phase and turned off during the non-sampling phase.

In an embodiment of the present invention, the preset calibration end condition includes: the last bit of the calibration code storage clock signal is received. For example, when the fourth shift register 102 is a 9-bit shift register and generates nine calibration code storage clock signals in total, referring to fig. 7, the detection circuit 231 may generate a detection result signal to turn off the comparator offset calibration device when receiving the last calibration code storage clock signal, i.e., the ninth calibration code storage clock signal cal_clk <8 >.

That is, the detection circuit 231 may generate the detection result signal when the number of times that the K differential output results simultaneously appear in the high level and the low level exceeds two in the process of generating any pair of candidate calibration code signals, or may generate the detection result signal after generating the last pair of candidate calibration code signals.

In an embodiment of the present invention, referring to fig. 3, the first clock signal cal_clk may be generated by the comparator control unit 23. Specifically, referring to fig. 7, the clock logic 232 may generate the first clock signal with the predetermined frequency when the calibration clock signal is at the high level before the calibration is not completed. For example, the input of the clock logic 232 may be coupled to a calibration clock reset signal and a calibration clock signal to generate the first clock signal.

In particular implementations, referring to fig. 3, the calibration DAC unit 22 may include: switch control circuit 221 and resistor DAC222. Wherein:

the switch control circuit 221 includes N switch control modules, where the switch control modules are used to be turned on in the sampling process, and obtain corresponding control codes based on the calibration codes generated by the calibration logic control unit in the calibration process; n is more than or equal to 2 and N is an integer;

the resistor DAC222 is connected to the switch control circuit 221, and includes two resistor DAC subunits, where each resistor DAC subunit includes N resistor units connected in series, and each resistor unit is connected to a corresponding switch control module.

In a specific implementation, the value of N may be set according to the actual precision requirement. N may be equal to 9 or other values, without limitation. When N varies, the number of switch control modules and the number of resistor units and the fourth shift register vary accordingly. As N increases, the calibration accuracy increases, and is more suitable for use in high accuracy ADCs.

In an embodiment of the present invention, referring to fig. 12, the switch control module may include: calibration code input sub-module 121 and calibration switch control logic sub-module 122. Wherein the calibration code input sub-module 121 stores the first calibration code signal CAL <8:0>, the second calibration code signal CAL' <8:0> and the calibration code storage clock signal cal_clk <8:0> is input to the calibration switch control logic sub-module 122.

The sampling clock signal is used to control the on time of the calibration switch control logic sub-module 122. The detection result signal is generated by the comparator control unit 23 for detecting whether the calibration is completed or not throughout the calibration process. If the calibration is completed, the detection result signal outputs a high level, and the calibration switch control logic sub-module 122 is turned off, otherwise, the calibration switch control logic sub-module 122 outputs a corresponding control code based on the input of the calibration code input sub-module 121. Wherein, the different calibration code signals and the calibration code storage clock signals are different corresponding control code signals.

In a specific implementation, when n=9, the switch control circuit includes 9 switch control modules, and the resistor DAC includes 9 resistor units, where the switch control modules and the resistor units are in one-to-one correspondence.

In a specific implementation, the resistor DAC222 may be in a split structure, and each resistor unit may include 3 resistors. Specifically, referring to fig. 13, each of the resistance units may include a first resistance R1, a second resistance R2, and a third resistance R3. The switch control module outputs two paths of control code signals which are respectively used for controlling a first resistor R1 and a second resistor R2 of the split resistor. The first resistor R1 is connected with a first control code signal, the second resistor R2 is connected with a second control code signal, and the third resistor is connected with the other ends of the first resistor R1 and the second resistor R2. The resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 may be the same, for example, the resistance values may be all 2R.

In an implementation, the resistor DAC222 includes two resistor DAC subunits, referring to fig. 14, p resistor DAC subunits dac_p and n resistor DAC subunits dac_n, respectively. Each path of resistor DAC subunit includes N series-connected resistor units. For example, when n=9, referring to fig. 15, there are 9 resistor units connected in series to form a p-path resistor DAC subunit, and the resistances of all resistors in each resistor unit are the same and are all 2R.

In particular implementations, referring to fig. 14, the p-way resistor DAC subunit dac_p is used to generate the p-way calibration signal inp_cal and the n-way resistor DAC subunit dac_n is used to generate the n-way calibration signal inn_cal. The resistor DAC222 may further include: the VCM generating unit 141, the second switch SW2, and the third switch SW3. The second switch SW2 is located between the p-way resistance DAC sub-unit dac_p and the VCM generating unit 141, and the third switch SW3 is located between the n-way resistance DAC sub-unit dac_n and the VCM generating unit 141. The VCM generating unit 141 is configured to output a common mode voltage.

Specifically, the p-way resistive DAC subunit dac_p and the n-way resistive DAC subunit dac_n are enabled under control of the path selection signal. For example, when the path select signal turns on the p-path, the p-way resistor DAC subunit DAC_p is enabled and the n-way resistor DAC subunit DAC_n is not enabled. When the path select signal turns on the n paths, the n-way resistor DAC subunit dac_n is enabled and the p-way resistor DAC subunit dac_p is not enabled.

If the p-way resistor DAC subunit DAC_p is started, the third switch SW3 is turned on, the second switch SW2 is turned off, the p-way calibration signal inp_cal outputs a calibration voltage, and the n-way calibration signal inn_cal outputs a common mode voltage. Conversely, if the n-way resistor DAC subunit dac_n is started, the second switch SW2 is turned on, the third switch SW3 is turned off, the n-way calibration signal inn_cal outputs a calibration voltage, and the p-way calibration signal inp_cal outputs a common mode voltage. The final p-path calibration signal inp_cal and the n-path calibration signal inn_cal are used as calibration signals to be output to the comparator to be calibrated, and the differential output offset of the comparator to be calibrated can be calibrated.

It should be noted that, in the implementation, the calibration DAC unit is not limited to the resistive DAC circuit, but may be implemented by a capacitive DAC circuit, which is not illustrated here.

Fig. 16 is a schematic circuit diagram of a dynamic differential comparator. The dynamic differential comparator may include: the first NMOS tube N1, the second NMOS tube N2, the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5, the first PMOS tube P1 and the second PMOS tube P2. The gates of the first NMOS transistor N1 and the second NMOS transistor N2 are adapted to be connected to differential input signals inp and inn, and the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to calibration signals inp_cal and inn_cal. The gates of the fifth NMOS tube N5, the first PMOS tube P1 and the second PMOS tube P2 are connected with the working clock signal clk.

The differential input end of the dynamic differential comparator is connected in parallel with a pair of calibration input tubes, namely a third NMOS tube N3 and a fourth NMOS tube N4, and the current of the differential input end of the dynamic differential comparator is adjusted through the input voltage difference value of the calibration input tubes, so that the purpose of offset calibration is achieved.

The comparator offset calibration device can work in a sampling stage, the comparator to be calibrated can perform comparison for offset calibration once in each sampling period, and the comparison result is output to the calibration code generation circuit for generating the calibration code. The calibration code is input to a switch control circuit of the calibration DAC unit to control the resistor DAC. The resistor DAC converts the digital code into an analog signal and outputs the analog signal to the third NMOS tube N3 and the fourth NMOS tube N4, and offset calibration of the input end of the comparator to be calibrated is carried out by adjusting the differential input current of the comparator.

Referring to fig. 3, taking k=6 as an example, a specific calibration procedure of the comparator offset calibration device in the embodiment of the present invention is as follows:

STEP1 reset phase: the sampling clock signal is at a high level, the first switch SW1 is turned off, and the differential input signals inn and inp of the comparator to be calibrated 10 are connected to the common mode voltage vcm.

STEP2 comparison stage: the sampling clock signal is kept at a high level, the calibration clock signal provides a rising edge, the comparator to be calibrated is started, and the comparator to be calibrated performs one-time comparison. And after the comparison result is generated, the comparator to be calibrated is turned off.

STEP3 operation stage: STEP1 and STEP2 are repeated six times, and a pair of candidate calibration code signals are obtained through logic operation of the offset calibration code generation circuit. In the operation stage, the detection circuit works to detect the calibration condition in real time. If the high level and the low level appear more than twice at the same time in the six differential output results, indicating that the calibration is finished, setting a detection result signal to be high level by the detection circuit, and turning off a comparator offset calibration device; if this is not the case, then the calibration code is selected from the six results for the majority of cases.

STEP4 calibration phase: and each time a one-bit calibration code is generated, outputting the one-bit calibration code to a calibration DAC, and adjusting the calibration voltage to prepare for the next calibration.

STEP5: repeating the four stages, if the condition that the detection result signal becomes high level does not appear in the middle, repeating the operation until the calibration code signal is completely generated, and completing the calibration.

The comparator offset calibration device in the embodiment of the invention has the advantages that each candidate calibration code signal is generated after multiple comparison and logic operation, and the reliability is higher. In addition, in the process of generating the calibration code, the calibration result is detected in real time, and if the comparator calibration is detected to be completed, the calibration circuit can be turned off without waiting for the calibration code to be completely generated, so that the calibration power consumption is effectively reduced.

The offset calibration device of the comparator in the embodiment of the invention can automatically calibrate after power-on without inputting any signal externally to adjust, thereby reducing the chip area and reducing the external control complexity of calibration. In addition, the comparator is calibrated by adopting a calibration DAC independent of the DAC in the ADC, the calibration precision is not limited by the number of bits of the ADC, and the calibration precision can be higher.

The embodiment of the invention also provides an analog-to-digital converter, which comprises the comparator calibration device in the embodiment.

It should be noted that the analog-to-digital converter includes, but is not limited to, an asynchronous dynamic successive approximation ADC.

The comparator calibration device can be used for calibrating a foreground of a comparator in an ADC. The comparator calibration device is inserted between the input and the output of the comparator, and the output parameters of the comparator calibration device are adjusted to correct the error of the comparator, so that the performance of the comparator is corrected in real time, and the accuracy of the ADC can be improved.

With respect to each of the apparatuses and each of the modules/units included in the products described in the above embodiments, it may be a software module/unit, a hardware module/unit, or a software module/unit, and a hardware module/unit. For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least part of the modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the rest (if any) of the modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a hardware manner such as a circuit, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program, the software program runs on a processor integrated in the chip module, and the rest (if any) of the modules/units can be realized in a hardware manner such as a circuit; for each device, product, or application to or integrated with the terminal, each module/unit included in the device, product, or application may be implemented by using hardware such as a circuit, different modules/units may be located in the same component (for example, a chip, a circuit module, or the like) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program, where the software program runs on a processor integrated inside the terminal, and the remaining (if any) part of the modules/units may be implemented by using hardware such as a circuit.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A comparator offset calibration device, characterized in that it is used for offset calibration of a dynamic differential comparator; the comparator offset calibration device includes: a calibration logic control unit, a calibration DAC unit and a comparator control unit; wherein:

The calibration logic control unit is connected to the comparator to be calibrated, and is used to generate and store a calibration code when the comparator to be calibrated is out of adjustment;

The calibration DAC unit is connected to the logic control unit and is used to obtain the calibration code generated by the logic control unit, generate a calibration signal based on the calibration code, and use the calibration signal to perform calibration on the comparator to be calibrated. calibration;

The comparator control unit is connected to the calibration logic control unit and is used to detect in real time whether the preset calibration end condition is met, and when the preset calibration end condition is met, generate a detection result signal to close the comparison instrument calibration device.

2. The comparator offset calibration device according to claim 1, wherein the calibration logic control unit includes:

a calibration code generation circuit, connected to the comparator to be calibrated, for generating a pair of candidate calibration code signals based on the differential output result of the differential comparator to be calibrated when the comparator to be calibrated is out of tune; the one The candidate calibration code signal is used to represent two one-bit candidate calibration codes;

A path selection circuit, connected to the calibration code generation circuit, used to determine the offset direction of the comparator to be calibrated using the candidate calibration code signal, and generate a corresponding path selection signal based on the determined offset direction;

A calibration code storage circuit is connected to the path selection circuit and the calibration code generation circuit, and is used to use the path selection signal to select a corresponding one-bit candidate calibration code signal from the candidate calibration code signals for storage.

3. The comparator offset calibration device according to claim 2, wherein the calibration code generation circuit is used to continuously obtain K differential output results of the comparator to be calibrated, and generate the calibration code based on the K differential output results of the comparator to be calibrated. The differential output result determines whether the comparator to be calibrated is out of tune, and when it is determined that the comparator to be calibrated is out of tune, a pair of candidate calibration code signals is generated; K≥2, and K is an integer.

4. The comparator offset calibration device according to claim 3, wherein the calibration code generation circuit includes: a first calibration code generation sub-circuit and a second calibration code generation sub-circuit, wherein:

The first calibration code generation sub-circuit includes: a first inverter, a first logic circuit, a first selector and a first shift register connected in sequence;

The second calibration code generation sub-circuit includes: a second inverter, a second logic circuit, a second selector and a second shift register connected in sequence;

Wherein, the input terminal of the first inverter is connected to the first output terminal of the comparator to be calibrated, and the input terminal of the second inverter is connected to the second output terminal of the comparator to be calibrated; The first selector and the second selector are used to store the output of the connected inverter in the connected shift register before calibration is completed;

The first shift register and the second shift register are used to store K output results of corresponding inverters and generate a candidate calibration code signal.

5. The comparator offset calibration device according to claim 4, wherein the first shift register and the second shift register are used to obtain two of the K differential output results of the corresponding inverter. When the above differential output result is high level, a high level candidate calibration code signal is generated, otherwise a low level candidate calibration code signal is generated.

6. The comparator offset calibration device according to claim 3, wherein the comparator control unit includes:

A detection circuit, connected to the calibration code generation circuit, is used to obtain the candidate calibration code signal, and determine whether the preset calibration end condition is met based on the candidate calibration code signal.

7. The comparator offset calibration device according to claim 6, wherein the preset calibration end condition includes: among the K differential output results, the number of occurrences of high level and low level exceeds the preset number of times at the same time. .

8. The comparator offset calibration device according to claim 6, wherein the comparator control unit further includes: a clock logic circuit and a clock generation circuit; wherein:

The clock logic circuit is configured to receive a calibration clock signal and a calibration clock reset signal, and provide the high-level signal in the calibration clock signal and the calibration clock reset signal to the clock generation circuit;

The clock generation circuit is connected to the clock logic circuit and the detection circuit, and is used to generate the to-be-used clock signal using the calibration clock signal, the calibration clock reset signal, the detection result signal and the internal cycle clock signal. The working clock signal of the calibration comparator; the inner loop clock signal is used to control the comparator to be calibrated to be in a normal working mode.

9. The comparator offset calibration device according to claim 8, wherein the clock generation circuit is configured to generate the calibration clock signal when the calibration clock signal is at a high level and the detection result signal is at a low level. The inner circulation clock signal is superposed with the calibration clock signal to obtain the working clock signal of the comparator to be calibrated; when the detection result signal is high level, the inner circulation clock signal is used as the working clock signal ; And when the calibration clock reset signal is high level, reset the calibration clock signal to turn off the comparator to be calibrated.

10. The comparator offset calibration device according to claim 8, wherein the calibration logic control unit further includes:

A calibration start circuit, connected to the output end of the comparator to be calibrated, the calibration code generation circuit and the comparator control unit, for generating a start signal when the differential output result of the comparator to be calibrated is detected. to the calibration code generation circuit to enable the calibration code generation circuit;

and generating the calibration clock reset signal to the comparator control unit.

11. The comparator offset calibration device according to claim 10, wherein the calibration start circuit includes:

A first NOR gate circuit, the input terminal is connected to the output terminal of the comparator to be calibrated, the output terminal is connected to the calibration code generating circuit, and is used to generate when the differential output result of the comparator to be calibrated is detected. initiating a signal to the calibration code generation circuit;

The first register is connected to the output end of the first NOR gate circuit and the detection circuit, and is used to open when the start signal is received, and when the detection result signal does not arrive, based on the sampling clock signal The calibration clock reset signal is generated, and when the detection result signal arrives, the calibration clock reset signal is set to a high level.

12. The comparator offset calibration device according to claim 3, wherein the calibration code storage circuit includes:

An OR gate circuit, a third selector and a fourth selector connected to the calibration code generation circuit;

a first latch connected to the OR gate circuit;

a first calibration code register connected to the third selector and the first latch;

And a second calibration code register connected to the fourth selector and the first latch;

Wherein, the first latch is used to enable the first calibration code register and the second calibration code register; the first calibration code register and the second calibration code register are used to select the signal based on the path. The corresponding candidate calibration code signal is stored.

13. The comparator offset calibration device according to claim 2, wherein the calibration logic control unit further includes:

A storage clock generation circuit, connected to the calibration code storage circuit and the calibration code generation circuit, for generating a calibration code storage clock signal and a calibration code reset signal based on a first clock signal of a preset frequency, wherein the calibration code The storage clock signal is used to control the calibration code storage circuit to store the calibration code, and the calibration code reset signal is used to reset the calibration code generation circuit.

14. The comparator offset calibration device according to claim 13, wherein the storage clock generation circuit includes:

The third shift register is used to receive the first clock signal and the sampling clock signal, and generate the calibration code after K rising edges of the first clock signal when the sampling clock signal is high level. reset signal;

and a fourth shift register, connected to the third shift register, for generating a one-bit calibration code storage clock signal when receiving the calibration code reset signal.

15. The comparator offset calibration device according to claim 14, wherein the preset calibration end condition includes: receiving the last bit of the calibration code storage clock signal.

16. The comparator offset calibration device according to claim 1, wherein the calibration DAC unit includes:

The switch control circuit includes N switch control modules. The switch control modules are used to turn on during the sampling process, and during the calibration process, based on the calibration code generated by the calibration logic control unit, the corresponding control code is obtained; N≥ 2 and N is an integer;

The resistor DAC is connected to the switch control circuit and includes two resistor DAC sub-units. Each resistor DAC sub-unit includes N resistor units connected in series, and each resistor unit is connected to the corresponding switch control module.

17. An analog-to-digital converter, comprising the comparator calibration device according to any one of claims 1 to 16.