CN117560002A - Detection device, method, correction device and method for metastable state of synchronization signal in clock circuit - Google Patents

Abstract

The invention discloses a device for detecting metastable state of synchronous signals in a clock circuit, which comprises: the second buffer is used for carrying out delay processing on the first delay signal to obtain a second delay signal; the front-stage trigger is used for respectively sampling the synchronous input signal and the second delay signal and outputting a first sampling signal and a second sampling signal; the exclusive OR gate logic module is used for carrying out exclusive OR operation on the first sampling signal and the second sampling signal to obtain a first width pulse signal; the sampling delay device is used for sampling the first width pulse signal to obtain a third sampling signal, and carrying out delay processing on the third sampling signal to obtain a third delay signal; and the OR gate logic module is used for carrying out OR operation on the third delay signal and the third sampling signal to output a pulse signal, and determining metastable state detection of the synchronous signal according to the level state of the pulse signal. The invention adopts a novel metastable state detection structure, and solves the problem that the metastable state output delay is relatively large when the synchronizing signal of the traditional structure is reduced.

Description

Device and method for detecting metastable state of synchronous signal in clock circuit, and device and method for correcting metastable state of synchronous signal in clock circuit

Technical Field

The invention relates to the technical field of digital-analog hybrid integrated circuits, in particular to a device and a method for detecting metastable state of a synchronizing signal in a clock circuit, and a device and a method for correcting the metastable state of the synchronizing signal.

Background

In a/D converter design, multi-core configuration is a more common approach. In order to ensure that the signal of each channel can be sampled simultaneously and the signal phase of the output channel is ensured, it is important to set an internal synchronization signal. The synchronous signal is aligned with the clock signal sampling through the latch, and in order to realize effective sampling of the synchronous signal, the synchronous signal is required to be kept stable in the time of establishing the rising edge of the clock and the time of keeping the rising edge of the clock, so that the synchronous signal is prevented from entering a metastable state.

Metastable states describe the situation where there is a mismatch between the rising edge of the synchronization signal and the edge of the clock signal, when the input of the synchronization signal transitions, entering the rising time and hold period of the clock signal, the signal output is in an indeterminate state, entering the metastable state, resulting in a failure of the signal synchronization function. When the clock frequency is low, the probability of entering a metastable state is not large, and the state is easily avoided. However, as the frequency increases, the clock period shortens, and the period of the sampling clock at frequencies above gigahertz shortens to picosecond, the situation of entering metastable state increases.

In order to reduce the probability of entering metastable state, the conventional structure mainly adopts a multi-stage D flip-flop as a synchronizer, which is relatively simple but increases the circuit scale, and the multi-stage flip-flop increases the input delay of the synchronizing signal, which limits the time for the a/D converter system to respond to the synchronizing signal, which is to be avoided as much as possible in the ultra-high-speed a/D converter. In order to solve the problem of large delay, another method is proposed, and a 2-stage synchronous trigger structure is adopted. The structure adopts the input of the clock multiplier to provide the clock for the trigger, and the method can meet the requirement of completing the response of the synchronous signal in a few clock cycles of the clock, but the design needs to specially design a frequency dividing circuit for the clock output, and the complexity and difficulty of the system design are also increased.

The method can reduce the occurrence probability of metastable state, can not eliminate the metastable state, and has the defects of the metastable state. In addition, when metastability occurs, the inside cannot be effectively detected, so that the overall function of the a/D converter is failed.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a device, a method, a device and a method for detecting metastable state of a synchronization signal, which are used for solving the problems of the prior art.

In order to achieve the above object and other related objects, the present invention provides a device for detecting metastable state of a synchronization signal in a clock circuit, where the synchronization signal is obtained by sampling a first delay signal by a first flip-flop based on a clock signal, and the first delay signal is obtained by delaying a synchronization input signal by a first buffer; the detection device includes:

the second buffer is used for carrying out delay processing on the first delay signal to obtain a second delay signal;

the front-stage trigger is used for receiving the synchronous input signal and the second delay signal, and respectively sampling the synchronous input signal and the second delay signal based on a clock signal to output a first sampling signal corresponding to the synchronous input signal and a second sampling signal corresponding to the second delay signal;

the exclusive-OR gate logic module is used for carrying out exclusive-OR operation on the first sampling signal and the second sampling signal to obtain a first width pulse signal;

the sampling delayer is used for sampling the first width pulse signal based on the clock signal to obtain a third sampling signal, and performing delay processing on the third sampling signal to obtain a third delay signal;

and the OR gate logic module is used for carrying out OR operation on the third delay signal and the third sampling signal to output a pulse signal, and determining metastable state detection of the synchronous signal according to the level state of the pulse signal.

In an embodiment of the present invention, the synchronization signal is in a metastable state when the pulse signal is at a high level, and is in a steady state when the pulse signal is at a low level.

In an embodiment of the present invention, the second buffer includes a first data input end and a first data output end, where the first data input end is electrically connected to the data output end of the first buffer and connected to a first delay signal; the first data output end is electrically connected with the data input end of the front-stage trigger module and outputs a second delay signal.

In an embodiment of the present invention, the pre-stage flip-flop includes:

a second flip-flop including a second data input, a second clock input, and a second data output for sampling a second delay signal; the second data input end is electrically connected with the output end of the second buffer and is connected with a second delay signal; the second clock input end is connected with a clock signal, and the second data output end is electrically connected with one data input end of the exclusive-OR gate logic module and outputs a first sampling signal;

the third trigger comprises a third data input end, a third clock input end and a third data output end and is used for sampling the synchronous input signal; the third data input end is connected with a synchronous input signal, and the third clock input end is connected with a clock signal; the third data output end is electrically connected with the other data input end of the exclusive-OR gate logic module and outputs a second sampling signal.

In an embodiment of the present invention, the sampling delay includes:

the fourth trigger comprises a fourth data input end, a fourth clock input end and a fourth data output end and is used for sampling the first width pulse signal; the fourth data input end is electrically connected with the data output end of the exclusive-OR gate logic module and is connected with a first width pulse signal; the fourth clock input end is connected with a clock signal; the fourth data output end is electrically connected with one data input end of the OR gate logic module and outputs a third sampling signal;

the fifth trigger comprises a fifth data input end, a fifth clock input end and a fifth data output end and is used for carrying out delay processing on the third sampling signal; the fifth clock input end is connected with a clock signal; the fifth data input end is electrically connected with the fourth data output end and is connected with a third sampling signal; the fifth data output end is electrically connected with the other data input end of the OR gate logic module and outputs a third delay signal.

In order to achieve the above object and other related objects, the present invention provides a method for detecting metastable state of a synchronization signal in a clock circuit, where the synchronization signal is obtained by sampling a first delay signal by a first flip-flop based on a clock signal, and the first delay signal is obtained by delaying a synchronization input signal by a first buffer; the detection method comprises the following steps:

performing delay processing on the first delay signal to obtain a second delay signal;

receiving the synchronous input signal and the second delay signal, and respectively sampling the synchronous input signal and the second delay signal based on a clock signal to output a first sampling signal corresponding to the synchronous input signal and a second sampling signal corresponding to the second delay signal;

performing exclusive OR operation on the first sampling signal and the second sampling signal to obtain a first width pulse signal;

sampling the first width pulse signal based on the clock signal to obtain a third sampling signal, and performing delay processing on the third sampling signal to obtain a third delay signal;

and performing OR operation on the third delay signal and the third sampling signal to output a pulse signal, and determining metastable state detection of the synchronous signal according to the level state of the pulse signal.

To achieve the above and other related objects, the present invention provides a correction device for metastable state of a synchronization signal in a clock circuit, the correction device comprising:

the detection device is used for detecting the detection result;

the RS trigger module comprises a first input end and a second input end; the first input end of the RS trigger module is electrically connected with the output end of the OR gate logic module, and the second input end of the RS trigger module is connected with a control signal; when the pulse signal is at a high level, setting a control signal to be high so as to reset the pulse signal to be at a low level; setting the control signal to be low, then changing the delay time of the first buffer and the second buffer, outputting again, and completing the correction of the synchronous signal when the pulse signal is detected to be low.

To achieve the above and other related objects, the present invention provides a synchronization signal correction method, including:

acquiring the level state of the pulse signal;

when the pulse signal is at a high level, setting a control signal to be high so as to reset the pulse signal to be at a low level; setting the control signal to be low, then changing the delay time of the first buffer and the second buffer, outputting again, and completing the correction of the synchronous signal when the pulse signal is detected to be low.

As described above, the device, method, correction device and method for detecting metastable state of synchronous signal in clock circuit provided by the invention have the following beneficial effects:

the invention relates to a device for detecting metastable state of synchronous signals in a clock circuit, which comprises: the second buffer is used for carrying out delay processing on the first delay signal to obtain a second delay signal; the front-stage trigger is used for receiving the synchronous input signal and the second delay signal, and respectively sampling the synchronous input signal and the second delay signal based on a clock signal to output a first sampling signal corresponding to the synchronous input signal and a second sampling signal corresponding to the second delay signal; the exclusive-OR gate logic module is used for carrying out exclusive-OR operation on the first sampling signal and the second sampling signal to obtain a first width pulse signal; the sampling delayer is used for sampling the first width pulse signal based on the clock signal to obtain a third sampling signal, and performing delay processing on the third sampling signal to obtain a third delay signal; and the OR gate logic module is used for carrying out OR operation on the third delay signal and the third sampling signal to output a pulse signal, and determining metastable state detection of the synchronous signal according to the level state of the pulse signal. The invention adopts a novel metastable state detection structure, solves the problem that the metastable state output delay is large when the synchronous signal of the traditional structure is reduced, and meets the requirement of quick response of the ultra-high-speed A/D converter.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram of a conventional multi-stage D flip-flop to reduce metastability;

FIG. 2 is a circuit diagram of a device for detecting metastable states of synchronization signals in a clock circuit according to an embodiment of the invention;

FIG. 3 is a schematic diagram of metastability identification according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating meta-stability identification according to an embodiment of the present invention;

FIG. 5 is a timing diagram of metastability detection according to an embodiment of the present invention;

FIG. 6 is a flowchart of a method for detecting metastability of a synchronization signal in a clock circuit according to an embodiment of the invention;

FIG. 7 is a schematic diagram of a device for correcting metastable states of synchronization signals in a clock circuit according to an embodiment of the invention.

Detailed Description

Further advantages and effects of the present invention will become readily apparent to those skilled in the art from the disclosure herein, by referring to the accompanying drawings and the preferred embodiments. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be understood that the preferred embodiments are presented by way of illustration only and not by way of limitation.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.

Referring to fig. 2, fig. 2 is a circuit diagram of a device for detecting metastable states of synchronization signals in a clock circuit according to an embodiment of the invention. The detection device is used for detecting metastable state of a synchronous signal, wherein the synchronous signal SYNCO is obtained by sampling the first delay signal SYNC_B1 through a first trigger D1 based on a clock signal, and the first delay signal SYNC_B1 is obtained by delaying a synchronous input signal SYNCIN based on a first BUFFER BUFFER 1; the detection device includes:

the second BUFFER2 is configured to perform delay processing on the first delay signal sync_b1 to obtain a second delay signal sync_b2;

the pre-stage flip-flop is configured to receive the synchronization input signal SYNCIN and the second delay signal sync_b2, and sample the synchronization input signal SYNCIN and the second delay signal sync_b2 based on a clock signal CLK, respectively, to output a first sampling signal Q2 corresponding to the synchronization input signal SYNCIN and a second sampling signal Q3 corresponding to the second delay signal sync_b2;

an exclusive-OR gate logic module XOR, configured to perform an exclusive-OR operation on the first sampling signal Q2 and the second sampling signal Q3 to obtain a first width pulse signal;

the sampling delayer is used for sampling the first width pulse signal based on the clock signal CLK to obtain a third sampling signal Q4, and performing delay processing on the third sampling signal Q4 to obtain a third delay signal Q5;

and the OR gate logic module OR is configured to perform an OR operation on the third delay signal Q5 and the third sampling signal Q4 to output a pulse signal sync_flag, and determine metastable state detection of the synchronization signal SYNCO according to the level state of the pulse signal sync_flag.

The above-described respective modules and units will be described in detail below.

In an embodiment, the second BUFFER2 includes a first data input end and a first data output end, where the first data input end is electrically connected to the data output end of the first BUFFER BUFFER1 and connected to the first delay signal SYNC_B1; the first data output end is electrically connected with the data input end of the front-stage trigger module and outputs a second delay signal SYNC_B2.

Specifically, the first buffer and the second buffer have the same structure, and the capability of delaying the processing signals is the same, so that equal delay signals sync_b1 and sync_b2 are obtained. As one example, in gigahertz clock circuit applications, a BUFFER unit may be delayed with a high-speed single stage amplifier, with a single BUFFER delay of T _delay The actual delay is controlled within tens of ps.

In one embodiment, the pre-stage flip-flop includes:

a second flip-flop D2 including a second data input, a second clock input and a second data output for sampling the second delay signal sync_b2; the second data input end is electrically connected with the output end of the second BUFFER BUFFER2 and is connected with a second delay signal SYNC_B2 output by the output end of the second BUFFER BUFFER 2; the second clock input end is connected with a clock signal CLK, and the second data output end is electrically connected with one data input end of the exclusive OR gate logic module XOR and outputs a first sampling signal Q2;

a third flip-flop D3 including a third data input terminal, a third clock input terminal, and a third data output terminal, for sampling the synchronization input signal SYNCIN; the third data input terminal is connected with a synchronous input signal SYNCIN, and the third clock input terminal is connected with a clock signal CLK; the third data output terminal is electrically connected with the other data input terminal of the exclusive-or gate logic module XOR, and outputs a second sampling signal Q3.

As shown in fig. 3, t1 is the setup and hold time of the synchronization input signal SYNCIN, and t2 is the delay time of the external port with the rising edge of the clock after looking into the setup of the synchronization input signal SYNCIN signal. The figure shows the case of 2 kinds of metastable forbidden zone identification. When the time t1 region of the synchronization input signal SYNCIN falls into the rising edge region of the clock signal CLK, as indicated by the dotted arrow in fig. 3, the synchronization input signal SYNCIN falls into the metastable forbidden region, and the synchronization input signal SYNCIN edge is in the metastable region as shown at the bottom.

Further, when the stable signal after the time t1 in the synchronization input signal SYNCIN falls into the rising edge region of the clock signal CLK, as indicated by the solid arrow in the figure, the rising edge of the synchronization input signal SYNCIN does not fall into the steady-state forbidden region, and at this time, the edge of the synchronization input signal SYNCIN is in the steady-state region as shown at the bottom.

t1 and t2 determine the valid time window of the synchronization input signal synnc signal input at the external port, and when the synchronization input signal synnc signal is valid, the synchronization design needs to ensure that the synchronization input signal synnc signal does not fall into the metastable forbidden zone.

It should be noted that, the first to fifth flip-flops are D flip-flops. As shown in fig. 4, the first, second and third flip-flops D1, D2 and D3 sample the synchronous input signal SYNCIN, the first and second delay signals sync_b1 and sync_b2 respectively by using rising edges of the master clock signal, and rising edges of the synchronous input signal SYNCIN, the first and second delay signals sync_b1 and sync_b2 respectively delay by T _delay Time.

When the signal establishment and maintenance stage of the first delay signal sync_b1 is not at the rising edge of the master clock signal CLK, the first delay signal sync_b1 is in a steady-state region, the phase of the first sampling signal Q2 output by the second trigger D2 is completely consistent with the phase of the second sampling signal Q3 output by the third trigger D3, and the output synchronizing signal SYNCO is in the steady-state region, so as to meet the synchronizing requirement of the synchronizing input signal SYNCIN.

When the first delay signal sync_b1 is in a metastable state, in the first flip-flop D1, the setup and hold phase thereof is located in the clock rising edge region, the first sampling signal Q2 output by the second flip-flop D2 and the second delay signal Q3 output by the third flip-flop D3 are different, the rising edge phase of the two rising edges is different by one clock period, and the output synchronizing signal SYNCO is in an unstable state in the clock period.

The synchronous input signal SYNCIN set-up and hold phase is to the left of the clock edge at which the output second sampling signal Q3 will be _CLK The rising edge is sampled when it arrives, and a first sampling signal Q2 is output.

The second delay signal SYNC_B2 signal establishing and maintaining stage is positioned at the right side of the clock edge, and the output of the first sampling signal Q2 is performed at the next clock T _CLK The +1 rising edge arrives, and a second sampling signal Q3 is output.

In one embodiment, the sampling delay includes:

a fourth flip-flop D4, including a fourth data input terminal, a fourth clock input terminal, and a fourth data output terminal, for sampling the first width pulse signal; the fourth data input end is electrically connected with the data output end of the exclusive-or gate logic module XOR and is connected with a first width pulse signal; the fourth clock input is connected with a clock signal CLK; the fourth data output end is electrically connected with one of the data input ends of the OR gate logic module OR and outputs a third sampling signal Q4;

a fifth flip-flop D5, including a fifth data input terminal, a fifth clock input terminal, and a fifth data output terminal, for performing delay processing on the third sampling signal Q4; the fifth clock input is connected with a clock signal CLK; the fifth data input end is electrically connected with the fourth data output end and is connected with a third sampling signal Q4; the fifth data output terminal is electrically connected to the other data input terminal of the OR gate logic module OR, and outputs the third delay signal Q5.

It should be noted that, the clock input ends of the fourth trigger D4 and the fifth trigger D5 are connected as clock inputs, so as to ensure that the sampled data edges are consistent, and the pulse width is one main clock period. The third sampling signal Q4 increases in width of its signal after being processed by the OR gate logic block OR.

In an embodiment, the synchronization signal is in a metastable state when the pulse signal is high, and in a steady state when the pulse signal is low.

In summary, the device for detecting metastable state of synchronous signal in gigahertz clock circuit provided by the invention adopts novel metastable state detection and correction structure, thereby avoiding the situation that synchronous signal enters metastable state due to shortened clock signal period, solving the problem that the output delay of metastable state is larger due to reduced synchronous signal of traditional structure, and meeting the requirement of quick response of ultra-high speed A/D converter; compared with the traditional metastable state reducing structure, the SYNCO synchronous output signal output by the invention can be sent into the internal AD core for synchronization after being sampled by only one D trigger clock edge, thereby avoiding the problems of larger synchronous input delay and slower effect caused by the multistage synchronizer structure. The synchronous output delay is small, and the response speed is high; meanwhile, in the metastable state detection process, a circuit frequency multiplier is not needed to be used for clock frequency multiplication, complex units such as a counter and the like are not needed, and the metastable state detection is realized only through simple logic operation. And the detection result is optimized, so that the situation that the output result is influenced by internal parasitism due to too fast high-frequency clock frequency and too narrow SYNC_FLAG pulse signal is avoided. Based on the description, the invention effectively solves the defect that the metastable state of the synchronous signal exists in the gigahertz clock circuit, has higher use value, and can be applied to the field of digital-analog hybrid integrated circuits.

Referring to fig. 6, fig. 6 is a schematic diagram showing a method for detecting metastable states of synchronization signals in a clock circuit according to an embodiment of the present invention, where the synchronization signals are obtained by sampling the first delay signal sync_b1 by a first flip-flop D1 based on clock signals, and the first delay signal sync_b1 is obtained by delaying the synchronization input signal SYNCIN by a first BUFFER 1; the detection method comprises the following steps:

step S610, performing delay processing on the first delay signal sync_b1 to obtain a second delay signal sync_b2;

step S620, receiving the synchronization input signal SYNCIN and the second delay signal sync_b2, and sampling the synchronization input signal SYNCIN and the second delay signal sync_b2 based on a clock signal CLK to output a first sampling signal Q2 corresponding to the synchronization input signal SYNCIN and a second sampling signal Q3 corresponding to the second delay signal sync_b2, respectively;

step S630, performing exclusive-or operation on the first sampling signal Q2 and the second sampling signal Q3 to obtain a first width pulse signal;

step S640, sampling the first width pulse signal based on the clock signal to obtain a third sampling signal Q4, and performing delay processing on the third sampling signal Q4 to obtain a third delay signal Q5;

in step S650, the third delay signal Q5 and the third sampling signal Q4 are ored to output a pulse signal sync_flag, and the metastable state detection of the synchronization signal is determined according to the level state of the pulse signal sync_flag.

It should be noted that, the detection method provided by the above embodiment and the detection device provided by the above embodiment belong to the same concept, and the specific manner in which each module and unit perform the operation has been described in detail in the embodiment of the detection device, which is not described herein again. In practical application provided by the above embodiment, the above function allocation may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to perform all or part of the functions described above, which is not limited herein.

An embodiment of the present invention further provides a device for correcting metastable state of a synchronization signal in a clock circuit, where the device includes:

a detection device as shown in fig. 2;

the RS trigger module comprises a first input end S and a second input end R; the first input end S of the RS trigger module is electrically connected with the output end of the OR gate logic module OR, and the second input end R of the RS trigger module is connected with a control signal RST_CTRL; when the pulse signal sync_flag is at a high level, setting a control signal rst_ctrl high so that the pulse signal sync_flag is at a low level; and setting the control signal RST_CTRL to be low, then changing the delay time of the first BUFFER BUFFER1 and the second BUFFER BUFFER2, outputting again, and completing the correction of the synchronizing signal SYNCO when the pulse signal SYNC_FLAG is detected to be low.

Specifically, when the external reading pulse signal sync_flag is high, it indicates that the metastable state is effective, and at this time, the control signal rst_ctrl of the second input terminal R of the RS flip-flop is set high, thereby realizing that the pulse signal sync_flag is reset to low. Then the control signal RST_CTRL is set to be low, then the delay of the synchronizing input signal SYNCIN is changed, the synchronizing signal SYNCIN is output again, when the pulse signal SYNC_FLAG is detected to be low, the condition that the synchronizing signal is prevented from entering a metastable state area is indicated, the output synchronizing signal SYNCO is normal, and the correction of the synchronizing signal is completed.

Referring to fig. 7, fig. 7 is a diagram illustrating a synchronization signal correction method according to an embodiment of the invention, the correction method,

step S710, acquiring a level state of the pulse signal sync_flag;

step S720, when the pulse signal sync_flag is at a high level, setting the control signal rst_ctrl high so that the pulse signal sync_flag is at a low level; and setting the control signal RST_CTRL to be low, then changing the delay time of the first BUFFER BUFFER1 and the second BUFFER BUFFER2, outputting again, and completing the correction of the synchronizing signal SYNCO when the pulse signal SYNC_FLAG is detected to be low.

Specifically, when the external reading pulse signal sync_flag is high, it indicates that the metastable state is effective, and at this time, the control signal rst_ctrl of the second input terminal R of the RS flip-flop is set high, thereby realizing that the pulse signal sync_flag is reset to low. Then the control signal RST_CTRL is set to be low, then the delay of the synchronizing input signal SYNCIN is changed, the synchronizing signal SYNCIN is output again, when the pulse signal SYNC_FLAG is detected to be low, the condition that the synchronizing signal is prevented from entering a metastable state area is indicated, the output synchronizing signal SYNCO is normal, and the correction of the synchronizing signal is completed.

It is noted that the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. Where each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units involved in the embodiments of the present application may be implemented by means of software, or may be implemented by means of hardware, and the described units may also be provided in a processor. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.

It should be further noted that, the foregoing embodiments are constructed based on the same technical concept, and the modules and the steps in the embodiments may be referred to each other.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. It is therefore intended that all equivalent modifications and changes made by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the appended claims.

Claims (8)

1. The device for detecting the metastable state of the synchronous signal in the clock circuit is characterized by being used for detecting the metastable state of the synchronous signal, wherein the synchronous signal is obtained by sampling the first delay signal through a first trigger based on the clock signal, and the first delay signal is obtained by delaying the synchronous input signal through a first buffer; the detection device includes:

the second buffer is used for carrying out delay processing on the first delay signal to obtain a second delay signal;

the front-stage trigger is used for receiving the synchronous input signal and the second delay signal, and respectively sampling the synchronous input signal and the second delay signal based on a clock signal to output a first sampling signal corresponding to the synchronous input signal and a second sampling signal corresponding to the second delay signal;

the exclusive-OR gate logic module is used for carrying out exclusive-OR operation on the first sampling signal and the second sampling signal to obtain a first width pulse signal;

the sampling delayer is used for sampling the first width pulse signal based on the clock signal to obtain a third sampling signal, and performing delay processing on the third sampling signal to obtain a third delay signal;

and the OR gate logic module is used for carrying out OR operation on the third delay signal and the third sampling signal to output a pulse signal, and determining metastable state detection of the synchronous signal according to the level state of the pulse signal.

2. The apparatus for detecting metastable state of a synchronization signal in a clock circuit according to claim 1, wherein the synchronization signal is in a metastable state when the pulse signal is at a high level, and in a steady state when the pulse signal is at a low level.

3. The apparatus for detecting metastable state of synchronous signal in clock circuit according to claim 1, wherein the second buffer comprises a first data input terminal and a first data output terminal, the first data input terminal is electrically connected with the data output terminal of the first buffer, and is connected with a first delay signal; the first data output end is electrically connected with the data input end of the front-stage trigger module and outputs a second delay signal.

4. A device for detecting metastability of a synchronization signal in a clock circuit according to claim 3, wherein said pre-stage flip-flop comprises:

a second flip-flop including a second data input, a second clock input, and a second data output for sampling a second delay signal; the second data input end is electrically connected with the output end of the second buffer and is connected with a second delay signal; the second clock input end is connected with a clock signal, and the second data output end is electrically connected with one data input end of the exclusive-OR gate logic module and outputs a first sampling signal;

the third trigger comprises a third data input end, a third clock input end and a third data output end and is used for sampling the synchronous input signal; the third data input end is connected with a synchronous input signal, and the third clock input end is connected with a clock signal; the third data output end is electrically connected with the other data input end of the exclusive-OR gate logic module and outputs a second sampling signal.

5. The apparatus for detecting metastability of a synchronization signal in a clock circuit according to claim 4, wherein said sample delay comprises:

the fourth trigger comprises a fourth data input end, a fourth clock input end and a fourth data output end and is used for sampling the first width pulse signal; the fourth data input end is electrically connected with the data output end of the exclusive-OR gate logic module and is connected with a first width pulse signal; the fourth clock input end is connected with a clock signal; the fourth data output end is electrically connected with one data input end of the OR gate logic module and outputs a third sampling signal;

the fifth trigger comprises a fifth data input end, a fifth clock input end and a fifth data output end and is used for carrying out delay processing on the third sampling signal; the fifth clock input end is connected with a clock signal; the fifth data input end is electrically connected with the fourth data output end and is connected with a third sampling signal; the fifth data output end is electrically connected with the other data input end of the OR gate logic module and outputs a third delay signal.

6. The method for detecting the metastable state of the synchronous signal in the clock circuit is characterized by comprising the steps of detecting the metastable state of the synchronous signal, wherein the synchronous signal is obtained by sampling the first delay signal through a first trigger based on the clock signal, and the first delay signal is obtained by delaying the synchronous input signal through a first buffer; the detection method comprises the following steps:

performing delay processing on the first delay signal to obtain a second delay signal;

receiving the synchronous input signal and the second delay signal, and respectively sampling the synchronous input signal and the second delay signal based on a clock signal to output a first sampling signal corresponding to the synchronous input signal and a second sampling signal corresponding to the second delay signal;

performing exclusive OR operation on the first sampling signal and the second sampling signal to obtain a first width pulse signal;

sampling the first width pulse signal based on the clock signal to obtain a third sampling signal, and performing delay processing on the third sampling signal to obtain a third delay signal;

and performing OR operation on the third delay signal and the third sampling signal to output a pulse signal, and determining metastable state detection of the synchronous signal according to the level state of the pulse signal.

7. A correction device for metastable state of a synchronizing signal in a clock circuit, the correction device comprising:

the detection device according to any one of claims 1 to 5;

the RS trigger module comprises a first input end and a second input end; the first input end of the RS trigger module is electrically connected with the output end of the OR gate logic module, and the second input end of the RS trigger module is connected with a control signal;

when the pulse signal is at a high level, setting a control signal to be high so as to reset the pulse signal to be at a low level; setting the control signal to be low, then changing the delay time of the first buffer and the second buffer, outputting again, and completing the correction of the synchronous signal when the pulse signal is detected to be low.

8. A synchronization signal correction method based on the correction device according to claim 7, characterized in that the correction method comprises:

acquiring the level state of the pulse signal;

when the pulse signal is at a high level, setting a control signal to be high so as to reset the pulse signal to be at a low level; setting the control signal to be low, then changing the delay time of the first buffer and the second buffer, outputting again, and completing the correction of the synchronous signal when the pulse signal is detected to be low.