CN117558251B

CN117558251B - Driving circuit and control method of display panel, array substrate and display panel

Info

Publication number: CN117558251B
Application number: CN202311816385.4A
Authority: CN
Inventors: 李佳龙
Original assignee: Shenzhen Skyworth Display Technology Co ltd
Current assignee: Shenzhen Skyworth Display Technology Co ltd
Priority date: 2023-12-26
Filing date: 2023-12-26
Publication date: 2024-07-19
Anticipated expiration: 2043-12-26
Also published as: CN117558251A

Abstract

The application discloses a driving circuit and a control method of a display panel, an array substrate and the display panel, and belongs to the technical field of display. The driving circuit of the display panel includes: the first end of the grid driving module is connected with the frame starting signal, the second end of the grid driving module is connected with the clock signal, and the grid driving module is used for transmitting the clock signal under the action of the frame starting signal; one end of the first capacitor is connected with the third end of the grid driving module, the other end of the first capacitor is connected with the public voltage, and the first capacitor is used for reducing the high-low voltage difference when the clock signal changes state; the first end of the data driving module is connected with one end of the first capacitor, the second end of the data driving module is connected with a data driving signal, the third end of the data driving module is connected with a public voltage, and the data driving module is used for driving the liquid crystal to turn over based on the data driving signal and the public voltage so as to display images. The application improves the screen flash phenomenon of the display panel.

Description

Driving circuit and control method of display panel, array substrate and display panel

Technical Field

The embodiment of the application relates to the technical field of display, in particular to a driving circuit and a control method of a display panel, an array substrate and the display panel.

Background

In recent years, with the development of TV (television) industry and the increase of consumer taste demands, the problem of flicker of pictures is also frequently occurring, and currently, methods for solving flicker are known to increase the refresh rate of products or to repeatedly adjust VCOM voltage (common voltage) and GM voltage (gamma voltage) to reduce flicker.

However, if the refresh rate of the product is increased, the hardware needs to be replaced, which increases the cost, and frequently modifying the VCOM voltage and GM voltage is equivalent to redesigning the product driving voltage multiple times, which results in larger workload and lower efficiency.

Disclosure of Invention

The embodiment of the application mainly aims to provide a driving circuit and a control method of a display panel, an array substrate and the display panel, and aims to solve the technical problem of how to reduce cost and improve picture flicker of the display panel.

To achieve the above object, an embodiment of the present application provides a driving circuit of a display panel, including:

The first end of the grid driving module is connected with a frame starting signal, the second end of the grid driving module is connected with a clock signal, and the grid driving module is used for transmitting the clock signal under the action of the frame starting signal;

One end of the first capacitor is connected with the third end of the gate driving module, the other end of the first capacitor is connected with a public voltage, and the first capacitor is used for reducing the high-low voltage difference when the clock signal is in a transition state;

The first end of the data driving module is connected with one end of the first capacitor, the second end of the data driving module is connected with a data driving signal, the third end of the data driving module is connected with the public voltage, and the data driving module is used for driving liquid crystal to turn over based on the data driving signal and the public voltage so as to display images.

Optionally, after the clock signal starts to output the high level or the low level for a first preset duration, the gate driving module is turned off, and the first capacitor maintains the data driving module to be turned on for a second preset duration so as to reduce a high-low voltage difference when the clock signal transitions, thereby reducing a data offset of the data driving signal when the clock signal transitions; and the sum of the first preset time length and the second preset time length is the total time length for continuously outputting high level or low level for the clock signal.

Optionally, the gate driving module includes:

the first end and the controlled end of the first switching tube are connected with the frame starting signal;

one end of the second capacitor is connected with the second end of the first switch tube, and the other end of the second capacitor is connected with one end of the first capacitor;

The first end of the second switching tube is connected with the clock signal, the controlled end of the second switching tube is connected with one end of the second capacitor, and the second end of the second switching tube is connected with the other end of the second capacitor.

Optionally, in the case that the frame start signal is at a high level, the first switch tube is turned on, the second capacitor is charged, and the second switch tube is turned on.

Optionally, the data driving module includes:

one end of the third capacitor is connected with one end of the first capacitor, and the other end of the third capacitor is connected with the data driving signal;

the controlled end of the third switching tube is connected with one end of the third capacitor, and the first end of the third switching tube is connected with the data driving signal;

one end of the fourth capacitor is connected with the controlled end of the third switching tube, and the other end of the fourth capacitor is connected with the second end of the third switching tube;

One end of the fifth capacitor is connected with the other end of the fourth capacitor, the other end of the fifth capacitor is connected with the public voltage, and the fifth capacitor is used for driving the liquid crystal to turn over based on the data driving signal and the public voltage so as to display images;

and one end of the sixth capacitor is connected with one end of the fifth capacitor, and the other end of the sixth capacitor is connected with the other end of the fifth capacitor.

Optionally, after the clock signal starts to output the high level or the low level for a first preset period, the gate driving module is turned off, the first capacitor maintains the third switch tube to be turned on in a second preset period, and the voltage between one end of the fifth capacitor and one end of the sixth capacitor gradually decreases in the second preset period.

Optionally, the driving circuit of the display panel further includes:

and one end of the delay resistor is connected with the clock signal, the other end of the delay resistor is connected with the second end of the grid driving module, and the delay resistor is used for delaying the transmission of the clock signal.

In addition, to achieve the above object, an embodiment of the present application provides a control method applied to a driving circuit of a display panel as described above, including:

Under the condition that the clock signal starts to output high level or low level, controlling the gate driving module to be turned on within a first preset time period, and controlling the gate driving module to be turned off within a second preset time period; and the sum of the first preset time length and the second preset time length is the total time length for continuously outputting high level or low level for the clock signal.

In addition, in order to achieve the above objective, an embodiment of the present application further provides an array substrate, where the array substrate includes an effective display area and an inactive display area, the inactive display area surrounds the periphery of the effective display area, and the driving circuit of the display panel is disposed in the inactive display area of the array substrate.

In addition, to achieve the above object, an embodiment of the present application further provides a display panel including: the liquid crystal display comprises a color film substrate, a liquid crystal layer and the array substrate, wherein the liquid crystal layer is arranged between the array substrate and the color film substrate.

The embodiment of the application provides a driving circuit of a display panel, a control method, an array substrate and the display panel, wherein the driving circuit of the display panel comprises the following components: the first end of the grid driving module is connected with a frame starting signal, the second end of the grid driving module is connected with a clock signal, and the grid driving module is used for transmitting the clock signal under the action of the frame starting signal; one end of the first capacitor is connected with the third end of the gate driving module, the other end of the first capacitor is connected with a public voltage, and the first capacitor is used for reducing the high-low voltage difference when the clock signal is in a transition state; the first end of the data driving module is connected with one end of the first capacitor, the second end of the data driving module is connected with a data driving signal, the third end of the data driving module is connected with the public voltage, and the data driving module is used for driving liquid crystal to turn over based on the data driving signal and the public voltage so as to display images. According to the embodiment of the application, the capacitor is added in the in-plane driving circuit, so that the data volume drift caused by the switching voltage difference can be reduced by reducing the high-low voltage difference when the in-plane driving circuit is switched, the occurrence of the screen flash is avoided, the technical defect that the product refresh rate is required to be improved or the product driving voltage is required to be redesigned for multiple times in the related art is overcome, the improvement cost can be reduced, the repeated workload can be effectively reduced, and the working efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only a part of the embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a driving circuit of a display panel according to an embodiment of the present application;

Fig. 2 is a schematic diagram of a detailed structure of a driving circuit of a display panel according to an embodiment of the present application;

Fig. 3 is a schematic structural diagram of a driving circuit of a display panel according to another embodiment of the present application;

fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present application.

Reference numerals illustrate:

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that embodiments of the application may be practiced in other embodiments, which depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the embodiments of the present application with unnecessary detail.

It should be noted that although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order different from that in the flowchart. The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

It should also be appreciated that references to "one embodiment" or "some embodiments" or the like described in the specification of an embodiment of the present application mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more, but not all, embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

In recent years, with the development of TV industry and the increase of consumer taste, the problem of flicker of pictures is also frequently occurring, and currently, methods for solving flicker are known to increase the refresh rate of products or to repeatedly adjust VCOM voltage and GM voltage to reduce flicker.

Based on the above, the embodiment of the application provides a driving circuit, a control method, an array substrate and a display panel of the display panel, in the driving circuit of the display panel, the embodiment of the application can reduce the data volume drift caused by the switching voltage difference by reducing the switching voltage difference of the in-plane driving circuit by adding a capacitor in the in-plane driving circuit, thereby avoiding the occurrence of a flash screen, overcoming the technical defect that the refresh rate of a product needs to be improved or the driving voltage of the product needs to be redesigned for many times in the related art, not only reducing the improvement cost, but also effectively reducing the repeated workload and improving the working efficiency.

The embodiment of the application provides a driving circuit of a display panel, a control method, an array substrate and the display panel, and specifically, the following embodiment is used for explaining, first, the driving circuit of the display panel in the embodiment of the application.

An embodiment of the present application provides a driving circuit of a display panel, referring to fig. 1, fig. 1 is a schematic structural diagram of the driving circuit of the display panel according to an embodiment of the present application, where in the embodiment, the driving circuit of the display panel includes:

the gate driving module 10, a first end of the gate driving module 10 is connected to the frame start signal STV, a second end of the gate driving module 10 is connected to the clock signal CK, and the gate driving module 10 is used for transmitting the clock signal CK under the action of the frame start signal STV;

One end of the first capacitor C1 is connected with the third end of the gate driving module 10, the other end of the first capacitor C1 is connected with the common voltage VCOM, and the first capacitor C1 is used for reducing the high-low voltage difference when the clock signal CK turns;

the first end of the DATA driving module 20 is connected to one end of the first capacitor C1, the second end of the DATA driving module 20 is connected to the DATA driving signal DATA, the third end of the DATA driving module 20 is connected to the common voltage VCOM, and the DATA driving module 20 is used for driving the liquid crystal to turn over based on the DATA driving signal DATA and the common voltage VCOM to display images.

In this embodiment, only a part of the driving circuit of the display panel is shown, the gate driving module may further include a longitudinally extending switching tube, and the driving circuit of the display panel may further include a plurality of parallel DATA lines and corresponding DATA driving modules 20, which may be extended with reference to the in-plane driving circuit commonly used in the related art, and all fall within the protection scope of this embodiment.

In this embodiment, the gate driving module 10 may be turned on and transmit the clock signal CK to the first capacitor C1 and the data driving module 20 under the action of the frame start signal STV, or may be turned off and stop transmitting the clock signal CK to the first capacitor C1 and the data driving module 20 under the action of the frame start signal STV, and whether the gate driving module 10 can transmit the clock signal CK may be determined by the combined control of the frame start signal STV and the switch, which is not limited in this embodiment.

In this embodiment, the first capacitor C1 may be a storage capacitor, or may be other components with similar functions, which is not limited in this embodiment.

In some possible embodiments, after the clock signal CK starts to output the high level or the low level for the first preset period, the gate driving module 10 is turned off, and the first capacitor C1 maintains the DATA driving module 20 turned on for the second preset period to reduce the high-low voltage difference when the clock signal CK transitions, so as to reduce the DATA offset of the DATA driving signal DATA when the clock signal CK transitions; and the sum of the first preset time length and the second preset time length is the total time length for continuously outputting the high level or the low level for the clock signal.

In the present embodiment, the switching transition of the clock signal CK refers to an instantaneous state at the time when the clock signal CK transitions from the output high level VGH to the output low level VGL or from the output low level VGL to the output high level VGH.

In the related art, when the clock signal CK is turned on or off, the DATA driving signal DATA is caused to drift, for example, the voltage fluctuates by about 1V, and the voltage fluctuation of about 1V causes the difference between the DATA driving signal DATA and the common voltage VCOM, that is, the liquid crystal deflection voltage, to become larger than the threshold range, so that the flicker phenomenon occurs, and therefore, the present embodiment aims to reduce the voltage fluctuation, so that the liquid crystal deflection voltage does not exceed the threshold range even if the fluctuation occurs, so as to improve the flicker phenomenon.

In the present embodiment, since the DATA offset of the DATA driving signal DATA when the clock signal CK is turned on or off changes along with the voltage difference of the voltage of the DATA driving module 20 affected by the clock signal, the conventional mode of the DATA driving module 20 continuously receiving the clock signal CK is changed. As an example, in the case that the timing of the clock signal CK is not changed (i.e., the time period in which the clock signal CK outputs the high level VGH and the low level VGL is consistent and alternately output), taking the high level VGH as an example, the embodiment turns on the gate driving module 10 only in the first preset time period t1 after the clock signal CK starts to output the high level VGH, so that the DATA driving module 20 is directly affected by the clock signal CK, and in the second preset time period t2 after t1, the DATA driving module 20 is discharged through the first capacitor C1 to gradually reduce the voltage amplitude in the DATA driving module 20 that is originally consistent with the clock signal CK, for example, from VGH to VGHL, so that when the clock signal CK switches to a state after t2, the voltage difference in the DATA driving module 20 that is changed is no longer consistent with the clock signal CK, but is VGHL-VGL, and VGHL-VGL is obviously smaller than VGH-VGL, that is capable of reducing the voltage difference when the DATA driving module 20 switches to a high state, for example, when the clock signal CK switches to a low state, the DATA driving circuit of the display panel provided in the embodiment can reduce the voltage difference, for example, from the left to the low voltage, and the DATA voltage is further reduced, and the voltage difference is reduced from the left to the right voltage to the left voltage when the original voltage is more than 0.

Referring to fig. 2, in some possible embodiments, the gate driving module 10 includes:

The first end and the controlled end of the first switching tube T1 are connected with a frame start signal STV;

one end of the second capacitor C2 is connected with the second end of the first switch tube T1, and the other end of the second capacitor C2 is connected with one end of the first capacitor C1;

the first end of the second switching tube T2 is connected with the clock signal CK, the controlled end of the second switching tube T2 is connected with one end of the second capacitor C2, and the second end of the second switching tube T2 is connected with the other end of the second capacitor C2.

In this embodiment, the first end and the controlled end of the first switching tube T1 correspond to the first end of the gate driving module 10, and the first end of the second switching tube T2 is connected to the clock signal CK corresponds to the second end of the gate driving module 10.

In this embodiment, the first switching tube T1 and the second switching tube T2 may be TFT switches, or may be other switching tubes with similar functions, and the second capacitor C2 may be a storage capacitor, or may be other components with similar functions.

In some possible embodiments, when the frame start signal STV is at a high level, the first switch T1 is turned on, the second capacitor C2 is charged, and the second switch T2 is turned on.

In the present embodiment, the second switching tube T2 is turned on, and the clock signal CK can be transmitted to the first capacitor C1 and the data driving module 20.

Referring to fig. 2, in some possible embodiments, the data driving module 20 includes:

One end of the third capacitor C3 is connected with one end of the first capacitor C1, and the other end of the third capacitor C3 is connected with the DATA driving signal DATA;

The controlled end of the third switching tube T3 is connected with one end of the third capacitor C3, and the first end of the third switching tube T3 is connected with the DATA driving signal DATA;

one end of the fourth capacitor C4 is connected with the controlled end of the third switching tube T3, and the other end of the fourth capacitor C4 is connected with the second end of the third switching tube T3;

one end of the fifth capacitor C5 is connected with the other end of the fourth capacitor C4, the other end of the fifth capacitor C5 is connected with the common voltage VCOM, and the fifth capacitor C5 is used for driving the liquid crystal to turn over based on the DATA driving signal DATA and the common voltage VCOM so as to display images;

and one end of the sixth capacitor C6 is connected with one end of the fifth capacitor C5, and the other end of the sixth capacitor C6 is connected with the other end of the fifth capacitor C5.

In this embodiment, one end of the third capacitor C3, the controlled end of the third switching tube T3, and one end of the fourth capacitor C4 correspond to the first end of the data driving module 20, the other end of the third capacitor C3 and the first end of the third switching tube T3 correspond to the second end of the data driving module 20, and the other end of the fifth capacitor C5 and the other end of the sixth capacitor C6 correspond to the third end of the data driving module 20.

In this embodiment, the third switching tube T3 may be a TFT switch, or may be another switching tube with similar functions, the third capacitor C3 and the fourth capacitor C4 may be TFT parasitic capacitors, or may be other components with similar functions, the fifth capacitor C5 may be a liquid crystal capacitor, or may be other components with similar functions, and the sixth capacitor C6 may be a storage capacitor with a large capacity, or may be other components with similar functions, which is not limited in this embodiment.

In some possible embodiments, after the clock signal CK starts to output the high level or the low level for the first preset period, the gate driving module 10 is turned off, the first capacitor C1 maintains the third switching transistor T3 turned on for the second preset period, and the voltage between one end of the fifth capacitor C5 and one end of the sixth capacitor C6 gradually decreases for the second preset period.

In this embodiment, when the clock signal CK switches, the on/off of the third switching transistor T3 and the voltage at the Q point between one end of the fifth capacitor C5 and one end of the sixth capacitor C6 are affected.

As an example, in the related art, when the CK signal is at the high level VGH, T3 is turned on, DATA enters the liquid crystal capacitor C5 through T3, and a voltage difference is formed with VCOM to drive the liquid crystal to flip, thereby displaying an image; when the CK signal is at a low level VGL, T3 is turned off, and C6 continuously supplies power to C5 to ensure image display; when the CK signal turns from VGH to VGL, the potential drift of the Q point is caused, the DATA signal drift and CFcom differential pressure change are caused, the liquid crystal turns, and the bright and dark changes appear in the phenomenon of screen flashing; in the embodiment, a first capacitor C1 is added to change the continuous access time of the CK signal, and the DATA drift amount formula of the Q point is usedIt is known that reducing the CK high-level transition voltage, for example, from original VGH to VGHL, can change VGH-VGL to VGHL-VGL, and further reduce the Q-point drift, and when the Q-point drift is reduced, the pressure difference variation between DATA and VCOM is reduced, so that the liquid crystal is turned over and the screen brightness variation is reduced, thereby achieving the effect of improving the flash screen.

As an example, when the CK signal instantaneously changes, the voltage difference between DATA and VCOM is reduced because C4 causes the Q point potential to drop and C1 causes the VCOM voltage to drop, so that the flicker can also be improved.

In some possible embodiments, the Q-point drift amount can be further reduced by adjusting the VGH-VGL pressure difference, C4, C5, and C6 according to the Q-point drift amount calculation formula, so as to improve the splash screen.

Referring to fig. 3, in some possible embodiments, the driving circuit of the display panel further includes:

And one end of the delay resistor R is connected with the clock signal CK, the other end of the delay resistor R is connected with the second end of the grid driving module 10, and the delay resistor R is used for delaying the transmission of the clock signal CK.

In this embodiment, a delay resistor R between the clock signal CK and the gate driving module 10 may be added to the driving circuit of the display panel provided in the above embodiments, and by connecting a delay resistor in series, the voltage difference between the high voltage and the low voltage when the clock signal CK is turned on and turned off can be further optimized, so that the DATA offset of the DATA driving signal DATA when the clock signal CK is turned on can be further reduced.

The embodiment of the application provides a driving circuit of a display panel, which can reduce the data volume drift caused by switching voltage difference by reducing the high-low voltage difference when the in-plane driving circuit is switched on and off by adding a capacitor in the in-plane driving circuit, thereby avoiding the occurrence of screen flash, overcoming the technical defect that the refresh rate of a product needs to be improved or the driving voltage of the product needs to be designed for many times in the related art, reducing the improvement cost, effectively reducing the repeated workload and improving the working efficiency.

In addition, an embodiment of the present application further provides a control method, where the control method is applied to the driving circuit of the display panel provided in any one of the foregoing embodiments, and the control method includes:

Step S10, under the condition that the clock signal starts to output high level or low level, the gate driving module is controlled to be turned on within a first preset time period, and the gate driving module is controlled to be turned off within a second preset time period; and the sum of the first preset time length and the second preset time length is the total time length for continuously outputting the high level or the low level for the clock signal.

In this embodiment, the gate driving module in the driving circuit of the display panel may be controlled to be turned on or off by changing the frame start signal, or may be controlled to be turned on or off by continuously outputting a high-level frame start signal, but a grounding switch is added, or may be controlled to be turned on or off by other suitable manners, so long as the gate driving module is controlled to be turned on within a first preset duration and the gate driving module is controlled to be turned off within a second preset duration in a half-level period of the clock signal.

In this embodiment, the effect equivalent to the above steps may be achieved by changing the timing sequence of the clock signal without changing the on/off state of the gate driving module, for example, the gate driving module is kept on, but the clock signal is controlled to continuously output a high level or a low level for a first preset period of time, and then the clock signal is controlled not to output for a second preset period of time, so long as the voltage given by the clock signal in the data driving module can be gradually adjusted through the first capacitor within the second preset period of time.

The control method provided in this embodiment is applied to the driving circuit of the display panel provided in the foregoing embodiment, and all the technical solutions of the foregoing embodiments are adopted and belong to the same technical concept, so this embodiment at least has all the beneficial effects brought by the technical solutions of the foregoing embodiments, which are not described in detail herein.

In addition, referring to fig. 4, in this embodiment, the array substrate includes an effective display area 101 and an inactive display area, where the inactive display area surrounds the periphery of the effective display area 101, and the driving circuit 102 of the display panel is disposed in the inactive display area of the array substrate.

The specific structure of the driving circuit 102 of the display panel in this embodiment refers to the above embodiment, and since the array substrate provided in this embodiment adopts all the technical solutions of the driving circuit of the display panel provided in the above embodiment, and belongs to the same technical concept, this embodiment at least has all the beneficial effects brought by the technical solutions of the above embodiment, which are not described in detail herein.

In addition, referring to fig. 5, the display panel further includes an array substrate 100, a color film substrate 200, and a liquid crystal layer 300, where the liquid crystal layer 300 is disposed between the array substrate 100 and the color film substrate 200.

As an example, the display panel In the present embodiment may be a TN (TWISTED NEMATIC ) display panel, an IPS (In-PLANE SWITCHING ) display panel, a VA (VERTICAL ALIGNMENT ) display panel, an MVA (Multi-Domain VERTICAL ALIGNMENT ) display panel, but may be other types of display panels, such as an OLED (organic light-Emitting Diode) display panel.

As an example, the display panel may be applied to a display device, which may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

It will be appreciated by those skilled in the art that the structure shown in fig. 5 is not limiting of the display device and may include more or fewer components than shown, or may combine certain components, or may be arranged in different components.

The specific structure of the array substrate 100 in this embodiment refers to the foregoing embodiments, and since the display panel provided in this embodiment adopts all the technical solutions of all the foregoing embodiments, and belongs to the same technical concept, this embodiment at least has all the beneficial effects brought by the technical solutions of the foregoing embodiments, which are not described in detail herein.

It should be noted that the technical solutions of the various embodiments of the present application may be combined with each other, but it is necessary to be based on the fact that those skilled in the art can implement the present application, and when the combination of the technical solutions contradicts or cannot be implemented, it should be considered that the combination of the technical solutions does not exist and is not within the scope of protection claimed by the present application.

The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the application.

Claims

1. A driving circuit of a display panel, characterized in that the driving circuit of the display panel comprises:

the first end of the data driving module is connected with one end of the first capacitor, the second end of the data driving module is connected with a data driving signal, the third end of the data driving module is connected with the public voltage, and the data driving module is used for driving liquid crystal to turn over based on the data driving signal and the public voltage so as to display images;

after the clock signal starts to output high level or low level for a first preset time period, the gate driving module is turned off, and the first capacitor keeps the data driving module on in a second preset time period so as to reduce the high-low voltage difference when the clock signal is turned to a state, and further reduce the data offset of the data driving signal when the clock signal is turned to a state; and the sum of the first preset time length and the second preset time length is the total time length for continuously outputting high level or low level for the clock signal.

2. The driving circuit of the display panel according to claim 1, wherein the gate driving module comprises:

3. The driving circuit of the display panel according to claim 2, wherein the first switching tube is turned on, the second capacitor is charged, and the second switching tube is turned on in a case that the frame start signal is at a high level.

4. The driving circuit of the display panel according to claim 1, wherein the data driving module comprises:

5. The driving circuit of the display panel according to claim 4, wherein the gate driving module is turned off after the clock signal starts outputting the high level or the low level for a first preset time period, the first capacitor maintains the third switching tube to be turned on for a second preset time period, and a voltage between one end of the fifth capacitor and one end of the sixth capacitor gradually decreases for the second preset time period.

6. The drive circuit of a display panel according to any one of claims 1 to 5, wherein the drive circuit of the display panel further comprises:

7. A control method, characterized in that the control method is applied to the drive circuit of the display panel according to any one of claims 1 to 6, comprising:

8. An array substrate, wherein the array substrate comprises an effective display area and an inactive display area, the inactive display area surrounds the periphery of the effective display area, and the driving circuit of the display panel according to any one of claims 1 to 6 is disposed in the inactive display area of the array substrate.

9. A display panel, the display panel comprising: the color film substrate, the liquid crystal layer and the array substrate as claimed in claim 8, wherein the liquid crystal layer is arranged between the array substrate and the color film substrate.