CN117524284B - Programming verification voltage setting method, programming method, device, chip and equipment - Google Patents
Programming verification voltage setting method, programming method, device, chip and equipment Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention relates to the technical field of memory chips, and particularly discloses a programming verification voltage setting method, a programming method, a device, a chip and equipment, wherein the programming verification voltage setting method comprises the following steps: acquiring a threshold voltage of a target storage area after an erasing operation is performed; acquiring a voltage difference value according to the initial threshold voltage of the target storage area and the threshold voltage; setting a programming verification voltage according to the voltage difference and the initial programming verification voltage; the programming verification voltage setting method utilizes the threshold voltage and the initial threshold voltage to calculate and obtain a voltage difference value capable of independently representing the electron capturing capability of the tunneling oxide layer, and adjusts and sets the programming verification voltage according to the voltage difference value so as to accurately judge whether the programming operation of the memory cell is qualified or not and avoid the weak 0 state of the programmed memory cell after a period of time.
Description
Technical Field
The present disclosure relates to the field of memory chips, and in particular, to a program verification voltage setting method, a program verification voltage setting device, a chip, and a device.
Background
The nor flash stores data using a memory cell that stores data 1 or data 0 in the magnitude of a threshold voltage.
The data retention capacity of the memory cell may be deteriorated in the later stage of use, mainly because: the tunneling oxide layer of the memory cell has a card electron phenomenon when the programming operation is performed, namely, redundant unstable electrons are captured, so that after the memory cell is qualified in programming verification, the problem of threshold voltage reduction caused by release of the unstable electrons is caused, and the programmed memory cell has a weak 0 state after a period of time.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The application aims to provide a programming verification voltage setting method, a programming device, a chip and equipment, so as to accurately judge whether programming operation of a memory cell is qualified or not and avoid a weak 0 state of the programmed memory cell after a period of time.
In a first aspect, the present application provides a program verify voltage setting method, applied to a programming operation of a nor flash, where the program verify voltage setting method includes the following steps:
acquiring a threshold voltage of a target storage area after an erasing operation is performed;
acquiring a voltage difference value according to the initial threshold voltage of the target storage area and the threshold voltage;
and setting a programming verification voltage according to the voltage difference value and the initial programming verification voltage.
According to the programming verification voltage setting method, the threshold voltage of the obtained target storage area after the erasing operation is executed can represent the electron capturing capability of the tunneling oxide layer and the floating gate superposition of the storage unit, the threshold voltage and the initial threshold voltage are utilized for calculation to obtain the voltage difference value capable of independently representing the electron capturing capability of the tunneling oxide layer, and the programming verification voltage is adjusted and set according to the voltage difference value so as to accurately judge whether the programming operation of the storage unit is qualified or not, and the weak 0 state of the storage unit after programming is avoided after the storage unit is placed for a period of time.
The programming verification voltage setting method is triggered to be executed when the cycle times of the target storage area reach a preset cycle times threshold value so as to update the programming verification voltage.
The programming verification voltage setting method is triggered when the cycle times of the target storage area reach a preset cycle times threshold value so as to update and set the programming verification voltage in a staged mode.
The program verify voltage setting method, wherein the cycle number threshold is one or more of 30000, 50000, 70000 and 90000.
The program verify voltage setting method, wherein the step of setting the program verify voltage according to the voltage difference and the initial program verify voltage includes:
and setting a programming verification voltage according to the product of the voltage difference and a correction coefficient and the initial programming verification voltage, wherein the correction coefficient is set according to the electron concentration relation between the programming operation and the erasing operation of the nor flash.
The program verification voltage setting method includes that the threshold voltage is an average threshold voltage of all memory cells of the target memory area after the erasing operation is executed, or is an intermediate threshold voltage of the target memory area after the erasing operation is executed, or is a maximum threshold voltage of the target memory area after the erasing operation is executed, or is a minimum threshold voltage of the target memory area after the erasing operation is executed, or is an average value of the maximum threshold voltage and the minimum threshold voltage, or is an average value of the maximum threshold voltage, the minimum threshold voltage and the intermediate threshold voltage.
The programming verification voltage setting method is characterized in that the target storage area comprises a plurality of storage arrays or a plurality of blocks or a plurality of sectors.
In a second aspect, the present application also provides a programming method including the steps of:
performing programming operation on target memory cells in the target memory area;
verifying the program data of the target memory cell according to the program verify voltage set by the program verify voltage setting method as provided in the first aspect.
According to the programming method, the programming data of the target memory cell is verified by using the programming verification voltage set by the programming verification voltage setting method provided by the first aspect, the influence of the electron capturing capability of the tunneling oxide layer on the threshold voltage of the target memory cell can be fully considered, so that the memory cell qualified in programming verification cannot be in a weak 0 state after being placed for a period of time, and the memory cell has good data holding capability.
In a third aspect, the present application further provides a program verify voltage setting device, applied to a programming operation of a nor flash, where the program verify voltage setting device includes:
the acquisition module is used for acquiring the threshold voltage of the target storage area after the erasing operation is performed;
the calculation module is used for obtaining a voltage difference value according to the initial threshold voltage of the target storage area and the threshold voltage;
and the setting module is used for setting the programming verification voltage according to the voltage difference value and the initial programming verification voltage.
According to the programming verification voltage setting device, the threshold voltage of the obtained target storage area after the erasing operation is executed can represent the electron capturing capability of the tunneling oxide layer and the floating gate superposition of the storage unit, the threshold voltage and the initial threshold voltage are utilized to calculate and obtain the voltage difference value capable of independently representing the electron capturing capability of the tunneling oxide layer, and the programming verification voltage is adjusted and set according to the voltage difference value, so that whether the programming operation of the storage unit is qualified or not is accurately judged, and the weak 0 state of the storage unit after programming is avoided after the storage unit is placed for a period of time.
In a fourth aspect, the present application also provides a memory chip including a control circuit and a memory array, the memory chip setting a program verify voltage for verifying program data in the memory array based on the control circuit operating the program verify voltage setting method as provided in the first aspect.
In a fifth aspect, the present application also provides an electronic device comprising a memory chip as provided in the fourth aspect.
As can be seen from the foregoing, the present application provides a program verify voltage setting method, a program method, an apparatus, a chip, and a device, where the program verify voltage setting method of the present application, the threshold voltage of an obtained target storage area after performing an erase operation represents an electron capturing capability of a tunneling oxide layer and a floating gate of a storage unit, calculates and obtains a voltage difference value capable of independently representing the electron capturing capability of the tunneling oxide layer by using the threshold voltage and an initial threshold voltage, and adjusts the program verify voltage by using the voltage difference value, so as to accurately determine whether the program operation of the storage unit is qualified, and avoid a weak 0 state after a period of storage unit after programming is placed.
Drawings
Fig. 1 is a flowchart of a program verify voltage setting method according to an embodiment of the present application.
Fig. 2 is a flowchart of a programming method provided in an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a programming verification voltage setting device according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a memory cell.
Reference numerals: 301. an acquisition module; 302. a computing module; 303. and setting a module.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 4, the conventional nor flash uses a MOS transistor as a memory cell, and a Tunnel oxide layer (Tunnel Ox) is disposed between a P substrate and a Floating Gate (Floating Gate), and the memory cell changes the electron binding amount in the Floating Gate by an external input voltage (such as an erase voltage and a program voltage) to change the threshold voltage (Vth) of the MOS transistor, so as to change the value of the stored data; as the erasing and programming times of the memory cell increase, more positive holes appear in the tunneling oxide layer, and each time the memory cell performs erasing or programming operation, the positive holes capture electrons to form an unstable state, and after the erasing or programming is finished, the electrons in the unstable state are gradually released or gradually diffused to other places to gradually lose the electrons in the tunneling oxide layer; the memory cell generally judges the number of electrons in the floating Gate to realize data reading based on the application of a read voltage to a Control Gate (Control Gate), and the specific process is to judge whether the data stored in the memory cell is 1 or 0 by judging the magnitude of the output current of the source and the drain; when the number of cycles is large enough in the later life of the nor flash, the tunneling oxide layer of the memory cell has too many holes, so that the difference of the number of electrons in the tunneling oxide layer is too large when the programming of the memory cell is completed and after a period of time is completed, the threshold voltage of the memory cell at the later time is obviously reduced (electrons are reduced), thus the retention capacity of the programmed data 0 of the memory cell is obviously deteriorated, but the retention capacity is actually caused by carrying out integral threshold voltage verification on electrons in an unstable state captured in the tunneling oxide layer in a programming verification stage, namely, the existing programming verification method is equivalent to considering all electrons captured by the tunneling oxide layer and a floating gate as the data storage capacity of the memory cell, and the data storage capacity of the memory cell is actually only embodied as the capacity of the floating gate to bind electrons; the problem of threshold voltage deviation caused by the tunneling oxide layer is also a main reason for the reduced erasing performance (more difficult to erase and easier to program) of the non flash in the later period of life.
In a first aspect, referring to fig. 1, some embodiments of the present application provide a program verify voltage setting method, which is applied to a programming operation of a nor flash, and includes the following steps:
s1, acquiring threshold voltage of a target storage area after an erasing operation is executed;
s2, acquiring a voltage difference value according to the initial threshold voltage of the target storage area and the threshold voltage;
s3, setting a programming verification voltage according to the voltage difference value and the initial programming verification voltage.
Specifically, for the same memory cell, in one cycle (also called P/E cycle), the ability of the tunnel oxide to capture electrons can be regarded as uniform (because positive holes are generated more slowly), and in both erase operation and program operation, the positive holes in the tunnel oxide capture enough electrons, so that in one cycle, the threshold voltage deviation caused by the tunnel oxide is substantially uniform in both types of operation; the program verification voltage setting method in the embodiment of the application mainly dynamically sets a new program verification voltage by acquiring the influence of the threshold voltage estimation tunneling oxide layer after the erase operation on the threshold voltage of the memory cell, so as to ensure that the memory cell is programmed to an expected state exactly.
More specifically, the target storage area is a storage area where an object to be subjected to a program verification process operation or a program operation is located, and the object may be a single or a plurality of storage units requiring a program operation; the target storage area may be constituted in units of sectors, blocks, or the like, and in the embodiment of the present application, it is preferable that a processing unit corresponding to an erase operation; the programming operation is a process of programming data 1 of a specific position and a number of memory cells in a target memory area into data 0 according to operation requirements, and the erasing operation is a process of pre-programming data in all memory cells in the target memory area into data 0 and then completely erasing the data into data 1, so that the number of cycles of corresponding levels of different memory cells in the same target memory area is equal, and the method of the embodiment of the invention can estimate the capability of capturing electrons of a tunneling oxide layer of an object according to the threshold voltage of the target memory area after the erasing operation is executed; it should be noted that, in the embodiment of the present application, the threshold voltage obtained in step S1 is the average threshold voltage of all the memory cells or part of the memory cells in the target memory area, so as to represent the capability of capturing electrons of the tunnel oxide layer of the memory cells in the whole target memory area, so as to ensure that the voltage difference obtained by calculating the threshold voltage is representative and universal, and can represent the universal deviation condition of the threshold voltage of the memory cells in the target memory area.
More specifically, the initial threshold voltage is a threshold voltage value determined when the memory cell in the nor flash is in an initial good state, may be an average threshold voltage when the corresponding target memory area is in an initial good state, or may be a threshold voltage value determined when the memory cell of the memory array of the entire nor flash is in an initial good state, and in this embodiment, the former is preferred, where the initial threshold voltage may be a threshold voltage determined based on recording based on a single or multiple erasure verification tests, and may accurately reflect the original data retention capability of the memory cell in the target memory area.
More specifically, based on the foregoing, it can be known that the problem of deviation of the threshold voltage caused by the tunneling oxide layer is also a main cause of causing the reduction of the erasing performance of the nor flash in the later period of life, so as to accurately reflect the influence of the capability of capturing electrons of the tunneling oxide layer on the threshold voltage, the nor flash applied in the method according to the embodiment of the present application preferably always uses an erase voltage with a specific magnitude to complete the erase operation, so that the threshold voltage obtained in the step S1 can be compared with the initial threshold voltage used as a reference, so as to accurately obtain the capability of the tunneling oxide layer to influence the threshold voltage, that is, the voltage difference obtained in the step S2 characterizes the electron quantity temporarily captured by the tunneling oxide layer, and simultaneously characterizes the maximum release electric quantity of the tunneling oxide layer.
More specifically, the initial program verify voltage is a program verify voltage set by the nor flash according to the usage specification, for verifying whether the threshold voltage of the program object reaches a preset value.
More specifically, the process of setting the program verify voltage according to the voltage difference and the initial program verify voltage in step S3 may be a process of numerical value superposition, or may be a process of correcting the initial verify voltage according to the voltage difference converted into specific compensation data to set the program verify voltage; in general, the value of the program verify voltage set in this step is higher than the initial program verify voltage, which considers electrons which are trapped in the tunnel oxide layer and are not related to the data retention capability of the memory cell, so as to verify the program data of the memory cell, so that the threshold voltage of the memory cell passing the program verify is still maintained above the preset value after all electrons are released from the tunnel oxide layer, and the threshold voltage is not converted into a weak 0 state, thereby ensuring the stability of data storage.
According to the programming verification voltage setting method, the threshold voltage of the obtained target storage area after the erasing operation is executed can represent the electron capturing capability of the tunneling oxide layer and the floating gate superposition of the storage unit, the threshold voltage and the initial threshold voltage are utilized for calculation to obtain the voltage difference value capable of representing the electron capturing capability of the tunneling oxide layer independently, and the programming verification voltage is adjusted and set according to the voltage difference value, so that whether the programming operation of the storage unit is qualified or not is accurately judged, and the situation that the storage unit after programming is placed for a period of time and then is in a weak 0 state is avoided.
The weak 0 state is a state in which the threshold voltage of the memory cell is slightly lower than or near the lower threshold voltage of data 0.
In some preferred embodiments, the program verify voltage setting method of the embodiments triggers execution to update the program verify voltage when the cycle number of the target storage area reaches a preset cycle number threshold.
Specifically, as the process of generating positive charges on the tunneling oxide layer is slower, the quantity of electrons captured by the tunneling oxide layer of the memory cell between programming operations of similar rounds is similar, if the programming verification voltage is updated and set frequently, the operation efficiency of the chip is affected; therefore, the program verify voltage setting method in the embodiment of the application triggers when the cycle number of the target storage area reaches the preset cycle number threshold value, so as to update the set program verify voltage in a staged manner.
More specifically, the preset cycle number threshold may be one value or a plurality of values; when the preset cycle number threshold is a plurality of values, the method of the embodiment of the application can update the programming verification voltage for a plurality of times according to different using degrees of the nor flash, so that the threshold voltage of the memory cell which is subjected to programming can be accurately verified at different stages, and the memory cell is ensured to be programmed to an expected state exactly.
In some preferred embodiments, the cycle number threshold is one or more of 30000, 50000, 70000, and 90000.
Specifically, the life cycle of the nor flash is generally more than 10 ten thousand times, that is, the number of erasable times corresponding to each memory area and each memory unit is also more than 10 ten thousand times, so that the update time of the programming verification voltage is set according to a plurality of key time points of the life cycle.
More specifically, in the embodiment of the present application, the cycle number threshold is preferably 50000, 70000, and 90000; generally, the memory cell will not have obvious card electrons (i.e. fewer holes generated by the tunnel oxide layer) during initial use, so the method of the embodiment of the present application does not need to update the program verify voltage in the early stage of the life cycle, but resets the appropriate program verify voltage with 20000 cycles as the update interval in the middle and later stages of the life cycle.
In some preferred embodiments, the step of setting the program verify voltage according to the voltage difference and the initial program verify voltage includes:
the program verification voltage is set according to the product of the voltage difference and the correction coefficient and the initial program verification voltage, and the correction coefficient is set according to the electron concentration relation between the programming operation and the erasing operation of the nor flash.
Specifically, based on the foregoing, it can be seen that the threshold voltage deviation caused by the tunneling oxide layer in the erase operation and the program operation is basically consistent, but there is a certain difference, which is related to the manufacturing process of the MOS transistor, so that the tunneling oxide layer has slightly different capturing capability for electrons under different electron concentrations.
More specifically, in the present embodiment, the program verify voltage is denoted as PV, and then PV satisfies:
PV=PVi+α·△eV （1）
PVi is initial programming verification voltage, alpha is correction coefficient, and delta eV is voltage difference.
In some preferred embodiments, the correction factor is 0.9-1.1; and if the correction coefficient obtained by experimental test exceeds the range, other quality problems of the nor flash can be considered.
In some preferred embodiments, the threshold voltage obtained in step S1 is an average threshold voltage of all memory cells of the target memory area after performing the erase operation, or is an intermediate threshold voltage of the target memory area after performing the erase operation, or is a maximum threshold voltage of the target memory area after performing the erase operation, or is a minimum threshold voltage of the target memory area after performing the erase operation, or is an average of the maximum threshold voltage and the minimum threshold voltage, or is an average of the maximum threshold voltage, the minimum threshold voltage, and the intermediate threshold voltage.
Specifically, in the embodiment of the present application, the threshold voltage obtained in step S1 is preferably the middle threshold voltage of the target memory area after the erasing operation is performed, that is, the threshold voltage of all the memory cells in the area that is at the middle value; in general, the threshold voltages of the memory cells in one region have a normal distribution characteristic, so that the intermediate threshold voltage can represent the average threshold voltage of the target memory region, and the method of the embodiment of the application adopts the intermediate threshold voltage as the threshold voltage of the step S1, so that the analysis process of the step S1 can be effectively simplified.
In some preferred embodiments, the target storage area comprises several storage arrays or several blocks or several sectors.
Specifically, in the embodiment of the present application, the target storage area is preferably a single sector, so that the use condition of each sector is recorded separately to update and set a proper programming verification voltage; the sector is the minimum unit of the erasing operation in the nor flash, all the memory cells in the sector have the same cycle times, and the set programming verification voltage can be accurately applied to all the memory cells in the target memory area.
In a second aspect, referring to fig. 2, some embodiments of the present application further provide a programming method, where the programming method includes the following steps:
a1, performing programming operation on a target storage unit in a target storage area;
a2, verifying the program data of the target memory cell according to the program verification voltage set by the program verification voltage setting method as provided in the first aspect.
It should be noted that if the verification in step A2 is not passed, A1 is returned to continue programming the target memory cell until the target memory cell passes the verification in step A2 or the maximum number of times of programming is exceeded.
Specifically, the target memory cell is a memory cell whose stored data is programmed from data 1 to data 0 using a programming operation.
According to the programming method, the programming data of the target memory cell is verified by using the programming verification voltage set by the programming verification voltage setting method provided by the first aspect, the influence of the electron capturing capability of the tunneling oxide layer on the threshold voltage of the target memory cell can be fully considered, so that the memory cell qualified in programming verification cannot be in a weak 0 state after being placed for a period of time, and the memory cell has good data holding capability.
In a third aspect, referring to fig. 3, some embodiments of the present application further provide a program verification voltage setting device, which is applied to a programming operation of a nor flash, where the program verification voltage setting device includes:
an acquisition module 301, configured to acquire a threshold voltage of a target storage area after performing an erase operation;
a calculation module 302, configured to obtain a voltage difference according to an initial threshold voltage of the target storage area and the threshold voltage;
the setting module 303 is configured to set the program verify voltage according to the voltage difference and the initial program verify voltage.
According to the programming verification voltage setting device, the threshold voltage of the obtained target storage area after the erasing operation is performed can represent the electron capturing capability of the tunneling oxide layer and the floating gate of the storage unit, the threshold voltage and the initial threshold voltage are utilized to calculate and obtain the voltage difference value which can independently represent the electron capturing capability of the tunneling oxide layer, and the programming verification voltage is adjusted and set according to the voltage difference value, so that whether the programming operation of the storage unit is qualified or not is accurately judged, and the situation that the storage unit after programming is placed for a period of time and then is in a weak 0 state is avoided.
In some preferred embodiments, the program-verify voltage setting device of the embodiments of the present application is configured to perform the program-verify voltage setting method provided in the first aspect.
In a fourth aspect, some embodiments of the present application further provide a memory chip including a control circuit and a memory array, the memory chip setting a program verify voltage for verifying program data in the memory array based on the control circuit operating the program verify voltage setting method as provided in the first aspect.
In a fifth aspect, some embodiments of the present application further provide an electronic device including a memory chip as provided in the fourth aspect.
In summary, the embodiment of the application provides a programming verification voltage setting method, a programming method, a device, a chip and equipment, wherein the threshold voltage of an obtained target storage area after the erasing operation is executed can represent the electron capturing capability of the tunneling oxide layer and floating gate superposition of a storage unit, the threshold voltage and the initial threshold voltage are utilized to calculate and obtain the voltage difference value which can independently represent the electron capturing capability of the tunneling oxide layer, and then the programming verification voltage is adjusted and set according to the voltage difference value, so that whether the programming operation of the storage unit is qualified or not is accurately judged, and the weak 0 state of the storage unit after the programming is prevented after the storage unit is placed for a period of time.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (8)
1. The programming verification voltage setting method is applied to the programming operation of the nor flash and is characterized by comprising the following steps of:
acquiring a threshold voltage of a target storage area after an erasing operation is executed, wherein the threshold voltage is an intermediate threshold voltage of the target storage area after the erasing operation is executed;
acquiring a voltage difference value according to the initial threshold voltage of the target storage area and the threshold voltage;
setting a programming verification voltage according to the voltage difference value and the initial programming verification voltage;
wherein, the step of setting the program verify voltage according to the voltage difference value and the initial program verify voltage includes:
and setting a programming verification voltage according to the product of the voltage difference and a correction coefficient and the initial programming verification voltage, wherein the correction coefficient is set according to the electron concentration relation between the programming operation and the erasing operation of the nor flash.
2. The program verify voltage setting method of claim 1, wherein the program verify voltage setting method triggers execution to update the program verify voltage when a cycle number of a target memory area reaches a preset cycle number threshold.
3. The program verify voltage setting method of claim 2, wherein the cycle number threshold is one or more of 30000, 50000, 70000, and 90000.
4. The program verify voltage setting method of claim 1, wherein the target storage area comprises a number of storage arrays or a number of blocks or a number of sectors.
5. A method of programming, the method comprising the steps of:
performing programming operation on target memory cells in the target memory area;
the program verify voltage set by the program verify voltage setting method of any one of claims 1 to 4 verifies the program data of the target memory cell.
6. The utility model provides a programming check voltage setting device, is applied in the programming operation of nor flash, its characterized in that, programming check voltage setting device includes:
the acquisition module is used for acquiring the threshold voltage of the target storage area after the erasing operation is executed, wherein the threshold voltage is the middle threshold voltage of the target storage area after the erasing operation is executed;
the calculation module is used for obtaining a voltage difference value according to the initial threshold voltage of the target storage area and the threshold voltage;
the setting module is used for setting the programming verification voltage according to the voltage difference value and the initial programming verification voltage;
wherein, the step of setting the program verify voltage according to the voltage difference value and the initial program verify voltage includes:
and setting a programming verification voltage according to the product of the voltage difference and a correction coefficient and the initial programming verification voltage, wherein the correction coefficient is set according to the electron concentration relation between the programming operation and the erasing operation of the nor flash.
7. A memory chip comprising a control circuit and a memory array, the memory chip setting a program verify voltage for verifying program data in the memory array based on the control circuit operating the program verify voltage setting method according to any one of claims 1 to 4.
8. An electronic device comprising the memory chip of claim 7.
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| US8036044B2 (en) * | 2009-07-16 | 2011-10-11 | Sandisk Technologies Inc. | Dynamically adjustable erase and program levels for non-volatile memory |
| KR20140088386A (en) * | 2013-01-02 | 2014-07-10 | 에스케이하이닉스 주식회사 | Semiconductor apparatus and method of operating the same |
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| US6222768B1 (en) * | 2000-01-28 | 2001-04-24 | Advanced Micro Devices, Inc. | Auto adjusting window placement scheme for an NROM virtual ground array |
| CN101388248A (en) * | 2007-09-10 | 2009-03-18 | 海力士半导体有限公司 | Flash memory device and method of operating the same |
| US11373715B1 (en) * | 2021-01-14 | 2022-06-28 | Elite Semiconductor Microelectronics Technology Inc. | Post over-erase correction method with auto-adjusting verification and leakage degree detection |
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