CN117476800B - Silicon-based photoelectric detector and preparation method thereof - Google Patents

Abstract

The present invention relates to the field of semiconductor manufacturing, and provides a silicon-based photodetector and a preparation method, including a substrate, a first silicon oxide layer, an epitaxial layer, a second silicon oxide layer, a metal electrode layer and a metal layer; the first silicon oxide layer is deposited on the upper surface of the substrate, and a window is opened to expose the substrate to form an epitaxial window area; the epitaxial layer grows in the window area and is surrounded by the first silicon oxide layer, and the epitaxial layer can be one or a stack of silicon, germanium or silicon-germanium alloy, or impurities such as carbon, tin, and lead are doped as needed; the second silicon oxide layer is deposited on the epitaxial layer; the metal electrode layer is exposed on the surface of the second silicon oxide layer and connected to the epitaxial layer and the substrate; the metal layer is deposited on the lower surface of the substrate. The present invention can effectively reflect the incident light that is not completely absorbed by the absorption layer for recycling, and can increase the responsiveness and sensitivity of the detector; the potential of the suspended area of the silicon layer is controlled by connecting the metal layer to a fixed potential, thereby reducing interference with the behavior of the detector.

Description

Silicon-based photodetector and preparation method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and in particular to a silicon-based photoelectric detector and a preparation method thereof.

Background technique

Silicon photonic chip technology is a technology that integrates optoelectronic devices on a silicon substrate using CMOS technology. It combines the ultra-large-scale and ultra-high-precision manufacturing characteristics of integrated circuit technology with the advantages of ultra-high speed and ultra-low power consumption of photonic technology. Silicon photonic technology has broad application prospects in optical communications, data centers, optical interconnection, lidar, medical health, optical computing and other fields. After 20 years of extensive attention and in-depth research and development by academia and industry, it has been widely used in telecommunications and data centers. The band gap of silicon of 1.12eV determines that the cutoff wavelength of the response of silicon photodetectors is about 1.1 microns. By epitaxially growing germanium materials with narrower band gaps on silicon substrates as absorption materials to make silicon-based germanium photodetectors, the cutoff wavelength can be increased to about 1.6 microns, covering the most important infrared optical communication wavelengths of 1310nm and 1550nm. This technological breakthrough is one of the most critical links in the development of silicon photonic chips. Therefore, silicon-based photodetectors can flexibly choose to use silicon, germanium or silicon-germanium alloys as absorption layer materials to absorb and detect light of different wavelengths.

Silicon-based photodetectors can be divided into two categories: one is a waveguide-type detector in which light propagates and is absorbed in the horizontal direction, which is generally used in high-speed integrated optical circuits (PIC); the other is a detector in which light is incident and absorbed in the vertical direction. Among them, vertically structured silicon-based detectors have a wide range of uses because of their simple structure, convenient light coupling, and can be used flexibly as discrete devices or in array devices and optoelectronic integration (such as detector and transimpedance amplifier integration). Vertically structured detectors are usually made on silicon on insulator (SOI) substrates. The buried oxide layer produces two silicon/silicon oxide interfaces. Part of the light that is not completely absorbed by the detector will be reflected back to the detector by the interface to enhance absorption. The buried oxide layer can also reduce the parasitic effects of the substrate at high frequencies and increase the 3dB electrical bandwidth. However, as shown in FIG1 , this type of vertical structure detector often has two types of problems: on the one hand, when the P-type top silicon layer (Top Silicon Layer) of the conventional SOI substrate is used for N-type in-situ doping epitaxy or low-energy ion implantation of N-type impurities, part of the P-type top silicon layer may be retained under the N-type doped layer at the bottom of the detector. This part of the P-type top silicon layer becomes a suspended structure, which is easy to induce charge and generate an uncertain potential, so that the parasitic PN junction formed by the 13A P-type silicon layer and the 13B N ⁺ silicon layer is in a forward or reverse bias state, resulting in the injection or extraction of carriers, which may interfere with the behavior of the detector, such as changing the detector series resistance or substrate parasitic capacitance. On the other hand, no matter how the structure of the vertical detector is designed and coordinated with the buried oxide layer, it is impossible to avoid that a part of the incident light A is not completely absorbed by the absorption layer. This part of the light passes through the buried oxide layer of the SOI and leaks to the back surface of the silicon substrate. Finally, about 70% of it escapes from the SOI structure, which becomes a light loss problem that this type of vertical structure detector must face. This part of the escaped light has nothing to do with the doping type of the detector. Even in the waveguide detector that transmits and absorbs light in the horizontal direction, there is light that leaks into the silicon substrate and escapes through the back surface. If most of the escaped light can be reflected back to the absorption layer and absorbed and utilized again, the detector's responsiveness and sensitivity can be improved.

Summary of the invention

In view of the interference of the top silicon layer suspension area on the detector behavior and the light escape loss on the back side of the substrate in the prior art, a silicon-based photodetector and a preparation method thereof are provided. After all the steps including metallization and passivation layers are completed in the production of the silicon-based detector, a metal layer is deposited on the back surface of the silicon substrate. On the one hand, this back metal layer can act as an effective broadband reflector to reflect most of the infrared light back to be absorbed and utilized by the absorption layer again. On the other hand, the back metal layer is connected to a fixed potential, and the metal-oxide-semiconductor (MOS) structure constructed by silicon substrate-buried oxide layer-P-type top silicon layer suspension area can control the potential of the P-type top silicon layer suspension area, thereby reducing the interference with the detector behavior.

The first aspect of the present invention proposes a silicon-based photodetector, comprising a substrate, a first silicon oxide layer, an epitaxial layer, a second silicon oxide layer, a metal electrode layer and a metal layer; the first silicon oxide layer is deposited on the upper surface of the substrate, and a window is etched to expose the substrate for growing the epitaxial layer; the epitaxial layer grows in the window area of the first silicon oxide layer and is surrounded by the first silicon oxide layer; the second silicon oxide layer is deposited on the epitaxial layer; the metal electrode layer is exposed on the surface of the second silicon oxide layer and is connected to the epitaxial layer and the substrate; the metal layer is deposited on the lower surface of the substrate.

Furthermore, the metal layer is connected to zero potential or other fixed potential.

Furthermore, the substrate is a SOI (Silicon On Insulator) substrate or a bulk silicon substrate.

Furthermore, the metal layer is made of a material having both good infrared light reflection performance and excellent ohmic contact performance with silicon.

Furthermore, the metal layer material is aluminum or aluminum alloy.

Furthermore, the thickness of the metal layer is 100-500 nanometers.

Furthermore, the epitaxial layer is one of silicon, germanium or silicon-germanium alloy or a stack of these materials, or is formed by doping impurities such as carbon, tin, lead, etc. as needed.

The second aspect of the present invention provides a method for preparing a silicon-based photodetector, which is used to prepare the silicon-based photodetector provided in the first aspect of the present invention, comprising:

Step S1, selecting an SOI substrate;

Step S2, using photolithography and dry etching to etch ridge waveguides and strip waveguides on the top silicon layer of the SOI substrate, and to achieve mesa isolation between detector areas;

Step S3, preparing a selective epitaxial detector until the metallization process and the passivation layer opening are completed;

Step S4, sputtering a 150-nanometer aluminum metal layer on the back of the silicon substrate, and annealing it at 350° C. for half an hour in a nitrogen-hydrogen mixed atmosphere to form a silicon-based photodetector.

Furthermore, the metal layer is connected to a zero potential or a non-zero fixed potential.

Furthermore, in step S1, a bulk silicon substrate is used instead of an SOI substrate.

Compared with the prior art, the beneficial effects of adopting the above technical solution are:

1) Adding a metal reflector on the back of the substrate can effectively reflect the incident light that is not completely absorbed by the absorption layer and recycle it, which can increase the responsiveness and sensitivity of the detector;

2) By grounding the metal layer on the back of the substrate or connecting it to a fixed potential, the MOS structure consisting of silicon substrate-buried oxide layer-top silicon layer is used to control the potential of the floating area of the top silicon layer, thereby reducing the interference with the detector behavior;

3) It is suitable for both vertically incident pancake detectors and horizontally light-coupled waveguide detectors, and can also be used for vertical or horizontal avalanche photodiodes; it is not only suitable for detectors on SOI substrates, but also for detectors on bulk silicon substrates, with flexibility and economy;

4) The back-side deposition of metal materials and alloy processes is compatible with CMOS processes, with a simple structure and low cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a vertical structure detector on an SOI substrate in the prior art.

FIG. 2 is a cross-sectional structure of a silicon-based detector proposed in the present invention.

FIG3 (a) is a schematic diagram showing the simulation results of the light reflectivity of the metal reflective layer on the back of the SOI substrate as a function of substrate thickness when the wavelength is 1550 nanometers. FIG3 (b) is a schematic diagram showing the simulation results of the light reflectivity of the metal reflective layer on the back of the SOI substrate as a function of substrate thickness when the wavelength is 1310 nanometers.

FIG4(a) is a schematic diagram showing the simulation results of the light reflectivity of the metal reflective layer on the back of the bulk silicon substrate varying with the substrate thickness when the wavelength is 1550 nanometers, and FIG4(b) is a schematic diagram showing the simulation results of the light reflectivity of the metal reflective layer on the back of the bulk silicon substrate varying with the substrate thickness when the wavelength is 1310 nanometers.

Figure symbols: 1-SOI substrate, 2-first silicon oxide layer, 3-epitaxial layer, 4-second silicon oxide layer, 5-metal electrode layer, 6-metal layer, 7-MOS structure, 11-silicon substrate, 12-buried oxide layer, 13-top silicon layer, 3A-epitaxial I layer, 3B-epitaxial P ⁺ layer, 3C-epitaxial P ⁺⁺ layer, 5A-positive electrode, 5B-negative electrode, 13A-P-type silicon layer, 13B-N ⁺ silicon layer, 13C-N ⁺⁺ silicon layer.

Detailed ways

Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar modules or modules with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be construed as limitations on the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

Example 1

In order to solve the problem of interference of the floating area of the P-type silicon layer 13A of the top silicon layer on the detector behavior and light escape loss on the back side of the substrate, this embodiment proposes a silicon-based photodetector. After all the steps including metallization and passivation layers are completed in the production of the silicon-based detector, a metal layer 6 is deposited on the back surface of the silicon substrate 11. The metal layer 6 simultaneously plays the role of a light reflection layer and a back electrode. The metal layer 6 is an effective broadband reflector that reflects most of the infrared light back and is absorbed and utilized by the absorption layer again. In one embodiment, the potential of the P-type silicon layer 13A is controlled by connecting it to zero potential or other fixed potential to reduce interference with the detector behavior.

Please refer to FIG2 , the silicon-based photodetector includes a substrate, a first silicon oxide layer 2, an epitaxial layer 3, a second silicon oxide layer 4, a metal electrode layer 5 and a metal layer 6. In this embodiment, the substrate is a starting SOI (Silicon-on-insulator, SOI) substrate 1 material, which includes a silicon substrate 11, a buried oxide layer 12, and a top silicon layer 13 from bottom to top. The top silicon layer 13 includes, from bottom to top, a P-type silicon layer 13A originally doped with the top silicon layer of the SOI substrate, an N ⁺ silicon layer 13B and an N ⁺⁺ silicon layer 13C doped with N-type and gradually increasing concentrations. In one embodiment, the substrate resistivity is 0.01-10k ohm·cm, and materials with higher resistivity are preferably used to reduce the parasitic effects of the substrate, which is more beneficial to the performance of the silicon photonic chip; the buried oxide layer 12 has a thickness of 0.1-3 microns, and SOI materials with thicker buried oxide layer 12 are preferably used to improve the RF bandwidth of the detector; the top silicon layer 13 has a thickness of 0.1-3 microns, and a certain thickness is required to grow a high-quality epitaxial layer and facilitate optical waveguide design and etching processing.

A first silicon oxide layer 2 is deposited on the SOI substrate 1 material, which is mainly used to define a selective epitaxial window and has a thickness of 0.5-2 microns. A window is opened on the first silicon oxide layer to expose the top silicon layer 13 of the SOI substrate, forming a window area for growing an epitaxial layer. The epitaxial layer 3 is epitaxially grown in the window area and surrounded by the first silicon oxide layer 2. The epitaxial layer 3 can be one of silicon, germanium or silicon-germanium alloy or a stack of these materials, and can also be doped with impurities such as carbon, tin, and lead as needed. From bottom to top, it includes an intrinsic epitaxial I layer 3A and a P-type doped epitaxial P ⁺ layer 3B and an epitaxial P ⁺⁺ layer 3C with gradually increasing concentration. In one embodiment, the thickness of the epitaxial layer 3 is 0.5-2 microns, which is the same as the first silicon oxide layer 2, so as to keep the absorption layer flush with the upper part of the first silicon oxide layer 2.

The second silicon oxide layer 4 is deposited on the epitaxial layer 3 and serves as a pre-metallization dielectric. In one embodiment, the pre-metallization dielectric has a conventional thickness in the range of 0.4-1 micron.

The metal electrode layer 5 is exposed on the surface of the second silicon oxide layer 4. The metal electrode layer 5 includes a positive electrode 5A and a negative electrode 5B. The positive electrode 5A is connected to the epitaxial layer 3, and the negative electrode 5B is connected to the N ⁺⁺ silicon layer 13C in the SOI layer substrate. In one embodiment, the metal electrode layer has a conventional thickness of 0.5-1 micron and is composed of pure aluminum or an aluminum alloy containing a small amount of silicon and/or copper.

The metal layer 6 is deposited on the lower surface of the SOI substrate 1. It should be noted that a metal with good reflectivity to light, which can reflect most of the infrared light back to the silicon substrate 11 and easily form an excellent ohmic contact with silicon should be selected, preferably aluminum or an alloy material with aluminum as the main component; the thickness of the metal layer 6 is 100-500 nanometers, the lower limit is determined by the thickness sufficient to maintain the effective reflection ability of light and the minimum thickness when used as electrode wire bonding, and the upper limit is subject to the destructive effect of stress when the thickness is too large. If it is too thin, it is easy to be penetrated by light and insufficient for effective reflection, and it is not conducive to wire bonding external electrodes. If it is too thick, it will significantly increase the stress and cause wafer warping or even peeling.

In the silicon-based detector shown in FIG2 , the silicon substrate 11-buried oxide layer 12-top silicon layer 13 constitutes a MOS structure 7, and this part of the top silicon layer will form a suspended P-type silicon layer 13A, which is easy to induce charge and generate an uncertain potential, so that the parasitic PN junction formed by the suspended P-type silicon layer 13A and the N ⁺ silicon layer 13B is in a forward biased or reverse biased state, resulting in the injection or extraction of carriers, which may interfere with the behavior of the detector. Based on this, after the metal layer 6 is set on the back of the silicon substrate 11, after the silicon substrate 11 is connected to a zero potential or a non-zero fixed potential through the metal layer 6, the potential of the suspended P-type silicon layer 13 is also clamped and has certainty, so that the bias state of the parasitic PN junction formed by the suspended P-type silicon layer 13A and the N ⁺ silicon layer 13B is more certain, which can reduce the interference with the behavior of the detector.

Please refer to Figure 1. When there is no metal reflective layer on the back of the silicon substrate 11, most of the infrared light reaching the back surface of the silicon substrate 11, about 70%, escapes, and a small part of the light is reflected back to the silicon substrate 11 (A ₁ in Figure 1), accounting for about 30% of the incident light A; after adding a metal reflective layer on the back of the silicon substrate 11, the light reflected back to the silicon substrate 11 is greatly increased to 70-80% (A ₁ ^′ in Figure 2), that is, most of the light can be absorbed and utilized again by the absorption layer. The specific reflectivity here is related to the infrared wavelength and the structure of each material layer.

At the same time, a metal material with good ohmic contact characteristics with the silicon substrate 11 is selected, and the back metal reflective layer also plays the role of the back electrode, which is connected to zero potential or other fixed potential, and can effectively control the potential of the floating area of the P-type top silicon layer 13 through the MOS effect, thereby reducing the interference of this floating area with the detector behavior caused by the random induced charge changing the PN junction bias in the top silicon layer 13. Therefore, the two problems of infrared light escaping from the back of the substrate and the floating area of the top silicon layer 13 interfering with the detector behavior in the existing silicon-based detectors are well solved by adding a metal layer 6 on the back of the silicon substrate 11 and connecting it to a fixed potential.

As shown in Figures 3 (a) and 3 (b), the simulation results show that the light reflectivity of the metal reflective layer on the back of the SOI substrate 1 varies with the thickness of the substrate. Regardless of whether the most commonly used infrared communication wavelength is 1550 nanometers or 1310 nanometers, the reflectivity of the metal layer 6 on the back of the SOI substrate 1 to vertically incident light waves fluctuates periodically with the thickness of the substrate. The highest reflectivity is about 95% and the lowest is about 65%. For most substrate thicknesses, the reflectivity is above 80%. Therefore, after adding a metal reflective layer on the back of the substrate, the recycling effect of the escaped light on the back of the substrate will be very significant.

In another embodiment, the SOI substrate 1 can be replaced by a bulk silicon substrate. Although there is no MOS effect to control when there is no buried oxide layer 12, the fixed potential connected to the back metal layer 6 directly determines the substrate potential, and the uncertainty of the substrate potential is also avoided. At this time, please refer to Figures 4 (a) and 4 (b), which show the simulation results of the light reflectivity of the metal reflection layer on the back of the bulk silicon substrate at infrared communication wavelengths of 1550 nanometers and 1310 nanometers as the substrate thickness changes. It can be seen that the metal layer 6 on the back of the substrate also has good light reflectivity.

It should be noted that in this embodiment, the solution proposed by the present invention is described by taking a vertical silicon-based PIN detector as an example. However, it is not difficult to understand from the device structure and working principle that the present invention is applicable to both PN detectors and avalanche photodiodes (APDs), as well as horizontal waveguide PN, PIN detectors and APDs; it is not only suitable for detectors on SOI substrates, but also for detectors on bulk silicon substrates. That is, the method of adding a metal layer 6 on the back of the substrate to reduce interference with the detector behavior and light escape loss on the back of the substrate can be used in all the above-mentioned scenarios.

Example 2

This embodiment proposes a method for preparing a silicon-based photoelectric detector, which is used to prepare the silicon-based photoelectric detector proposed in Embodiment 1, comprising:

Step S1, select an SOI substrate. In one embodiment, select an 8-inch P(100) SOI substrate with a substrate thickness of 725 microns, a resistivity of -10 ohm·cm, a buried oxide layer thickness of 2 microns, and a top silicon layer thickness of 0.22 microns.

Step S2, using photolithography and dry etching to etch ridge waveguides and strip waveguides on the top silicon layer of the SOI substrate, and to achieve mesa isolation between detector areas;

Step S3, preparing a selective epitaxial detector until the metallization process and the passivation layer opening are completed;

Step S4, sputtering a 150-nanometer aluminum metal layer on the back of the silicon substrate, and annealing it at 350° C. for half an hour in a nitrogen-hydrogen mixed atmosphere to form a silicon-based photodetector.

When an SOI substrate is used, the metal layer is connected to the zero-point potential to reduce the interference of the PN junction under the detector absorption layer on the detector behavior.

In another embodiment, in step S1, a bulk silicon substrate may be used instead of an SOI substrate. In this case, the metal layer is connected to a fixed potential to reduce the interference of PN on the detector behavior.

When the silicon-based photodetector prepared with an SOI substrate is in the working state, 1310 nanometer infrared light is irradiated from the front of the detector, the positive electrode 4A is connected to 0 potential, and the negative electrode 4B is connected to the positive bias potential, so that the detector is in a negatively biased working state, and the back metal layer 6 is connected to 0 potential. In this case, the light that is not completely absorbed by the absorption layer is reflected back by the back metal layer and absorbed and utilized again, so that a higher detector responsiveness and sensitivity can be obtained. At the same time, because the back of the silicon substrate is grounded, the MOS effect clamps the suspended P-type silicon layer 13A potential and the PN junction bias state, reducing interference with the detector behavior.

It should be noted that in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "setting" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances; the drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings herein can be arranged and designed in various different configurations.

Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims (7)

1. The silicon-based photoelectric detector is characterized by comprising a substrate, a first silicon oxide layer, an epitaxial layer, a second silicon oxide layer, a metal electrode layer and a metal layer; the first silicon oxide layer is deposited on the upper surface of the substrate, and windows are formed on the substrate to expose the substrate to form an epitaxial window area; the epitaxial layer grows in the window area and is surrounded by the first silicon oxide layer; the second silicon dioxide layer is deposited on the epitaxial layer; the metal electrode layer is exposed on the surface of the second silicon dioxide layer and is connected with the epitaxial layer and the substrate; the metal layer is deposited on the lower surface of the substrate; the substrate is a silicon-on-insulator substrate, a silicon substrate-oxygen-buried layer-top silicon layer of the silicon-on-insulator substrate forms a MOS structure, and the top silicon layer forms a suspended P-type silicon layer; the metal layer is connected to zero potential or other non-zero fixed potential, so that the silicon substrate is also connected to zero potential or non-zero fixed potential, and the fixed potential externally connected with the silicon substrate is controlled through the MOS structure, so that the potential of the suspended P-type silicon layer is deterministic.

2. The silicon-based photodetector of claim 1, wherein said metal layer is made of a material having both infrared light reflection properties and ohmic contact properties with silicon.

3. The silicon-based photodetector of claim 1, wherein the metal layer material is aluminum or an aluminum alloy.

4. The silicon-based photodetector of claim 1, wherein the metal layer has a thickness of 100-500 nm.

5. The silicon-based photodetector of claim 1, wherein said epitaxial layer is one of silicon, germanium or a silicon-germanium alloy, or a stack of two or three of silicon, germanium or a silicon-germanium alloy.

6. The silicon-based photodetector device of claim 5, wherein said epitaxial layer is doped with any one of carbon, tin or lead as desired.

7. A method for manufacturing a silicon-based photodetector, for manufacturing a silicon-based photodetector according to any one of claims 1 to 6, comprising:

s1, selecting a silicon-on-insulator substrate;

step S2, etching a ridge waveguide and a strip waveguide on a top silicon layer of a silicon substrate on an insulator by adopting the combination of photoetching and dry etching, and realizing mesa isolation between detector areas;

s3, preparing a selective epitaxial detector until the metallization process and the opening of the passivation layer are completed;

s4, sputtering a 150-nanometer aluminum metal layer on the back surface of the silicon substrate, and annealing for half an hour at 350 ℃ in a nitrogen-hydrogen mixed atmosphere to form a silicon-based photoelectric detector;

the metal layer is connected with zero potential or non-zero fixed potential.