CN117476654B - Display panel and preparation method thereof - Google Patents
Display panel and preparation method thereofInfo
- Publication number
- CN117476654B CN117476654B CN202211738578.8A CN202211738578A CN117476654B CN 117476654 B CN117476654 B CN 117476654B CN 202211738578 A CN202211738578 A CN 202211738578A CN 117476654 B CN117476654 B CN 117476654B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
- H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
- H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- Thin Film Transistor (AREA)
Abstract
The invention relates to a display panel and a preparation method thereof. The invention prepares the first polycrystalline oxide active part on the first channel part of the first amorphous oxide active part, realizes the effect of a high mobility carrier channel by utilizing the laminated structure formed by the first channel part and the first polycrystalline oxide active part, and realizes the effect of low off-current by utilizing the single-layer structure of the first contact part and the second contact part. The invention prepares the second polycrystalline oxide active part and the third polycrystalline oxide active part on the third contact part and the fourth contact part of the second amorphous oxide active part respectively, realizes the effects of high stability and low off current by utilizing the single-layer structure of the second channel part, optimizes the ohmic contact characteristic with the second source electrode by utilizing the laminated structure of the third contact part and the second polycrystalline oxide active part, and optimizes the ohmic contact characteristic with the second drain electrode by utilizing the laminated structure of the fourth contact part and the third polycrystalline oxide active part.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a preparation method thereof.
Background
The low temperature poly-Oxide thin film transistor (Low Temperature Poly-Oxide TFT, LTPOTFT) technology is an emerging thin film transistor technology in recent years. LTPO the backplate technology combines the low off-current of an oxide active part thin film transistor (igzo TFT) with the high carrier mobility characteristics of a low temperature polysilicon thin film transistor (english: low Temperature Poly-Silicon TFT, LTPS TFT for short), and can realize functions such as variable refresh rate and off-screen display (Always-on).
However, the uniformity of large-size LTPS prepared by using an Excimer LASER ANNEALING (ELA) process is problematic, the display quality is degraded due to the variation of the characteristics of the thin film transistor caused by the non-uniformity of the LTPS, the LTPO back plate technology needs to prepare the driving TFT of the LTPS and the switching TFT of Oxide on different film layers respectively, the process is complicated and high in cost, the large-size production is not favored, the hydrogenation of the polysilicon layer can improve the device characteristics of the low-temperature polysilicon thin film transistor by adopting the thin film transistor of the polysilicon active part material, and the thin film transistor of the Oxide active part material can cause the characteristic degradation of the Oxide active part thin film transistor when hydrogen or water vapor enters the Oxide active layer from the film layer adjacent to the Oxide active layer, so that the LTPO technology must overcome the conflict characteristics caused by the influence of the hydrogen and the like.
Disclosure of Invention
The invention aims to provide a display panel and a preparation method thereof, which can solve the problems of display quality reduction, complex process, high cost, unfavorable mass production of large size, and deterioration of the characteristics of an oxide active part thin film transistor caused by hydrogen or water vapor entering an oxide active layer due to non-uniformity of LTPS in the prior LTPO technology.
In order to solve the problems, the invention provides a display panel which comprises a substrate, a first active layer, a second active layer and a polycrystalline oxide, wherein the first active layer is arranged on the substrate and is made of amorphous oxide and comprises a first amorphous oxide active part and a second amorphous oxide active part which are mutually spaced, the second active layer is arranged on one side of the first active layer, which is far away from the substrate, and is made of polycrystalline oxide and comprises a first polycrystalline oxide active part, a second polycrystalline oxide active part and a third polycrystalline oxide active part which are mutually spaced, the first amorphous oxide active part comprises a first channel part, a first contact part and a second contact part, the first polycrystalline oxide active part and the second polycrystalline oxide active part are respectively arranged at two ends of the first channel part, the first polycrystalline oxide active part is correspondingly arranged with the first channel part, the second amorphous oxide active part comprises a second channel part, a third contact part and a fourth contact part which are respectively arranged at two ends of the second channel part, the second amorphous oxide active part comprises a first polycrystalline oxide active part, a second polycrystalline oxide active part and a third polycrystalline oxide active part, and a fourth polycrystalline oxide active part, and a first polycrystalline oxide active part are respectively arranged at two ends of the first polycrystalline oxide active part.
Further, the display panel further comprises a light shielding layer arranged between the substrate and the first active layer and corresponding to the first amorphous oxide active part, a buffer layer arranged between the light shielding layer and the first active layer, and a blocking layer arranged between the buffer layer and the first active layer.
The display panel further comprises a gate insulating layer, an interlayer insulating layer, a second metal layer, a first metal layer, a second metal layer, a passivation layer, a first metal layer, a second metal layer, a passivation layer and a passivation layer, wherein the gate insulating layer is arranged on one side of the second active layer away from the substrate, the first gate insulating layer and the second gate insulating layer are respectively arranged corresponding to the first channel part and the second channel part, the first metal layer is arranged on one side of the first metal layer away from the substrate and extends to cover the barrier layer, the second metal layer is arranged on one side of the interlayer insulating layer away from the substrate, the interlayer insulating layer comprises a first drain electrode, a first source electrode, a second drain electrode and a second source electrode which are mutually spaced, the first drain electrode, the first source electrode, the second drain electrode and the second source electrode are respectively and electrically connected to the first contact part, the second contact part, the third contact part and the fourth contact part, the passivation layer is arranged on one side of the first metal layer away from the substrate, the second metal layer is arranged on one side of the passivation layer away from the passivation layer, and the passivation layer is arranged on one side of the passivation layer away from the first metal layer.
Further, the projection of the first amorphous oxide active part on the substrate falls into the projection of the light shielding layer on the substrate.
Further, the blocking layer is made of one or more of aluminum oxide, hafnium oxide, zirconium oxide and yttrium oxide, and the thickness of the blocking layer ranges from 100 angstroms to 500 angstroms.
In order to solve the problems, the invention provides a preparation method of a display panel, which comprises the steps of providing a substrate, preparing amorphous oxide on the substrate to form a first active part material layer, preparing polycrystalline oxide on one side of the first active part material layer far away from the substrate to form a second active part material layer, etching the second active part material layer and the first active part material layer by using a half-tone photomask, etching the second active part material layer to form first polycrystalline oxide active parts, second polycrystalline oxide active parts and third polycrystalline oxide active parts which are mutually spaced, etching the first active part material layer to form first amorphous oxide active parts and second amorphous oxide active parts which are mutually spaced, wherein the first amorphous oxide active parts comprise a first channel part and first contact parts and second contact parts which are respectively positioned at two ends of the first channel part, etching the second active part material layer and the first active part material layer by using a half-tone photomask, etching the second active part material layer to form first polycrystalline oxide active parts, the second polycrystalline oxide active parts and the second polycrystalline oxide active parts which are mutually spaced, and the third polycrystalline oxide active parts are respectively positioned at two ends of the first amorphous oxide active parts and the second amorphous oxide active parts, and the first amorphous oxide active parts are respectively positioned at two ends of the first amorphous oxide active parts and the second amorphous oxide active parts.
The step of etching the second active portion material layer and the first active portion material layer by using the halftone mask includes dividing the first active portion material layer into the first channel portion, the second channel portion, the first contact portion, the second contact portion, the third contact portion and the fourth contact portion, wherein the halftone mask includes a light shielding region, a semi-transparent region and a full-transparent region, the light shielding region is arranged corresponding to the first channel portion, the third contact portion and the fourth contact portion, and the semi-transparent region is arranged corresponding to the first contact portion, the second contact portion and the second channel portion.
Further, the step of etching the second active portion material layer and the first active portion material layer by using the halftone mask further comprises disposing a photoresist layer on a side of the second active portion material layer, which is far away from the substrate, at positions corresponding to the first channel portion, the second channel portion, the first contact portion, the second contact portion, the third contact portion and the fourth contact portion, and thinning the photoresist layer corresponding to the first contact portion, the second contact portion and the second channel portion by an exposure and development process.
Further, the thicknesses of the photoresist layers corresponding to the first contact portion, the second contact portion, and the second channel portion are the same, and the thicknesses of the photoresist layers corresponding to the first channel portion, the third contact portion, and the fourth contact portion are the same.
Further, the step of etching the second active part material layer and the first active part material layer by using the halftone mask further comprises the steps of etching the first active part material layer and the second active part material layer through a dry etching process, and stripping and removing the photoresist layer.
The invention has the advantages that the invention utilizes the characteristics of high mobility of polycrystalline oxide, on-current and lower off-current similar to LTPS and better large-size uniformity, and solves the problem of poor large-size uniformity of LTPO backboard technology. A first polycrystalline oxide active part is prepared on a first channel part of the first amorphous oxide active part, the effect of a high-mobility carrier channel is achieved by using a laminated structure formed by the first channel part and the first polycrystalline oxide active part, and the effect of low off-current is achieved by using a single-layer structure of a first contact part and a second contact part.
The invention prepares the second polycrystalline oxide active part and the third polycrystalline oxide active part on the third contact part and the fourth contact part of the second amorphous oxide active part respectively, realizes the effects of high stability and low off current by utilizing the single-layer structure of the second channel part, optimizes the ohmic contact characteristic with the second source electrode by utilizing the laminated structure of the third contact part and the second polycrystalline oxide active part, and optimizes the ohmic contact characteristic with the second drain electrode by utilizing the laminated structure of the fourth contact part and the third polycrystalline oxide active part.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a display panel according to the present invention;
FIG. 2 is a schematic diagram of a structure of a light shielding layer formed on a substrate according to the present invention;
FIG. 3 is a schematic illustration of a mechanism for preparing the buffer layer, the barrier layer, the first active layer, and the second active layer on the basis of FIG. 2;
FIG. 4 is a schematic diagram of an etching configuration using a halftone mask;
FIG. 5 is a schematic diagram of a structure after etching using a halftone mask;
fig. 6 is a schematic structural view of preparing a gate insulating layer and a first metal layer on a second active layer;
Fig. 7 is a schematic structural view of an interlayer insulating layer prepared on a first metal layer;
fig. 8 is a schematic structural view of a second metal layer prepared on an interlayer insulating layer;
Fig. 9 is a schematic structural view of a passivation layer and a planarization layer prepared on a second metal layer.
Reference numerals illustrate:
100. A display panel;
1.2, a shading layer;
3. a buffer layer, a barrier layer;
5. a first active layer, a second active layer;
7. A gate insulating layer; 8, a first metal layer;
9. 10, a second metal layer;
11. A passivation layer 12, a planarization layer;
13. A pixel electrode 14, a first active portion material layer;
15. A second active material layer, a halftone mask;
17. a photoresist layer;
51. a first amorphous oxide active portion; 52, a second amorphous oxide active portion;
511. 512, first contact portions;
513. 521, second channel portion;
522. 523, fourth contact portion;
61. A first polycrystalline oxide active portion 62, a second polycrystalline oxide active portion;
63. A third polycrystalline oxide active portion;
71. A first gate insulating unit 72, a second gate insulating unit;
81. a first gate 82, a second gate;
101. 102, a first source;
103. 104, a second source electrode;
161. a light shielding region 162;
163. a full penetration zone.
Detailed Description
The following detailed description of the preferred embodiments of the invention, taken in conjunction with the accompanying drawings, is provided to fully convey the substance of the invention to those skilled in the art, and to illustrate the invention to practice it, so that the technical disclosure of the invention will be made more clear to those skilled in the art to understand how to practice the invention more easily. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as limited to the set forth herein.
The directional terms used herein, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are used for explaining and describing the present invention only in terms of the directions of the drawings and are not intended to limit the scope of the present invention.
In the drawings, like structural elements are referred to by like reference numerals and components having similar structure or function are referred to by like reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of understanding and description, and the present invention is not limited to the size and thickness of each component.
Example 1
As shown in fig. 1, the present embodiment provides a display panel 100. The display panel 100 includes a substrate 1, a light shielding layer 2, a buffer layer 3, a barrier layer 4, a first active layer 5, a second active layer 6, a gate insulating layer 7, a first metal layer 8, an interlayer insulating layer 9, a second metal layer 10, a passivation layer 11, a planarization layer 12, and a pixel electrode 13.
The material of the substrate 1 includes polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, and the like. In this embodiment, the substrate 1 is made of polyimide, so that the substrate 1 has better impact resistance and can effectively protect the display panel 100.
Wherein the light shielding layer 2 is disposed on the substrate 1. Wherein the light shielding layer 2 has a three-layer structure, the lower layer comprises one or more of Mo, ti and Ni, the middle layer is Cu or Cu alloy, and the upper layer comprises one or more of Mo, ti and Ni. Wherein the thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2000 angstroms to 10000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms.
The buffer layer 3 is disposed on a side of the light shielding layer 2 away from the substrate 1, and extends to cover the substrate 1. The buffer layer 3 mainly plays a role of buffering, and the material of the buffer layer comprises one or more of SiOx and SiNx. The thickness of the buffer layer 3 ranges from 2000 a to 10000 a.
Wherein a barrier layer 4 is arranged on the side of the buffer layer 3 remote from the substrate 1. The material of the barrier layer 4 includes one or more of aluminum oxide (AlOx), hafnium oxide (HfO 2), zirconium oxide (ZrO 2) and yttrium oxide (Y 2O3). In this embodiment, the material of the barrier layer 4 is alumina. The thickness of the barrier layer 4 ranges from 100 angstroms to 500 angstroms. Since the material of the first active layer is amorphous oxide and the material of the second active layer is polycrystalline oxide, the barrier layer 4 is mainly used to prevent hydrogen or water vapor from affecting the characteristics of the first active layer and the second active layer, and improve the reliability of the display panel 100.
Wherein the first active layer 5 is arranged on the side of the barrier layer 4 remote from the substrate 1. The material of the first active layer 5 is amorphous oxide. The thickness of the first active layer 5 ranges from 100 angstroms to 1000 angstroms. The first active layer 5 includes a first amorphous oxide active portion 51 and a second amorphous oxide active portion 52 spaced apart from each other.
The first amorphous oxide active portion 51 includes a first channel portion 511, and a first contact portion 512 and a second contact portion 513 respectively located at both ends of the first channel portion 511. The second amorphous oxide active portion 52 includes a second channel portion 521 and third and fourth contact portions 522 and 523 located at both ends of the second channel portion 521, respectively.
Wherein the light shielding layer 2 is provided corresponding to the first amorphous oxide active portion 51. In this embodiment, the projection of the first amorphous oxide active portion 51 onto the substrate 1 falls within the projection of the light shielding layer 2 onto the substrate 1.
Wherein the second active layer 6 is arranged on the side of the first active layer 5 remote from the substrate 1. The material of the second active layer 6 is polycrystalline oxide. The thickness of the second active layer 6 ranges from 100 angstroms to 500 angstroms. The second active layer 6 includes a first polycrystalline oxide active portion 61, a second polycrystalline oxide active portion 62, and a third polycrystalline oxide active portion 63 that are spaced apart from each other.
The first polycrystalline oxide active part 61 is provided corresponding to the first channel part 511. The second polycrystalline oxide active region 62 is provided corresponding to the third contact portion 522, and the third polycrystalline oxide active region 63 is provided corresponding to the fourth contact portion 523.
The embodiment utilizes the characteristics of high mobility of polycrystalline oxide, on-current and lower off-current similar to LTPS and better large-size uniformity, and solves the problem of poor large-size uniformity of LTPO backboard technology. The first polycrystalline oxide active part 61 is prepared on the first channel part 511 of the first amorphous oxide active part 51, an effect of a high mobility carrier channel is achieved by using a stacked structure formed by the first channel part 511 and the first polycrystalline oxide active part 61, and an effect of a low off-current is achieved by using a single layer structure of the first contact part 512 and the second contact part 513.
In this embodiment, the second polycrystalline oxide active part 62 and the third polycrystalline oxide active part 63 are respectively prepared on the third contact part 522 and the fourth contact part 523 of the second amorphous oxide active part 52, the effects of high stability and low off-current are achieved by using the single-layer structure of the second channel part 521, the ohmic contact characteristic with the second drain electrode 103 is optimized by using the stacked structure of the third contact part 522 and the second polycrystalline oxide active part 62, and the ohmic contact characteristic with the second source electrode 104 is optimized by using the stacked structure of the fourth contact part 523 and the third polycrystalline oxide active part 63.
Wherein a gate insulating layer 7 is provided on a side of the second active layer 6 remote from the substrate 1. The material of the gate insulating layer 7 includes one or more of aluminum oxide (AlOx), hafnium oxide (HfO 2), zirconium oxide (ZrO 2) and yttrium oxide (Y 2O3). In this embodiment, the material of the gate insulating layer 7 is alumina. The thickness of the gate insulating layer 7 ranges from 500 a to 1000 a. The gate insulating layer 7 includes a first gate insulating unit 71 and a second gate insulating unit 72 provided corresponding to the first channel portion 511 and the second channel portion 521, respectively. The first gate insulating unit 71 serves to prevent a short circuit phenomenon from occurring in contact between the first channel portion 511 and the first gate 81. The second gate insulating unit 72 is used to prevent the contact between the second channel portion 521 and the second gate 82 from being shorted.
Wherein the first metal layer 8 is disposed on a side of the gate insulating layer 7 away from the substrate 1. The first metal layer 8 has a three-layer structure, the lower layer includes one or more of Mo, ti, ni, the middle layer is Cu or Cu alloy, and the upper layer includes one or more of Mo, ti, ni. Wherein the thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2000 angstroms to 10000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms. The first metal layer 8 includes a first gate 81 and a second gate 82 provided corresponding to the first channel portion 511 and the second channel portion 521, respectively.
The interlayer insulating layer 9 is disposed on a side of the first metal layer 8 away from the substrate 1, and extends to cover the barrier layer 4. The thickness of the interlayer insulating layer 9 ranges from 2000 a to 10000 a. The material of the interlayer insulating layer 9 includes one or more of SiOx and SiNx. In this embodiment, the interlayer insulating layer 9 is made of SiOx.
Wherein the second metal layer 10 is disposed on a side of the interlayer insulating layer 9 away from the substrate 1. The second metal layer 10 has a three-layer structure, the lower layer includes one or more of Mo, ti, ni, the middle layer is Cu or Cu alloy, and the upper layer includes one or more of Mo, ti, ni. Wherein the thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2000 angstroms to 10000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms. The second metal layer 10 includes a first drain electrode 101, a first source electrode 102, a second drain electrode 103, and a second source electrode 104 spaced apart from each other. The first drain 101, the first source 102, the second drain 103, and the second source 104 are electrically connected to the first contact 512, the second contact 513, the third contact 522, and the fourth contact 523, respectively.
Wherein a passivation layer 11 is arranged on the side of the second metal layer 10 remote from the substrate 1. The passivation layer 11 is made of one or more of SiOx and SiNx. In this embodiment, the passivation layer 11 is made of SiOx. The passivation layer 11 has a thickness in the range of 1000 angstroms to 5000 angstroms.
Wherein the planarization layer 12 is disposed on a side of the passivation layer 11 away from the substrate 1. The material of the planarization layer 12 is an organic layer.
Wherein, the pixel electrode 13 is disposed on a side of the planarization layer 12 away from the substrate 1 and is electrically connected to the first drain electrode 101. Specifically, the pixel electrode 13 is electrically connected to the first drain electrode 101 through a via hole penetrating the planarization layer and the passivation layer. The pixel electrode 13 may have a stacked structure of indium tin oxide/silver/indium tin oxide.
The embodiment also provides a preparation method of the display panel of the embodiment, which comprises the following steps.
As shown in fig. 2, a substrate 1 is provided, and a light shielding layer 2 is prepared on the substrate 1.
As shown in fig. 3, a buffer layer 3 is prepared on the side of the light shielding layer 2 away from the substrate 1, and the buffer layer 3 extends to cover the substrate 1. A barrier layer 4 is prepared on the side of the buffer layer 3 remote from the substrate 1.
As shown in fig. 3 and 4, a first active layer 5 and a second active layer 6 are prepared on the side of the barrier layer 4 remote from the substrate 1. Specifically, an amorphous oxide is prepared on the side of the barrier layer 4 away from the substrate 1 to form a first active material layer 14, and a polycrystalline oxide is prepared on the side of the first active material layer 14 away from the substrate 1 to form a second active material layer 15. The first active material layer 14 is divided into the first channel portion 511, the second channel portion 521, the first contact portion 512, the second contact portion 513, the third contact portion 522, and the fourth contact portion 523. The second active material layer 15 and the first active material layer 14 are etched using a halftone mask 16. The halftone mask 16 includes a light shielding region 161, a semi-transparent region 162, and a full-transparent region 163, wherein the light shielding region 161 is disposed corresponding to the first channel portion 511, the third contact portion 522, and the fourth contact portion 523, and the semi-transparent region 162 is disposed corresponding to the first contact portion 512, the second contact portion 513, and the second channel portion 521. The photoresist layer 17 is provided on a side of the second active material layer 15 away from the substrate 1 at positions corresponding to the first channel portion 511, the second channel portion 521, the first contact portion 512, the second contact portion 513, the third contact portion 522, and the fourth contact portion 523, and the photoresist layer 17 corresponding to the first contact portion 512, the second contact portion 513, and the second channel portion 521 is thinned by an exposure and development process. In this embodiment, the thicknesses of the photoresist layers 17 corresponding to the first contact portion 512, the second contact portion 513, and the second channel portion 521 are the same, the thicknesses of the photoresist layers 17 corresponding to the first channel portion 511, the third contact portion 522, and the fourth contact portion 523 are the same, and the thicknesses of the photoresist layers 17 corresponding to the first contact portion 512 are smaller than the thicknesses of the photoresist layers 17 corresponding to the third contact portion 522. The first active material layer 14 and the second active material layer 15 are etched by a dry etching process to form the structure of fig. 5. After the etching is finished, the photoresist layer 17 needs to be stripped and removed to form the structure of fig. 3.
As shown in fig. 4, the second active portion material layer 15 is etched into a first polycrystalline oxide active portion 61, a second polycrystalline oxide active portion 62, and a third polycrystalline oxide active portion 63 that are spaced apart from each other, and the first active portion material layer 14 is etched into a first amorphous oxide active portion 51 and a second amorphous oxide active portion 52 that are spaced apart from each other. The first polycrystalline oxide active part 61 is provided corresponding to the first channel part 511, the second polycrystalline oxide active part 62 is provided corresponding to the third contact part 522, and the third polycrystalline oxide active part 63 is provided corresponding to the fourth contact part 523.
The embodiment utilizes the characteristics of high mobility of polycrystalline oxide, on-current and lower off-current similar to LTPS and better large-size uniformity, and solves the problem of poor large-size uniformity of LTPO backboard technology. The first polycrystalline oxide active part 61 is prepared on the first channel part 511 of the first amorphous oxide active part 51, an effect of a high mobility carrier channel is achieved by using a stacked structure formed by the first channel part 511 and the first polycrystalline oxide active part 61, and an effect of a low off-current is achieved by using a single layer structure of the first contact part 512 and the second contact part 513.
In this embodiment, the second polycrystalline oxide active part 62 and the third polycrystalline oxide active part 63 are respectively prepared on the third contact part 522 and the fourth contact part 523 of the second amorphous oxide active part 52, the effects of high stability and low off-current are achieved by using the single-layer structure of the second channel part 521, the ohmic contact characteristic with the second drain electrode 103 is optimized by using the stacked structure of the third contact part 522 and the second polycrystalline oxide active part 62, and the ohmic contact characteristic with the second source electrode 104 is optimized by using the stacked structure of the fourth contact part 523 and the third polycrystalline oxide active part 63.
In this embodiment, the half-tone mask is used to etch the first active portion material layer 14 and the second active portion material layer 15 simultaneously, which is beneficial to reducing the complexity of the process and improving the yield of the process.
As shown in fig. 6, a gate insulating layer 7 is prepared on a side of the second active layer 6 remote from the substrate 1. A first metal layer 8 is prepared on the side of the gate insulation layer 7 remote from the substrate 1. The first gate 81 and the second gate 82 are formed simultaneously, which is beneficial to reducing the complexity of the process and improving the yield of the process.
Specifically, a Top-gate self-aligned (Top-gate) structure formed by the gate insulating layer 7 and the first metal layer 8 is further included, and the single-layer amorphous oxide of the first contact portion 512, the single-layer amorphous oxide of the second contact portion 513, the stacked layer of amorphous oxide and polycrystalline oxide of the third contact portion 522, and the stacked layer of amorphous oxide and polycrystalline oxide of the fourth contact portion 523 are made conductive by He Plasma.
As shown in fig. 7, an interlayer insulating layer 9 is prepared on a side of the first metal layer 8 remote from the substrate 1. Specifically, the method further includes patterning and etching contact holes of the first drain electrode 101, the first source electrode 102, the second drain electrode 103, and the second source electrode 104.
As shown in fig. 8, a second metal layer 10 is prepared on the side of the interlayer insulating layer 9 remote from the substrate 1.
As shown in fig. 9, a passivation layer 11 and a planarization layer 12 are sequentially prepared on a side of the second metal layer 10 remote from the substrate 1. Specifically, the method further comprises patterning a Half-tone Mask (Half-tone Mask) to form a contact hole of the pixel electrode 13.
The foregoing describes a display panel and a method for manufacturing the same, wherein specific examples are used to illustrate the principles and embodiments of the present application, and the above examples are provided to assist in understanding the method and core ideas of the present application, and meanwhile, the present application should not be construed as being limited to the above description, since modifications in the specific embodiments and application range will be apparent to those skilled in the art based on the ideas of the present application.
Claims (10)
1. A display panel, comprising:
A substrate;
the first active layer is arranged on the substrate and is made of amorphous oxide, and comprises a first amorphous oxide active part and a second amorphous oxide active part which are mutually spaced;
The second active layer is arranged on one side of the first active layer, which is far away from the substrate, and is made of polycrystalline oxide and comprises a first polycrystalline oxide active part, a second polycrystalline oxide active part and a third polycrystalline oxide active part which are mutually spaced;
the first amorphous oxide active part comprises a first channel part, a first contact part and a second contact part which are respectively positioned at two ends of the first channel part, and the first polycrystalline oxide active part is arranged corresponding to the first channel part;
The second amorphous oxide active part comprises a second channel part, a third contact part and a fourth contact part, wherein the third contact part and the fourth contact part are respectively positioned at two ends of the second channel part, the second polycrystalline oxide active part is correspondingly arranged with the third contact part, and the third polycrystalline oxide active part is correspondingly arranged with the fourth contact part.
2. The display panel of claim 1, further comprising:
a light shielding layer arranged between the substrate and the first active layer and corresponding to the first amorphous oxide active part;
a buffer layer disposed between the light shielding layer and the first active layer, and
And the barrier layer is arranged between the buffer layer and the first active layer.
3. The display panel of claim 2, further comprising:
The gate insulating layer is arranged on one side of the second active layer, far away from the substrate, and comprises a first gate insulating unit and a second gate insulating unit which are respectively arranged corresponding to the first channel part and the second channel part;
The first metal layer is arranged on one side of the gate insulating layer, far away from the substrate, and comprises a first gate and a second gate which are respectively arranged corresponding to the first channel part and the second channel part;
the interlayer insulating layer is arranged on one side of the first metal layer far away from the substrate and extends to cover the barrier layer;
A second metal layer disposed on a side of the interlayer insulating layer away from the substrate, and including a first drain electrode, a first source electrode, a second drain electrode, and a second source electrode that are spaced apart from each other, wherein the first drain electrode, the first source electrode, the second drain electrode, and the second source electrode are electrically connected to the first contact portion, the second contact portion, the third contact portion, and the fourth contact portion, respectively;
the passivation layer is arranged on one side of the second metal layer away from the substrate;
a planarization layer disposed on a side of the passivation layer away from the substrate, and
And the pixel electrode is arranged on one side of the flat layer away from the substrate and is electrically connected to the first drain electrode.
4. The display panel of claim 2, wherein a projection of the first amorphous oxide active portion onto the substrate falls within a projection of the light shielding layer onto the substrate.
5. The display panel of claim 2, wherein the barrier layer comprises one or more of aluminum oxide, hafnium oxide, zirconium oxide, and yttrium oxide, and the barrier layer has a thickness in a range of 100 angstroms to 500 angstroms.
6. A method for manufacturing a display panel, comprising the steps of:
Providing a substrate;
Preparing an amorphous oxide on the substrate to form a first active part material layer;
Preparing a polycrystalline oxide on one side of the first active part material layer far from the substrate to form a second active part material layer;
Etching the second active part material layer and the first active part material layer by using a half-tone photomask, wherein the second active part material layer is etched into a first polycrystalline oxide active part, a second polycrystalline oxide active part and a third polycrystalline oxide active part which are mutually spaced, and the first active part material layer is etched into a first amorphous oxide active part and a second amorphous oxide active part which are mutually spaced;
the first amorphous oxide active part comprises a first channel part, a first contact part and a second contact part which are respectively positioned at two ends of the first channel part, and the first polycrystalline oxide active part is arranged corresponding to the first channel part;
The second amorphous oxide active part comprises a second channel part, a third contact part and a fourth contact part, wherein the third contact part and the fourth contact part are respectively positioned at two ends of the second channel part, the second polycrystalline oxide active part is correspondingly arranged with the third contact part, and the third polycrystalline oxide active part is correspondingly arranged with the fourth contact part.
7. The method of manufacturing a display panel according to claim 6, wherein the etching the second active material layer and the first active material layer using a halftone mask comprises:
dividing the first active portion material layer into the first channel portion, the second channel portion, the first contact portion, the second contact portion, the third contact portion, and the fourth contact portion;
The half-tone light modulation cover comprises a light shielding area, a semi-permeable area and a full-permeable area, wherein the light shielding area is correspondingly arranged with the first channel part, the third contact part and the fourth contact part, and the semi-permeable area is correspondingly arranged with the first contact part, the second contact part and the second channel part.
8. The method of manufacturing a display panel according to claim 7, wherein the step of etching the second active material layer and the first active material layer using a halftone mask further comprises:
providing a photoresist layer on a side of the second active portion material layer away from the substrate at positions corresponding to the first channel portion, the second channel portion, the first contact portion, the second contact portion, the third contact portion, and the fourth contact portion;
And thinning the photoresist layer corresponding to the first contact part, the second contact part and the second channel part through an exposure and development process.
9. The method of manufacturing a display panel according to claim 8, wherein the thicknesses of the photoresist layers corresponding to the first contact portion, the second contact portion, and the second channel portion are the same as the thicknesses of the photoresist layers corresponding to the first channel portion, the third contact portion, and the fourth contact portion.
10. The method of manufacturing a display panel according to claim 8, wherein the step of etching the second active material layer and the first active material layer using a halftone mask further comprises:
Etching the first active part material layer and the second active part material layer by a dry etching process, and
And stripping and removing the photoresist layer.
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| CN102655165A (en) * | 2011-03-28 | 2012-09-05 | 京东方科技集团股份有限公司 | Amorphous-oxide thin-film transistor, manufacturing method thereof, and display panel |
| CN105304650A (en) * | 2015-11-04 | 2016-02-03 | 深圳市华星光电技术有限公司 | Thin-film transistor array substrate and preparation method and display device thereof |
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| CN114975486B (en) * | 2022-06-20 | 2025-06-03 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel and method for manufacturing array substrate |
| CN115483227B (en) * | 2022-08-16 | 2025-09-09 | Tcl华星光电技术有限公司 | Array substrate, manufacturing method thereof and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102655165A (en) * | 2011-03-28 | 2012-09-05 | 京东方科技集团股份有限公司 | Amorphous-oxide thin-film transistor, manufacturing method thereof, and display panel |
| CN105304650A (en) * | 2015-11-04 | 2016-02-03 | 深圳市华星光电技术有限公司 | Thin-film transistor array substrate and preparation method and display device thereof |
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