CN117456900A - Pixel driving circuit and display panel - Google Patents
Pixel driving circuit and display panel Download PDFInfo
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- CN117456900A CN117456900A CN202311346670.4A CN202311346670A CN117456900A CN 117456900 A CN117456900 A CN 117456900A CN 202311346670 A CN202311346670 A CN 202311346670A CN 117456900 A CN117456900 A CN 117456900A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The invention provides a pixel driving circuit and a display panel, wherein the pixel driving circuit comprises a pulse width modulation module electrically connected with a light-emitting control line and a sweep frequency signal, when the pulse width modulation module responds to the light-emitting control signal transmitted by the light-emitting control line to transmit the sweep frequency signal transmitted by the sweep frequency signal line to a third node, the potential of the control end of a first driving transistor is coupled through a first capacitor included by the pulse width modulation module, and the first driving transistor is controlled to switch between a conducting state and a cut-off state, so that the adjustment of display brightness is realized by adjusting the light-emitting time of a light-emitting device under the condition that driving current is unchanged, and the aim of gray scale segmentation is fulfilled. When the pixel driving circuit is applied to the display panel, the pulse width modulation module is matched with the sweep frequency signals to control the light emitting time of the plurality of sub-pixels, so that the gray scale segmentation under the low gray scale display picture is realized, the light emitting device is prevented from working in an unstable efficiency interval, and the display uniformity of the display panel is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a pixel driving circuit and a display panel.
Background
The chip working current interval of the submillimeter light emitting device (Mini LED) has larger efficiency variation, particularly has obvious variation range in a low current interval (as shown in figure 1), and is easy to cause the problem of poor uniformity of a display picture. The traditional Mini LED pixel driving circuit is pure pulse amplitude modulation driving, the switching of different gray scales is realized only by changing the magnitude of current amplitude, and the actual picture display with low current and low gray scale has serious pits and poor display uniformity. Wherein A1 represents an efficiency-unstable region, and A2 represents an efficiency-stable region.
Disclosure of Invention
The embodiment of the invention provides a pixel driving circuit and a display panel, which can solve the problem of poor display uniformity.
The embodiment of the invention provides a pixel driving circuit which comprises a light emitting device, a pulse amplitude modulation module and a pulse width modulation module. The light emitting device is electrically connected between the first node and the first power supply end; the pulse amplitude modulation module comprises a first driving transistor and a first capacitor; the control end of the first driving transistor is electrically connected with the second node, the input end of the first driving transistor is electrically connected with the second power supply end, and the output end of the first driving transistor is electrically connected with the first node; the first end of the first capacitor is electrically connected with the second node, and the second end of the first capacitor is electrically connected with the third node. The pulse width modulation module is electrically connected with the third node, the light-emitting control line and the sweep frequency signal line, and is configured to respond to the light-emitting control signal transmitted by the light-emitting control line and transmit the sweep frequency signal transmitted by the sweep frequency signal line to the third node so as to couple the potential of the second node through the first capacitor and control the first driving transistor to switch between a conducting state and a cut-off state according to the potential of the second node.
Optionally, in some embodiments of the present invention, when the pulse width modulation module transmits the sweep signal to the third node in response to the light emission control signal, the sweep signal is a triangular wave signal.
Optionally, in some embodiments of the present invention, the pulse width modulation module includes a first switching transistor, a control end of the first switching transistor is electrically connected to the light emitting control line, an input end of the first switching transistor is electrically connected to the frequency sweeping signal line, and an output end of the first switching transistor is electrically connected to the third node.
Optionally, in some embodiments of the present invention, the pulse width modulation module includes a first reset transistor, a control end of the first reset transistor is electrically connected to the first scan line, an input end of the first reset transistor is electrically connected to the first reset line, and an output end of the first reset transistor is electrically connected to the third node.
Optionally, in some embodiments of the present invention, the pulse width modulation module includes a second driving transistor, a first data transistor, and a second capacitor. The input end of the second driving transistor is electrically connected with the third node, and the output end of the second driving transistor is electrically connected with the output end of the first switching transistor. The control end of the first data transistor is electrically connected with the second scanning line, and the input end of the first data transistor is configured to receive pulse width modulation voltage. The first end of the second capacitor is electrically connected to the output end of the first data transistor, and the second end of the second capacitor is electrically connected to the control end of the second driving transistor.
Optionally, in some embodiments of the present invention, the pulse amplitude modulation module includes a first compensation transistor and a second reset transistor. The control end of the first compensation transistor is electrically connected with the first scanning line, the input end of the first compensation transistor is electrically connected with the output end of the second driving transistor, and the output end of the first compensation transistor is electrically connected with the first end of the second capacitor. The control end of the second reset transistor is electrically connected with the first scanning line, the input end of the second reset transistor is electrically connected with the second reset line, and the output end of the second reset transistor is electrically connected with the control end of the second driving transistor.
Optionally, in some embodiments of the invention, the pulse amplitude modulation module includes a second compensation transistor and a second data transistor. The control end of the second compensation transistor is electrically connected with the second scanning line, the input end of the second compensation transistor is electrically connected with the output end of the first driving transistor, and the output end of the second compensation transistor is electrically connected with the second node. The control end of the second data transistor is electrically connected with the second scanning line, the input end of the second data transistor is configured to receive pulse amplitude modulation voltage, and the output end of the second data transistor is electrically connected with the input end of the first driving transistor.
Optionally, in some embodiments of the present invention, the pulse amplitude modulation module includes a third reset transistor, a control end of the third reset transistor is electrically connected to the first scan line, an input end of the third reset transistor is electrically connected to the second reset line, and an output end of the third reset transistor is electrically connected to the second node.
Optionally, in some embodiments of the invention, the pulse amplitude modulation module includes a second switching transistor and a third switching transistor. The control end of the second switch transistor is electrically connected with the light-emitting control line, the input end of the second switch transistor is electrically connected with the second power end, and the output end of the second switch transistor is electrically connected with the input end of the first drive transistor. The control end of the third switch transistor is electrically connected with the light-emitting control line, the input end of the third switch transistor is electrically connected with the first node, and the output end of the third switch transistor is electrically connected with the light-emitting device.
The embodiment of the invention also provides a display panel, which comprises a plurality of sub-pixels, wherein at least one sub-pixel comprises any one of the pixel driving circuits.
The embodiment of the invention provides a pixel driving circuit and a display panel, wherein the pixel driving circuit comprises a pulse width modulation module electrically connected with a light-emitting control line and a sweep frequency signal, when the pulse width modulation module responds to the light-emitting control signal transmitted by the light-emitting control line to transmit the sweep frequency signal transmitted by the sweep frequency signal line to a third node, the potential of the control end of a first driving transistor is coupled through a first capacitor included in the pulse width modulation module, and the first driving transistor is controlled to switch between a conducting state and a cut-off state, so that the adjustment of display brightness is realized by adjusting the light-emitting time of a light-emitting device under the condition that driving current is unchanged, and the aim of gray scale segmentation is fulfilled. When the pixel driving circuit is applied to the display panel, the pulse width modulation module is matched with the sweep frequency signals to control the first driving transistors of the plurality of sub-pixels to be continuously turned on or turned off during low gray scale display so as to control the light emitting duration of the light emitting device, realize gray scale segmentation under a low gray scale display picture, avoid the light emitting device from working in an unstable efficiency interval and improve the display uniformity of the display panel.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a graph of the operating efficiency of a sub-millimeter light emitting diode chip;
fig. 2 is a schematic diagram of a pixel driving circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram provided by an embodiment of the present invention;
FIG. 4 is a timing diagram of a swept frequency signal according to an embodiment of the invention;
FIG. 5 is a schematic diagram of simulated ash cutting results provided by an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and description only, and is not intended to limit the invention. In the present invention, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
According to the pixel driving circuit, the pulse width modulation module is included in the pixel driving circuit, so that the adjustment of the light emitting time of the light emitting device is realized through the pulse width modulation module under the condition that the driving current is unchanged, the adjustment of the display brightness is realized, the purpose of gray scale segmentation is achieved, and the pixel driving circuit has the current gray scale cutting capability and the light emitting time gray scale cutting capability.
Specifically, fig. 2 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention. The invention provides a pixel driving circuit, which comprises a light emitting device Di, a pulse amplitude modulation module 100 and a pulse width modulation module 200.
The light emitting device Di is electrically connected between the first node N1 and the first power terminal VSS. Optionally, an anode of the light emitting device Di is electrically connected to the first node N1, and a cathode of the light emitting device Di is electrically connected to the first power supply terminal VSS.
Optionally, the light emitting device Di includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, and the like.
With continued reference to fig. 2, the pulse amplitude modulation module 100 is electrically connected to the light emitting device Di, and the pulse amplitude modulation module 100 is configured to control the amplitude of the driving current according to the pulse amplitude modulation voltage data_pam.
Optionally, the pulse amplitude modulation module 100 includes a first driving transistor Tdr1 and a first capacitor C1.
The control end of the first driving transistor Tdr1 is electrically connected to the second node N2, the input end of the first driving transistor Tdr1 is electrically connected to the second power supply end VDD, and the output end of the first driving transistor Tdr1 is electrically connected to the first node N1. The first driving transistor Tdr1 is configured to generate the driving current to drive the light emitting device Di to emit light.
The first end of the first capacitor C1 is electrically connected to the second node N2, and the second end of the first capacitor C1 is electrically connected to the third node N3. The first capacitance C1 is configured to couple the potential of the second node N2 according to the potential of the third node N3.
With continued reference to fig. 2, the pulse width modulation module 200 is electrically connected to the third node N3, the light emission control line EML and the frequency Sweep signal line SWL, and the pulse width modulation module 200 is configured to respond to the light emission control signal EM transmitted by the light emission control line EML to transmit the frequency Sweep signal Sweep transmitted by the frequency Sweep signal line SWL to the third node N3, so as to couple the potential of the second node N2 through the first capacitor C1, and control the first driving transistor Tdr1 to switch between the on state and the off state according to the potential of the second node N2, so as to achieve the purpose of gray scale segmentation by adjusting the light emission duration of the light emitting device Di under the condition that the driving current is unchanged. When the pixel driving circuit is applied to the display panel, the pulse width modulation module 200 is matched with the Sweep frequency signal Sweep to control the first driving transistor Tdr1 of the plurality of sub-pixels to be continuously turned on or turned off during low-gray-scale display so as to control the light emitting duration of the light emitting device Di, realize gray scale segmentation under a low-gray-scale display picture, avoid the light emitting device Di from working in an efficiency unstable region and improve the display uniformity of the display panel.
Optionally, when the pulse width modulation module 200 transmits the Sweep signal Sweep to the third node N3 in response to the light emission control signal EM, the Sweep signal Sweep is a triangular wave signal to control the first driving transistor Tdr1 to be switchable between an on state and an off state.
Optionally, referring to fig. 2, the pulse width modulation module 200 includes a first switching transistor Ts1, a control end of the first switching transistor Ts1 is electrically connected to the emission control line EML, an input end of the first switching transistor Ts1 is electrically connected to the sweep signal line SWL, and an output end of the first switching transistor Ts1 is electrically connected to the third node N3. The first switching transistor Ts1 is configured to be turned on or off according to the emission control signal EM.
Optionally, referring to fig. 2, the pulse width modulation module 200 includes a first reset transistor Ti1, a control end of the first reset transistor Ti1 is electrically connected to the first scan line SL1, an input end of the first reset transistor Ti1 is electrically connected to the first reset line VL1, an output end of the first reset transistor Ti1 is electrically connected to the third node N3, and the first reset transistor Ti1 is configured to be turned on or turned off according to a first scan signal S1 transmitted by the first scan line SL1, so that when the first reset transistor Ti1 is turned on, the first reset line VL1 is electrically connected to the third node N3, so that the first reset signal VI1 transmitted by the first reset line VL1 is transmitted to the third node N3, so as to reset the electrical property of the third node N3.
Optionally, referring to fig. 2, the pulse width modulation module 200 includes a second driving transistor Tdr2, a first compensation transistor Tc1, a first data transistor Tda1, a second reset transistor Ti2, and a second capacitor C2.
The input end of the second driving transistor Tdr2 is electrically connected to the third node N3, and the output end of the second driving transistor Tdr2 is electrically connected to the output end of the first switching transistor Ts 1.
The control end of the first compensation transistor Tc1 is electrically connected to the first scan line SL1, the input end of the first compensation transistor Tc1 is electrically connected to the output end of the second driving transistor Tdr2, and the output end of the first compensation transistor Tc1 is electrically connected to the first end of the second capacitor C2.
The control end of the first Data transistor Tda1 is electrically connected to the second scan line SL2, the input end of the first Data transistor Tda1 is configured to receive the pulse width modulation voltage data_pwm, and the output end of the first Data transistor Tda1 is electrically connected to the first end of the second capacitor C2.
The control end of the second reset transistor Ti2 is electrically connected to the first scan line SL1, the input end of the second reset transistor Ti2 is electrically connected to the second reset line VL2, and the output end of the second reset transistor Ti2 is electrically connected to the control end of the second driving transistor Tdr2.
The first end of the second capacitor C2 is electrically connected to the output end of the first data transistor Tda1, and the second end of the second capacitor C2 is electrically connected to the control end of the second driving transistor Tdr2.
Wherein the first Data transistor Tda1 is configured to be turned on or off according to a second scan signal S2 transmitted by the second scan line SL2 to transmit the pulse width modulation voltage data_pwm to the first end of the second capacitor C2 when the first Data transistor Tda1 is turned on. The second capacitor C2 is configured to detect and store the threshold voltage of the second driving transistor Tdr2 according to the first reset signal VI1 and the second reset signal VI2 when the first compensation transistor Tc1 is turned on; and the second capacitor C2 is configured to couple the potential of the control terminal of the second driving transistor Tdr2 according to the pulse width modulation voltage data_pwm to compensate the threshold voltage of the second driving transistor Tdr2 when the first Data transistor Tda1 is turned on. The second reset transistor Ti2 is configured to transmit a second reset signal VI2 transmitted by the second reset line VL2 to the control terminal of the second driving transistor Tdr2 according to the first scan signal S1 transmitted by the first scan line SL1 to initialize the potential of the control terminal of the second driving transistor Tdr2. The first compensation transistor Tc1 is configured to electrically connect the control terminal of the second driving transistor Tdr2 with the output terminal of the second driving transistor Tdr2 according to the first scan signal S1, or disconnect the electrical connection between the control terminal of the second driving transistor Tdr2 and the output terminal of the second driving transistor Tdr2.
Optionally, referring to fig. 2, the pulse amplitude modulation module 100 includes a second compensation transistor Tc2 and a second data transistor Tda2.
The control end of the second compensation transistor Tc2 is electrically connected to the second scan line SL2, the input end of the second compensation transistor Tc2 is electrically connected to the output end of the first driving transistor Tdr1, and the output end of the second compensation transistor Tc2 is electrically connected to the second node N2.
The control terminal of the second Data transistor Tda2 is electrically connected to the second scan line SL2, the input terminal of the second Data transistor Tda2 is configured to receive the pulse amplitude modulation voltage data_pam, and the output terminal of the second Data transistor Tda2 is electrically connected to the input terminal of the first driving transistor Tdr1.
The second Data transistor Tda2 is configured to be turned on or off according to a second scan signal S2 transmitted by the second scan line SL2 to transmit the pulse amplitude modulation voltage data_pam to the input terminal of the first driving transistor Tdr1 when the second Data transistor Tda2 is turned on. The second compensation transistor Tc2 is configured to be turned on or off according to the second scan signal S2 transmitted by the second scan line SL2, so as to electrically connect the output terminal of the first driving transistor Tdr1 and the second node N2 when the second compensation transistor Tc2 is turned on. The threshold voltage of the first driving transistor Tdr1 is detected by the pulse amplitude modulation voltage data_pam, the second Data transistor Tda2 and the second compensation transistor Tc2, and the threshold voltage of the first driving transistor Tdr1 is stored by the first capacitor C1.
Optionally, referring to fig. 2, the pulse amplitude modulation module 100 includes a third reset transistor Ti3, a control end of the third reset transistor Ti3 is electrically connected to the first scan line SL1, an input end of the third reset transistor Ti3 is electrically connected to the second reset line VL2, and an output end of the third reset transistor Ti3 is electrically connected to the second node N2. The third reset transistor Ti3 is configured to be turned on or off according to the first scan signal S1 transmitted by the first scan line SL1, so as to electrically connect the second reset line VL2 and the second node N2 when the third reset transistor Ti3 is turned on, thereby transmitting the second reset signal VI2 transmitted by the second reset line VL2 to the second node N2, and initializing the potential of the second node N2 by the second reset signal VI 2.
Optionally, referring to fig. 2, the pulse amplitude modulation module 100 includes a second switching transistor Ts2 and a third switching transistor Ts3. The control end of the second switching transistor Ts2 is electrically connected to the emission control line EML, the input end of the second switching transistor Ts2 is electrically connected to the second power supply end VDD, and the output end of the second switching transistor Ts2 is electrically connected to the input end of the first driving transistor Tdr1. The control end of the third switching transistor Ts3 is electrically connected to the emission control line EML, the input end of the third switching transistor Ts3 is electrically connected to the first node N1, and the output end of the third switching transistor Ts3 is electrically connected to the light emitting device Di.
Wherein the second switching transistor Ts2 is configured to be turned on or off according to the emission control signal EM transmitted by the emission control line EML, so as to electrically connect the second power supply terminal VDD and the input terminal of the first driving transistor Tdr1 when the second switching transistor Ts2 is turned on; the third switching transistor Ts3 is configured to be turned on or off according to a light emission control signal EM transmitted from the light emission control line EML to electrically connect the first node N1 and the light emitting device Di when the third switching transistor Ts3 is turned on, thereby causing the first driving transistor Tdr1 to generate a driving current between the second power supply terminal VDD and the first power supply terminal VSS.
Optionally, the first driving transistor Tdr1, the second driving transistor Tdr2, the first data transistor Tda1, the second data transistor Tda2, the first compensation transistor Tc1, the second compensation transistor Tc2, the first reset transistor Ti1, the second reset transistor Ti2, the third reset transistor Ti3, the first switching transistor Ts1, the second switching transistor Ts2 and the third switching transistor Ts3 may be N-type transistors or P-type transistors, the first driving transistor Tdr1, the second driving transistor Tdr2, the first data transistor Tda1, the second data transistor Tda2, the first compensation transistor Tc1, the second reset transistor Ti2, the first reset transistor Ti1, the second reset transistor Ti2, the third switching transistor Ts3, the first reset transistor Ti3, the first switching transistor Ti3 and the third switching transistor Ts2 may be an oxide semiconductor material Ts2 or a semiconductor material Ts.
Fig. 3 is a timing chart provided by an embodiment of the present invention, and fig. 4 is a timing chart of a Sweep signal Sweep provided by an embodiment of the present invention; the operation principle of the pixel driving circuit provided in the present application will be described by taking the first driving transistor Tdr1, the second driving transistor Tdr2, the first data transistor Tda1, the second data transistor Tda2, the first compensation transistor Tc1, the second compensation transistor Tc2, the first reset transistor Ti1, the second reset transistor Ti2, the third reset transistor Ti3, the first switching transistor Ts1, the second switching transistor Ts2, and the third switching transistor Ts3 as examples. Where t represents time and U represents voltage.
First stage t1: the first scan signal S1 is at a low level, and the second scan signal S2, the emission control signal EM, and the Sweep signal Sweep are at a high level.
The first reset transistor Ti1, the second reset transistor Ti2, the third reset transistor Ti3 and the first compensation transistor Tc1 are turned on, and the first reset signal VI1 is transmitted to the third node N3 to reset the potential of the third node N3; the second reset signal VI2 is transmitted to the control terminal of the second driving transistor Tdr2 to reset the control terminal of the second driving transistor Tdr2, and the second reset signal VI2 is transmitted to the control terminal of the first driving transistor Tdr1 to reset the potential of the control terminal of the first driving transistor Tdr1. The first reset signal VI1 charges the second capacitor C2 through the first reset transistor Ti1, the second driving transistor Tdr2, and the first compensation transistor Tc1 until the second driving transistor Tdr2 is turned off, and the second capacitor C2 stores a voltage that is the threshold voltage vth_tdr2 of the second driving transistor Tdr2.
Second stage t2: the second scan signal S2 is at a low level, and the first scan signal S1, the emission control signal EM, and the Sweep signal Sweep are at a high level.
The first Data transistor Tda1, the second Data transistor Tda2 and the second compensation transistor Tc2 are turned on according to the second scan signal S2, and the pulse width modulation voltage data_pwm is transmitted to the first terminal of the second capacitor C2 to couple the potential of the control terminal of the second driving transistor Tdr2 through the second capacitor C2, such that the potential of the control terminal of the second driving transistor Tdr2 is coupled to data_pwm+vth_tdr2. The pulse amplitude modulation voltage data_pam charges the control end of the first driving transistor Tdr1 until the first driving transistor Tdr1 is turned off, so that the potential of the control end of the first driving transistor Tdr1 is data_pam+vth_tdr1. Wherein vth_tdr1 represents a threshold voltage of the first driving transistor Tdr1.
Third stage t3: the light emission control signal EM is at a low level, and the first scan signal S1 and the second scan signal S2 are at a high level.
The first switching transistor Ts1, the second switching transistor Ts2, and the third switching transistor Ts3 are turned on according to the emission control signal EM, and the driving current is generated between the second power supply terminal VDD and the first power supply terminal VSS to drive the light emitting device Di to emit light. Meanwhile, as the voltage of the Sweep signal Sweep increases, the potential of the output terminal of the second driving transistor Tdr2 increases continuously, when the voltage difference between the control terminal and the output terminal of the second driving transistor Tdr2 (i.e., vgs_tdr2) is smaller than the threshold voltage of the second driving transistor Tdr2 (i.e., vgs_tdr2< vth_tdr2), the second driving transistor Tdr2 is turned on, the Sweep signal Sweep is transmitted to the third node N3, and the potential of the second node N2 is coupled to increase via the first capacitor C1, the first driving transistor Tdr1 is turned off, and the light emitting device Di stops emitting light. Then, the voltage corresponding to the Sweep signal Sweep may be gradually reduced. Accordingly, as the voltage of the Sweep signal Sweep decreases, the potential of the second node N2 is coupled to gradually decrease through the first capacitor C1 until the first driving transistor Tdr1 is turned on again, and the light emitting device Di starts to emit light again.
Wherein, in the third stage t3, the driving current i=k (vgs_tdr1-vth_tdr1)/(2=k (data_pam-VDD)/(2) driving the light emitting device to emit light. Where vgs_tdr1 represents a gate-source voltage difference of the first driving transistor; k= (coxμnw)/2L; cox, μn, W, and L represent channel capacitance per unit area, channel mobility, channel width, and channel length, respectively. Thus, by modulating the magnitude of the pulse amplitude modulation voltage data_pam, the magnitude of the driving current can be adjusted.
By gradually increasing and gradually decreasing the voltage cycle of the Sweep signal Sweep in the third phase t3 (i.e., the trend of the Sweep signal Sweep in the third phase may be as shown in fig. 4), the cycle control of the light emission and non-light emission of the light emitting device Di may be realized, and the light emission duty ratio of the light emitting device Di may be improved.
Therefore, unlike the conventional pixel circuit including the pulse amplitude modulation module 100 and the pulse width modulation module 200, the pixel driving circuit provided in the present application directly acts on the control end of the first driving transistor Tdr1 by using the Sweep signal, and can control the on/off of the pulse amplitude modulation module 100 by controlling the amplitude variation of the voltage of the Sweep signal Sweep, without introducing other auxiliary signals, which is beneficial to improving the light emitting duty ratio of the pixel driving circuit.
FIG. 5 is a schematic diagram of simulated ash cutting results provided by an embodiment of the present invention; wherein L1 to L5 represent drive current curves. The inventor of the application carries out simulation analysis on the pixel driving circuit provided by the application, and the analysis result shows that: the high-level durations of L1 to L5 are different, and accordingly, the light emitting durations of the light emitting devices Di are also different, so that the pixel driving circuit provided by the application can control the light emitting durations of the light emitting devices Di through the pulse width modulation module 200 to realize the function of dividing gray scales.
Fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention. The embodiment of the application further provides a display panel, which comprises a plurality of sub-pixels Pi, wherein at least one sub-pixel Pi comprises any one of the above pixel driving circuits.
Optionally, when the display panel displays at a low gray scale, and the pulse width modulation module 200 transmits the Sweep signal Sweep to the third node N3 in response to the light emission control signal EM, the Sweep signal Sweep is a triangular wave signal.
Specifically, when the first switching transistor Ts1 is turned on according to the emission control signal EM, the Sweep signal Sweep may be a triangular wave signal. Accordingly, the light emitting device Di switches between a light emitting state and a non-light emitting state according to the change of the Sweep signal Sweep.
Optionally, when the display panel displays in high gray scale and the pulse width modulation module 200 transmits the Sweep signal Sweep to the third node N3 in response to the light emission control signal EM, the Sweep signal Sweep may be a triangular wave signal to reduce the control complexity of the Sweep signal Sweep. When the display panel displays with high gray scale, the current gray scale cutting capability is realized by the pulse amplitude modulation module 100.
Alternatively, when the display panel displays in high gray scale, the amplitude of the pulse width modulation voltage data_pwm may be controlled, so that the second driving transistor Tdr2 cannot be turned on when the Sweep signal Sweep gradually increases, and then the control of the light emitting duration of the light emitting device Di cannot be implemented when the Sweep signal Sweep displays in high gray scale. That is, when the display panel displays at a high gray scale, the pulse width modulation voltage data_pwm is larger, and when the pulse width modulation voltage data_pwm is coupled to the control terminal of the second driving transistor Tdr2 through the second capacitor C2, the potential of the control terminal of the second driving transistor Tdr2 is higher. Then, when the first switching transistor Ts1 is turned on, even if the Sweep signal Sweep is gradually increased, the voltage difference between the control terminal and the output terminal of the second driving transistor Tdr2 still satisfies the on condition, resulting in the second driving transistor Tdr2 remaining turned off, which in turn results in the Sweep signal Sweep not being transmitted to the third node N3, so that the control of the light emitting duration of the light emitting device Di cannot be achieved when the display panel displays in high gray scale.
Optionally, when the display panel displays in high gray scale and the pulse width modulation module 200 transmits the Sweep signal Sweep to the third node N3 in response to the light emission control signal EM, the Sweep signal Sweep may be a constant signal, so that when the display panel displays in high gray scale, the pulse width modulation module 100 adjusts the current to achieve gray scale division and reduce the power consumption; when the display panel displays with low gray scale, the pulse width modulation module 200 adjusts the light emitting time of the light emitting device Di to realize gray scale division, so as to avoid the light emitting device Di (such as a sub-millimeter light emitting diode) chip from working in an unstable efficiency region.
Optionally, the plurality of subpixels Pi included in the display panel share the same Sweep signal Sweep.
Alternatively, the display panel may further uniformly enter the third stage t3 after the sub-pixels Pi all go through the first stage t1 and the second stage t 2. Accordingly, since the same Sweep signal Sweep corresponds to a plurality of sub-pixels Pi, each sub-pixel Pi corresponds to the Sweep signal Sweep at different times in each frame, and when the number of frames is sufficient, the timing of the Sweep signal Sweep corresponding to each sub-pixel Pi may be regarded as uniform.
If the Sweep signal Sweep is only a simple ramp signal design in the third stage t3, the second driving transistor Tdr2 of each sub-pixel Pi is turned on under the influence of the Sweep signal Sweep, and then the second reset signal VI2 is required to be transmitted to the control terminal of the second driving transistor Tdr2 until the next frame, so that the second driving transistor Tdr2 is turned off, and the pulse width modulation module 200 stops working, and in this case, only the plurality of sub-pixels Pi of all rows in the display panel can be fully lighted after the data is written.
When the Sweep signal Sweep is set to be a triangular wave signal in the third stage t3, the second driving transistor Tdr2 may be turned on to operate the pwm module 200 in a stage where the voltage of the Sweep signal Sweep gradually increases; in the stage that the voltage of the Sweep signal Sweep gradually decreases, the second driving transistor Tdr2 may be turned off again, so that the pwm module 200 is turned off, and it is no longer necessary to wait until the second reset signal VI2 is transmitted to the control terminal of the second driving transistor Tdr2 in the next frame, so as to achieve the control of turning off and on the pwm module 200. Therefore, each sub-pixel Pi can be continuously cycled between a light emitting state and an off state within one frame, so that light can be emitted after writing data in one row, thereby realizing progressive scanning light emission setting and improving the light emitting duty ratio of the circuit.
Optionally, the display panel further includes a gate driving unit including a plurality of cascaded gate driving circuits. The first scanning signal and the second scanning signal corresponding to each pixel driving circuit can be generated by gate driving circuits with different stages in the gate driving unit. The first Scan signal S1 applied by the pixel driving circuit included in the sub-pixel located in the nth row is the gate control signal Scan (n-1) generated by the n-1 th stage gate driving circuit, and the second Scan signal S2 applied by the pixel driving circuit included in the sub-pixel located in the nth row is the gate control signal Scan (n) generated by the n-1 th stage gate driving circuit. Wherein n is greater than or equal to 1. The same grid driving unit is utilized to provide the corresponding first scanning signals S1 and second scanning signals S2 for the pixel driving circuits of a plurality of sub-pixels, so that the number of the grid driving units applied to the display panel is reduced, the frame width of the display panel occupied by the grid driving units is reduced, the number of used control signals is reduced, and the power consumption and the control complexity are reduced.
According to the method and the device, the amplitude change of the voltage of the Sweep frequency signal Sweep is controlled, so that each sub-pixel Pi in the display panel continuously circulates between the light-emitting state and the off state in one frame, progressive scanning light emission is achieved through controlling the waveform of the Sweep frequency signal Sweep, the improvement of the light-emitting duty ratio is facilitated, and the method and the device are suitable for high-resolution panel design.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present invention, the present description should not be construed as limiting the present invention.
Claims (10)
1. A pixel driving circuit, comprising:
the light-emitting device is electrically connected between the first node and the first power supply end;
the pulse amplitude modulation module comprises a first driving transistor and a first capacitor; the control end of the first driving transistor is electrically connected with the second node, the input end of the first driving transistor is electrically connected with the second power supply end, and the output end of the first driving transistor is electrically connected with the first node; the first end of the first capacitor is electrically connected with the second node, and the second end of the first capacitor is electrically connected with the third node;
the pulse width modulation module is electrically connected with the third node, the light-emitting control line and the sweep frequency signal line and is configured to respond to the light-emitting control signal transmitted by the light-emitting control line and transmit the sweep frequency signal transmitted by the sweep frequency signal line to the third node so as to couple the potential of the second node through the first capacitor and control the first driving transistor to switch between an on state and an off state according to the potential of the second node.
2. The pixel driving circuit according to claim 1, wherein the pulse width modulation module is configured to transmit the sweep signal to the third node in response to the emission control signal, the sweep signal being a triangular wave signal.
3. The pixel driving circuit according to claim 1, wherein the pulse width modulation module comprises:
the control end of the first switch transistor is electrically connected with the light-emitting control line, the input end of the first switch transistor is electrically connected with the sweep frequency signal line, and the output end of the first switch transistor is electrically connected with the third node.
4. A pixel driving circuit according to claim 3, wherein the pulse width modulation module comprises:
the control end of the first reset transistor is electrically connected with the first scanning line, the input end of the first reset transistor is electrically connected with the first reset line, and the output end of the first reset transistor is electrically connected with the third node.
5. The pixel driving circuit according to claim 4, wherein the pulse width modulation module comprises:
the input end of the second driving transistor is electrically connected with the third node, and the output end of the second driving transistor is electrically connected with the output end of the first switching transistor;
a first data transistor having a control terminal electrically connected to the second scan line, the input terminal configured to receive a pulse width modulated voltage; and
the first end of the second capacitor is electrically connected with the output end of the first data transistor, and the second end of the second capacitor is electrically connected with the control end of the second driving transistor.
6. The pixel driving circuit according to claim 5, wherein the pulse amplitude modulation module comprises:
the control end of the first compensation transistor is electrically connected with the first scanning line, the input end of the first compensation transistor is electrically connected with the output end of the second driving transistor, and the output end of the first compensation transistor is electrically connected with the first end of the second capacitor;
the control end of the second reset transistor is electrically connected with the first scanning line, the input end of the second reset transistor is electrically connected with the second reset line, and the output end of the second reset transistor is electrically connected with the control end of the second driving transistor.
7. The pixel driving circuit according to claim 1, wherein the pulse amplitude modulation module comprises:
the control end of the second compensation transistor is electrically connected with the second scanning line, the input end of the second compensation transistor is electrically connected with the output end of the first driving transistor, and the output end of the second compensation transistor is electrically connected with the second node;
and the control end of the second data transistor is electrically connected with the second scanning line, the input end of the second data transistor is configured to receive pulse amplitude modulation voltage, and the output end of the second data transistor is electrically connected with the input end of the first driving transistor.
8. The pixel driving circuit according to claim 7, wherein the pulse amplitude modulation module comprises:
the control end of the third reset transistor is electrically connected with the first scanning line, the input end of the third reset transistor is electrically connected with the second reset line, and the output end of the third reset transistor is electrically connected with the second node.
9. The pixel driving circuit according to claim 1, wherein the pulse amplitude modulation module comprises:
the control end of the second switch transistor is electrically connected with the light-emitting control line, the input end of the second switch transistor is electrically connected with the second power supply end, and the output end of the second switch transistor is electrically connected with the input end of the first drive transistor; and
the control end of the third switching transistor is electrically connected with the light-emitting control line, the input end of the third switching transistor is electrically connected with the first node, and the output end of the third switching transistor is electrically connected with the light-emitting device.
10. A display panel, comprising:
a plurality of sub-pixels, at least one of which comprises a pixel driving circuit as claimed in any one of claims 1 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311346670.4A CN117456900A (en) | 2023-10-17 | 2023-10-17 | Pixel driving circuit and display panel |
| PCT/CN2024/098008 WO2025081854A1 (en) | 2023-10-17 | 2024-06-07 | Pixel driving circuit and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311346670.4A CN117456900A (en) | 2023-10-17 | 2023-10-17 | Pixel driving circuit and display panel |
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| CN202311346670.4A Pending CN117456900A (en) | 2023-10-17 | 2023-10-17 | Pixel driving circuit and display panel |
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| WO (1) | WO2025081854A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025081854A1 (en) * | 2023-10-17 | 2025-04-24 | 武汉华星光电技术有限公司 | Pixel driving circuit and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102538488B1 (en) * | 2018-10-04 | 2023-06-01 | 삼성전자주식회사 | Display panel and driving method of the display panel |
| CN113077751B (en) * | 2020-01-03 | 2022-08-09 | 京东方科技集团股份有限公司 | Pixel driving circuit, driving method thereof and display panel |
| CN114333685B (en) * | 2020-09-25 | 2023-08-08 | 京东方科技集团股份有限公司 | Pixel driving structure and display panel |
| CN113487994B (en) * | 2021-06-16 | 2022-05-06 | 中国科学院微电子研究所 | A pixel circuit, display device and pixel compensation method |
| CN115641813B (en) * | 2022-10-11 | 2025-05-30 | 武汉华星光电技术有限公司 | Pixel driving circuit and display panel |
| TWI834473B (en) * | 2023-01-13 | 2024-03-01 | 友達光電股份有限公司 | Display panel |
| CN117456900A (en) * | 2023-10-17 | 2024-01-26 | 武汉华星光电技术有限公司 | Pixel driving circuit and display panel |
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- 2023-10-17 CN CN202311346670.4A patent/CN117456900A/en active Pending
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- 2024-06-07 WO PCT/CN2024/098008 patent/WO2025081854A1/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025081854A1 (en) * | 2023-10-17 | 2025-04-24 | 武汉华星光电技术有限公司 | Pixel driving circuit and display panel |
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