CN1174469C - Preparation method of polarization insensitive semiconductor optical amplifier - Google Patents

Abstract

A method for preparing a polarization-insensitive semiconductor optical amplifier, comprising the following steps: 1) using plasma chemical vapor deposition technology to grow a dielectric film on an indium phosphorus substrate; required mask pattern; 3) N-type InP buffer layer, InGaAsP active layer and p-type Indium-phosphide capping layer; 4) Remove the dielectric film by using an etching solution; 5) Secondary epitaxy of the p-type indium-phosphorus capping layer and zinc-doped indium gallium arsenic contact layer; 6) Photoetching out the strip structure of the device; 7) Tertiary epitaxy Indium phosphorus window area; 8) photolithography to etch out the strip structure of the device; 9) growing a silicon dioxide insulating layer by chemical vapor deposition, 10) opening a silicon dioxide window; 11) as an electrode; 12) cleavage, in the device Both ends are coated with dielectric optical film.

Description

Preparation method of polarization insensitive semiconductor optical amplifier

technical field

The invention belongs to the technical field of semiconductors, and relates to the integration of polarization-insensitive semiconductor optoelectronic devices (including semiconductor optical amplifiers and electro-absorption modulators) and an active mode spot-size converter (spot-size-converter, SSC), in particular to polarization-insensitive A method for preparing a sensitive semiconductor optical amplifier used as an optical switch.

Background technique

With the continuous development of optical fiber transmission bandwidth (it is now proved that its theoretical limit is (1260-1620) nm) and people's urgent demand for broadband networks, optical networks with optoelectronics as information carriers are gradually emerging and developing. The requirements for optoelectronic devices for receiving, amplifying and modulating light are also gradually strengthened. Polarization is one of the important intrinsic properties of optoelectronics. However, because the material gain in optoelectronic devices is related to current, and the asymmetric waveguide structure is independent of current, it is a big problem to realize polarization-controllable optoelectronic devices. Especially for passive optoelectronic devices, such as semiconductor optical amplifiers (SOAs), detectors, and modulators, polarization insensitivity is one of the main performance indicators. When these devices are used in systems such as DWDM (Dense Wavelength Division Multiplexing) and OADM (Optical Add-Add-Add-Add-Downmultiplexing), it is even more required that they be able to obtain polarization insensitivity in a large wavelength range. Approaches to design polarization-insensitive SOAs to date include:

1) Thick active region structure: this kind of structure adopts thick body material active region and short cavity length to achieve polarization insensitivity very effectively, but due to its large active region volume, the operating current is large and the heat dissipation is too large , the working reliability of the device is poor, and the energy consumption is also large. It cannot be an ideal component in an all-optical network.

2) Series-parallel connection of several devices: This method uses component assembly to achieve polarization insensitivity, but in the process of series-parallel connection of several devices, self-alignment between them is relatively difficult, and there is no improvement in the structure of the device itself.

3) Strained quantum well active layer: Since the strained quantum well has a small step morphological density, it can obtain low transparent carrier density, high differential quantum efficiency, low noise factor and high saturation output. In particular, the introduction of compressively strained materials can improve the performance of semiconductor lasers. But the compressive strain leads to the increase of TE mode gain (TE mode refers to the polarized light whose electric vector is parallel to the junction plane). In order to increase the TM mode gain (TM mode refers to the polarized light whose magnetic vector is parallel to the junction plane), it is necessary to try to realize the recombination transition between electrons and light holes. For this reason, the tensile strain quantum well is an effective method. However, gain materials near 1.5 μm are difficult to achieve using tensile strain. For this reason, to obtain polarization-insensitive optical amplifiers, quantum well active layers of the following materials and structures are usually used: (1) cross-mixed quantum well materials of compressive strain and tensile strain; (2) quantum well materials of low tensile strain; (3) The structure of quantum well material lattice-matched with indium phosphorus (InP) with tensile strain barrier; (4) Strain compensation between uncoupled well and barrier; (5) Coupled quantum well and interdiffusion quantum trap. Although these methods can obtain excellent polarization insensitivity at a certain point through optimized design, due to the large difference in the effective mass of light and heavy holes parallel to and perpendicular to the growth direction, their response to the injected current is different, and the quantum The polarization properties of the well change continuously with the external injection current, but the polarization of the waveguide geometry has nothing to do with the injection current. The inconsistency between the material gain and the optical field confinement factor makes it difficult to obtain the mode gain in a wide range of polarization. sensitive. Therefore, it is difficult to obtain polarization insensitivity in the large operating current range through the quantum well structure. In addition, for the fifth method using quantum wells, both theoretical design and material growth are more difficult.

4) Realize polarization insensitivity by structural compensation: This method is to use the strain-free body material as the active region to integrate the SOA with the passive spot conversion structure (SSC), and compensate the polarization amplification in the SOA through the intrinsic polarization absorption of the SSC . The device made by this method has high polarization insensitivity, and at the same time overcomes the weakness of narrow strip width required to achieve polarization insensitivity, which increases the tolerance of the strip width. The traditional photolithography process can be used, and the SSC can improve the far-field characteristics of the spot. The coupling efficiency is improved and the performance is reliable. However, butt-joint (docking) is used in the production to realize the integration of SOA and SSC. It is very difficult to completely connect the core layer of SOA and SSC waveguide, and it is difficult to guarantee the crystal quality of the docking part. At the same time, the process is complicated and five epitaxy is required. In addition, even if the quality of the device is quite high, since the polarization of the SOA changes dynamically, and because the SSC is a passive device, it can only statically compensate the polarization in a small range, so it is difficult for the device to obtain a wide range of polarization. Polarization insensitive. Thus limiting its application in all-optical networks.

5) Vertical cavity surface-emitting structure: Since the light-emitting end face of the surface-emitting structure is circular, there is no polarization sensitivity of the waveguide itself, so it is easier to use strain compensation quantum wells or bulk materials to obtain polarization insensitivity in a wide range. At the same time, because it can obtain a circular far-field spot, the coupling efficiency is high. However, since the vertical cavity surface emission is a microcavity structure, the gain will be very small for the preparation of the traveling wave amplifier. In addition, the preparation of the vertical cavity surface emission structure requires a bottom distributed Bragg reflector (DBR) to increase the transmission of the pump light. High reflection of input light, for optoelectronic devices used in optical fiber communication, the input light wavelength is 1.3-1.4, 1.5-1.6 μm, and the materials used to prepare devices in this band are basically indium phosphide (InP)-based series, The refractive index difference of InP-based series materials is relatively small, and as a result, it is difficult to meet the requirements for the reflectivity of DBR mirrors prepared with them. At present, there are GaAs (gallium arsenic) substrates and GaAs/AlGaAs (aluminum gallium arsenic) as devices. The DBR reflector, and then the InGaAsP/InP (InGaAsP/InP) active region is bonded (bonded) to the DBR reflector, so as to achieve high reflection of light in this range. However, the bonding technology of InP series materials and GaAs-based materials is not yet mature. Therefore, the technical difficulty of preparing such devices is relatively large.

6) Nearly tetragonal material active region structure: This is a commonly used method for preparing optical switching semiconductor optical amplifiers (SOAs) that has emerged in recent years. Because the SOA grown by this method can use the strain-free body material as the active region, and the waveguide adopts a nearly square structure, so that the material gain and the waveguide structure can achieve polarization insensitivity without affecting each other, so the device can be used in large Polarization insensitivity is obtained in a large current range and a large wavelength range. Moreover, the bulk material has a large density of states and a large effective mass, so it can maintain a linear gain in a large injection current range and obtain a short response time. These Both are advantages for SOA used as an optical switch. However, NEC currently uses narrow strip width selective growth SOA. Because the strip width of the dielectric film is very narrow (0.75 μm), electron beam exposure (e-beam) must be used, which is expensive, and pure SOA has a very narrow strip width. , it is difficult to align with the fiber coupling, and its light output power is small. Usually, both ends of the narrow-strip width SOA are integrated with the mode spot converter, and a one-time SOA and SSC integrated structure is adopted. In order to reduce the absorption of the SSC region, a large wavelength shift must be obtained. According to the characteristics of narrow-strip width selective growth, the band The large tensile strain makes the crystal quality of the SSC region of the bulk material worse, and in order to obtain a large wavelength shift, it is necessary to use the normal pressure MOVPE growth method, which brings higher requirements for the MOVPE growth method. In addition, in order to obtain a one-time integrated SOA+SSC device, the outer wedge-shaped photolithography plate of the pure SSC region has particularly stringent requirements for plate making. All of these increase the difficulty and device cost of one-time integration of SOA+SSC.

Contents of the invention

The purpose of the present invention is to provide a preparation method of polarization-insensitive semiconductor optical amplifier, the key of which is to provide a new mask pattern of SOA+SSC, so that the lithography layout of SOA+SSC is easy to make and can achieve higher The accuracy; the SSC part adopts an active structure, which not only obtains a large optical output, but also improves its far-field characteristics, and adopts a low-voltage narrow strip width selective growth method to obtain an SOA+SSC integrated device. The process is simple and the performance excellent.

A kind of preparation method of polarization insensitive semiconductor optical amplifier of the present invention is characterized in that, comprises the following steps:

1) Using plasma chemical vapor deposition technology to grow a dielectric film on an indium phosphorus substrate;

2) Use ordinary photolithography and etching technology to carve out the mask pattern required by the semiconductor optical amplifier; the dielectric film mask pattern is wedge-shaped, and its length can be changed according to actual needs. In order to overcome the physical limit of optical exposure and obtain a suitable wedge The height of the shape must be both inner wedge and outer wedge; the width of the middle strip is 1 micron, and the figure without the jagged edge of the dielectric film is obtained by using the ordinary photolithography etching method, and the gluing, exposure, and development are strictly controlled to obtain a clear mask. film pattern, and then use a buffered oxide etchant at room temperature to etch out a dielectric mask pattern without jagged edges;

3) Using narrow strip width selective growth metal organic chemical vapor deposition technology, sequentially grow n-type indium phosphorus buffer layer, indium gallium arsenic phosphorus active layer and p-type indium phosphorus capping layer on the indium phosphorus substrate after photolithography;

4) Use corrosive liquid to remove the dielectric film;

5) Secondary epitaxial p-type indium phosphorus capping layer and zinc-doped indium gallium arsenic contact layer;

6) Photoetching out the strip structure of the device;

7) Triple epitaxial indium phosphorus window region;

8) Erosion device strip structure by photolithography;

9) growing a silicon dioxide insulating layer by chemical vapor deposition;

10) Open the silica window;

11) as an electrode;

12) Cleavage, coating a dielectric optical film on the two end faces of the device.

The dielectric film grown in step 1 may be silicon dioxide, silicon nitride or silicon oxynitride, and no matter what kind of dielectric film, its growth thickness shall not exceed 150 nanometers.

In step 3, a large rate enhancement factor is obtained when growing the n-type indium-phosphide buffer layer by metal-organic chemical vapor deposition with narrow strip width selective growth, so as to form a steep thickness wedge shape, and when growing the indium-gallium-arsenide-phosphide active layer A small rate enhancement factor is used to reduce the large strain difference in the wedge-shaped growth region, and to ensure that the non-wedge-shaped InGaAsP active region is a strain-free region, and its growth height is consistent with the growth strip width, forming a nearly square The strip-shaped active region; and the wedge-shaped region is a tensile strain region, so as to ensure that the overall active region can obtain polarization-insensitive gain.

The corrosion solution used in its step 4 is exactly the same as the corrosion solution used in the step 2.

In step 5, it may be a p-type indium phosphorus structure, or ion implantation may be performed on both sides of the current blocking layer in these active regions to reduce leakage current.

The area etched by photolithography in step 6 is the area used to grow the indium phosphorus window.

The indium phosphorus window region grown in step 7 is an undoped indium phosphorus layer.

The insulating layer in step 9 may be silicon dioxide, silicon nitride or silicon oxynitride.

In the step 11, the electrode preparation adopts the direct stripping technique with glue, or the technique of etching the electrode pattern.

In its step 12, the optical dielectric film is coated with an anti-reflection film according to actual needs, and its reflectivity must be below 0.01%.

This preparation method is not only suitable for the preparation of polarization-insensitive semiconductor optical amplifiers, but also suitable for the preparation of the integration of SOA and electroabsorption modulator, including the integration of (SOA+SSC+EA).

Description of drawings

In order to further illustrate the technical content of the present invention, the present invention is described in detail below in conjunction with embodiment and accompanying drawing, wherein:

Figure 1 is the first photolithography layout for preparing this type of device;

Figure 2 is a top view of integration after one epitaxy;

Fig. 3 is a sectional view after a strip epitaxy;

Fig. 4 is a top view of the integrated device before secondary epitaxy;

5 is a cross-sectional view of an integrated device before secondary epitaxy;

Fig. 6 is a schematic diagram of SOA+ all active SSC integrated devices;

Fig. 7 is a schematic diagram of another SOA+ all active SSC integrated devices;

Fig. 8 is a schematic diagram of SOA+passive SSC+EA integrated device.

Detailed ways

Embodiment 1: Polarization-insensitive SOA+integration of all active SSCs

The polarization insensitive semiconductor optical amplifier prepared by the present invention is integrated with active SSC, and its preparation steps include as follows:

1) growing a _SiO2 dielectric film with a thickness of 100-150 nanometers (nm) on the n-type indium phosphorus substrate by using plasma chemical vapor deposition technology;

2) Prepare a photoresist plate by using ordinary ultraviolet exposure technology;

3) using the photolithography plate prepared in step 2 to photolithography and etch the substrate of step 1 to obtain the corresponding SiO ₂ The dielectric film pattern of the mask, as shown in Figure 1;

4) Using the low-pressure MOVPE narrow-strip growth technology, sequentially grow an n-type indium phosphide (InP) buffer layer, an undoped indium gallium arsenide phosphide (InGaAsP) active layer, and a p-type InP capping layer on the substrate obtained in step 3 ( As shown in Figure 2 and Figure 3);

5) using the etching solution used in step 3 to etch away the SiO ₂ on the sample (as shown in Figure 5);

6) The p-type InP cap layer and the heavily zinc-doped indium gallium arsenide (InGaAs) contact layer are grown by planar secondary epitaxy;

7) Photolithographic etching to form device stripes;

8) Using thermal oxidation chemical deposition technology to grow SiO ₂ insulating layer;

9) open SiO ₂ window;

10) Make electrode patterns by using adhesive stripping technology;

11) Coating the same anti-reflection coating on both ends of the device, the reflectivity of the cavity surface is less than 0.001% (as shown in Figure 6).

The dielectric film in step 1 can be SiO ₂ , or silicon oxynitride (SiON) or silicon nitride (SiN); the length of the wedge-shaped region and the inner wedge-shaped and outer wedge-shaped regions in the plate-making pattern in step 2 The width can be designed according to the actual needs and the accuracy of the plate making and the accuracy of photolithography. The photolithographic etching in step 3 must comply with the 1 μm process, so that the edges of the etched dielectric film pattern are smooth and burr-free. In step 3, in the process of using the low-voltage narrow-strip-width selective growth MOVPE technology, a large rate enhancement factor is used when growing n-InP, and a small rate enhancement factor is used when growing InGaAsP.

Example 2: Polarization-insensitive SOA+partially active SSC integration

The preparation method of this kind of device is basically the same as that of Embodiment 1, except that the wavelength drift needs to be further increased when the InGaAsP quaternary layer is grown in a narrow strip width to reduce the absorption of the passive SSC part; in addition, the electrode pattern is changed to make the SSC Partially covered with electrodes.

Embodiment 3: Polarization-insensitive SOA+active SSC+passive SSC+EA integration:

Since the integration of the electroabsorption modulator is involved here, the preparation steps are slightly different from the previous two examples, and the specific steps are as follows:

1. Using the photolithography plate in Figure 1, etch the n-InP substrate to form a dielectric film mask pattern with smooth and flat edges;

2. Perform a narrow strip width epitaxy on the chip etched by photolithography in step 1, including n-InP buffer layer, undoped InGaAsP active and passive waveguide layer and part of p-InP capping layer;

3. Etch the mask medium with corrosive solution; then rinse with deionized water, then etch out the fresh surface of the semiconductor with concentrated sulfuric acid, and rinse with a large amount of deionized water;

4. Planar secondary epitaxy, including p-InP buried layer and InGaAs contact layer;

5. Etch to remove the InGaAs contact layer between the SOA region and the EA, and use selective He ⁺ ion implantation to form an electrical isolation trench;

6. Evaporate the insulating dielectric film and carve the electrode window;

7. Use the lift-off technology to make the P surface electrode pattern of SOA and EA area;

8. Thinning, making N-side electrode;

9. Finally, an optical film is coated on the end face of the device.

Fig. 1 shows the first photolithography layout for preparing this type of device, which is the common photolithography version of these devices and also the main core of the present invention. In order to prepare polarization-insensitive SOA using strain-free bulk materials, the strip width of SOA should not exceed 1 μm. We use narrow strip width selective growth technology to automatically grow and form the strip width in the active region without using chemical etching. Therefore, The strip width of the selected growth area is selected as 1 μm. In order to obtain a specific rate enhancement factor, the width of the mask on both sides is 20 μm. According to the law of selective growth of narrow strip width, the growth rate of the material is continuously decreasing with the decrease of the mask width. Therefore, through the change of the strip width of the mask, a certain gradient is formed in the growth area in the longitudinal direction, forming a thickness-type taper. However, due to the limit of ultraviolet exposure, when the strip width is on the order of 1 μm, the mask width is reduced until it becomes zero. Due to diffraction effects, the bar width will be very inaccurate. In order to avoid the physical limit of this kind of exposure and at the same time ensure the required rate enhancement factor, we adopt the inner wedge type and the outer wedge type at the same time, so that the stripe width of the growth area is continuously increasing while the mask stripe width is reduced, so that The mask stripe width does not have to be reduced to zero to achieve a desired rate enhancement factor. The window area of the device is masked with SiO ₂ as a whole in this plate, which avoids the step of opening the InP window after an epitaxy, and also avoids the photolithographic corrosion of the active area, which is conducive to the improvement of device performance. To improve, each tube core is arranged in an S shape in the layout, which is convenient for forming an oblique window structure by photoetching InP after epitaxy, and is conducive to reducing the reflectivity of the cavity surface.

Figure 2 and Figure 3 show the side view and cross-sectional view after one epitaxy. In one epitaxy, the n-InP layer 4 is grown first, and its thickness is determined according to the required InGaAsP active layer 3 to ensure that the InGaAsP active layer 3 The width is narrow enough; after that, the nearly square InGaAsP active layer 3 is grown. During the growth, it is necessary to ensure that the strain in the SSC region is not too large, so as to ensure the crystal quality of the SSC region, and at the same time ensure that the SOA active region is a strain-free material. Afterwards, a p-InP capping layer 2 is grown to form a pn junction. Here, the SOA active region is 400 μm, and the SSC part is determined according to the active region growth wavelength shift and the taper shape mode spot conversion. In short, the length of the SSC region should ensure that the mode spot conversion is appropriate and there is a small far-field divergence angle. The pattern of the SiO ₂ mask 4 at both ends is designed according to the device to be generated. Among them, the oblique part is the InP window area, which is used to grow the p-InP window during the second epitaxy. In this way, the photolithography corrosion of the InP window area after the first epitaxy is avoided, the process steps are reduced, and the material in the active area is also reduced. damage and contamination, which is beneficial to ensure the performance of the device.

4 and 5 are schematic diagrams of etching away the dielectric film with an etchant after one epitaxy. Among them, 1, 2, and 3 refer to the same as those in Fig. 2 and Fig. 3 .

Figure 6 is an overall schematic diagram of the device. In the figure, 1 is the p-InP layer, which is used to form the buried pn junction and waveguide structure of the BH structure; 2 is the Au/Ge/Ni alloy layer, which is used to form the n-face electrode; 3 is the Zn heavily doped InGaAs contact layer, Used to form the ohmic contact of the device, reducing series resistance and unnecessary loss; 4 is the SiO2 insulating layer, used to reduce leakage current; 5 is the Au/Zn/Au alloy layer, used to form the p-side electrode, 6 is the InP window region; it can be non-doped InP or p-Inp, which is used to increase light scattering and reduce cavity surface reflectivity; 7 is n-InP substrate; 8 is wedge-shaped tensile strain active region, its main function is It is used to improve the shape of the mold spot. At the same time, the active structure is used to avoid the strong absorption caused by this part; 9 is the near-square active area of the bulk material, which is used for the amplifier to generate polarization-insensitive optical gain; 10 is n-InP The buffer layer, on the one hand, is used to form a pn junction, and on the other hand, it is used to form the narrow strip width required by the active region according to the characteristics of the narrow strip width selective growth according to the (111) B plane growth; 11 is the anti-reflection coating layer on the cavity surface, It is used to reduce the reflectivity of the cavity surface to form an effective traveling wave amplifier. Bulk material SOA active area is the main area that provides SOA amplification. It needs to form a nearly square waveguide structure. At the same time, it is a strain-free bulk material, so as to ensure polarization insensitivity in large current and large wavelength range. At the same time, Good linearity and fast response to signals. On the one hand, the active area of the SSC provides further signal amplification, and at the same time, its taper-type waveguide structure can realize mode spot conversion and improve its far-field characteristics, so as to ensure a high coupling efficiency of the output light. Due to the characteristic of narrow strip width selective growth, the SSC part must be under tensile strain, and as the thickness of the bulk material grows thinner, the tensile strain of the SSC region becomes larger. Therefore, although the SSC region is no longer a nearly square waveguide structure, it is still Polarization insensitivity can be obtained. At the same time, since the SSC region has a certain wavelength shift relative to the SOA region, such an active region structure can obtain polarization insensitivity in a larger range. The angled p-InP window layer is beneficial to reduce the reflectance of the cavity surface. Moreover, such an off-angle structure can be obtained only by etching InP after the second epitaxy, and does not need to grow narrow strips and wide off-angles, and can achieve the same result by different routes. But it is much easier to grow. 11 is an anti-reflection coating on the cavity surface, which is used to further reduce the reflectivity. Through the above measures, the reflectance of the cavity surface is lower than 10 ^-4 .

Figure 7 is a modification of Figure 6. When the wavelength shift of the active area is too long, it is necessary to use part of the SSC as the active area and part as a passive waveguide, as long as the electrode length is changed.

FIG. 8 is also a modification of FIG. 6 and is a schematic diagram of SOA+SSC+EA. Among them, 1, 2, 3, 4, have the same function as those mentioned above, and 5 refers to the p-surface electrode of the EA electroabsorption modulator. Since the modulator needs to consider the modulation rate, the electrode must be made into a specific pattern. It can form an effective current channel and reduce parasitic capacitance at the same time; 6 is the p-surface electrode in the SOA area. Since it works statically, it is not affected by capacitance and can be made into a large-area electrode pattern; 7 is p-InP The cover layer, on the one hand, is used to form the pn junction and active waveguide structure, and also forms the buried layer of the BH structure; 8 is the anti-reflection coating on the cavity surface, which is used to reduce the emissivity of the cavity surface, and helps to form a traveling wave amplifier; 9 10 is the n-InP substrate; 11 is the wedge-shaped EA electroabsorption modulator part; 12 is the passive wedge-shaped part. The amplified light transmission and modulation of the source region will also improve the spot quality of the output light, making it more suitable for coupling with optical fibers and reducing coupling loss; 13 is the part of the SOA active region of a nearly tetragonal material, which is used to generate polarization insensitive Optical gain; 14 is the n-InP buffer layer, which is used to form pn junctions and waveguide structures on the one hand, and more importantly, to form the narrow strip width required by the active region according to the characteristics of narrow strip width selective growth and (111) B plane growth 15 is a helium ion implantation area, located between the SOA and the EA, used to strengthen the isolation between the two, and reduce the influence of the parasitic capacitance of the SOA active area on the high-speed modulation of the EA. Since the EA region is acted by a wedge-shaped part, it has a certain wavelength range, so the wavelength range that can be modulated is large, which is consistent with the large wavelength range that can be amplified by the previous SOA. At the same time, the tensile strained bulk material and the flat waveguide structure are also EA can be made polarization insensitive. In a word, the cooperative operation of SOA and EA can obtain excellent performances such as polarization-insensitive amplification and modulation, large extinction ratio and large output power in a large wavelength range. Moreover, SOA and EA, which are both bulk materials, have a short response time to signals, reducing dynamic dispersion and crosstalk. At the same time, the SSC-type waveguide structure can reduce the far-field divergence angle, improve the far-field characteristics of the device, increase the coupling efficiency and coupling tolerance with the fiber, and thus obtain a large fiber-to-fiber gain and increase the optical power. The SSC region in the middle part of EA and SOA digs out the InGaAs contact layer to form an isolation trench, and then implants He ions in this region to increase the electrical isolation between the SOA and EA regions, reduce the parasitic capacitance of the EA region, and obtain high stability at the same time.

The advantages of the present invention are:

1. Both the inner wedge type and the outer wedge type are used to overcome the inaccuracy caused by the physical limit of exposure during the plate making process, and at the same time, it can meet the requirements of obtaining a large thickness enhancement factor during the growth process.

2. When growing n-InP during the growth process, a large rate enhancement factor is used to obtain a large thickness enhancement factor, while when growing the InGaAsP active region, a small rate enhancement factor is used to reduce wavelength drift and strain changes, thereby A one-time integrated structure of the mode speckle converter and the SOA is obtained, supplemented by a refractive index taper and dominated by a thickness taper.

3. InGaAsP in the non-taper region grows into a strain-free near-tetragonal structure, and the taper region grows into a tensile strain region, which ensures that the entire waveguide structure is insensitive to polarization.

4. The taper waveguide area adopts a fully active or partially active structure, which reduces the strong absorption of light in this area. At the same time, it is not necessary to use atmospheric pressure selective growth MOVPE technology in order to obtain a large wavelength shift, and there is no need to worry about the large wavelength shift. Drift introduces large strains resulting in poor crystal quality. At the same time, this taper structure can also improve the far-field characteristics of the spot, increase the coupling efficiency, and increase the output power of the SOA.

5. The bulk material active region dominated by strain-free nearly tetragonal materials can make SOA obtain polarization insensitivity in a large current injection range and a large wavelength range, and compared with the quantum well active region, the carrier The injection relaxation time is short, the response is fast, and the density of states is large, and the linearity of the device is high.

6. Adopt narrow strip width selective growth technology to automatically form nearly square mesas without etching the active waveguide, reducing defects in the active area, thereby reducing non-radiative convergence, which is conducive to reducing the transparent current and work of the device current, which is also beneficial to reduce the noise factor.

7. Use the SiO ₂ dielectric mask to obtain the oblique window area, which avoids the photolithographic corrosion of the active waveguide after one epitaxy, reduces the process steps, and also reduces the corrosion damage to the active waveguide, which helps to ensure the device performance. In the window area, the oblique angle structure is obtained by etching. On the one hand, it avoids the difficulty of oblique angle growth caused by the sensitivity of the crystal orientation effect in the selective growth of narrow strip width. The angled InP window, and the oblique InP window can very effectively reduce the reflectivity of the cavity surface, thereby reducing the difficulty of coating the cavity surface and obtaining an SOA with excellent performance.

8. SOA+SSC adopts a one-time integration structure, which avoids the difficulty of docking and the defects caused by it. The process steps are simple, and both plate making and photolithography all adopt ultraviolet exposure technology, which reduces technical difficulty and device cost. A polarization-insensitive SOA with excellent performance is obtained.

9. For this structure, if part of the SSC area is made into a reverse electrode, the other part is still a forward electrode, and an isolation trench is carved between SOA and EA, and then He is selectively implanted, and the EA electrode is made into a pattern Electrodes, strengthen electrical isolation, reduce parasitic capacitance, then the structure becomes a SOA+EA structure, and the SOA+EA integrated device prepared by this structure can obtain polarization-insensitive amplification and modulation in a large wavelength range, Excellent properties such as large extinction ratio and large output power. Moreover, SOA and EA, which are both bulk materials, have a short response time to signals, reducing dynamic dispersion and crosstalk. At the same time, the SSC-type waveguide structure can reduce the far-field divergence angle, improve the far-field characteristics of the device, increase the coupling efficiency and coupling tolerance with the fiber, and thus obtain a large fiber-to-fiber gain and increase the optical power.

Claims (10)

1, a kind of preparation method of polarization insensitive semiconductor optical amplifier, is characterized in that, comprises the steps: 1) Using plasma chemical vapor deposition technology to grow a dielectric film on an indium phosphorus substrate; 2) Use ordinary photolithography and etching technology to carve out the mask pattern required by the semiconductor optical amplifier; the dielectric film mask pattern is wedge-shaped, and its length can be changed according to actual needs. In order to overcome the physical limit of optical exposure and obtain a suitable wedge The height of the shape must be both inner wedge and outer wedge; the width of the middle strip is 1 micron, and the figure without the jagged edge of the dielectric film is obtained by using the ordinary photolithography etching method, and the gluing, exposure, and development are strictly controlled to obtain a clear mask. film pattern, and then use a buffered oxide etchant at room temperature to etch out a dielectric mask pattern without jagged edges; 3) Using narrow strip width selective growth metal organic chemical vapor deposition technology, sequentially grow n-type indium phosphorus buffer layer, indium gallium arsenic phosphorus active layer and p-type indium phosphorus capping layer on the indium phosphorus substrate after photolithography; 4) Use corrosive liquid to remove the dielectric film; 5) Secondary epitaxial p-type indium phosphorus capping layer and zinc-doped indium gallium arsenic contact layer; 6) Photoetching out the strip structure of the device; 7) Triple epitaxial indium phosphorus window region; 8) Erosion device strip structure by photolithography; 9) growing a silicon dioxide insulating layer by chemical vapor deposition; 10) Open the silica window; 11) as an electrode; 12) Cleavage, coating a dielectric optical film on the two end faces of the device. 2. The method for preparing a polarization-insensitive semiconductor optical amplifier according to claim 1, wherein the dielectric film grown in step 1 can be silicon dioxide, silicon nitride or silicon oxynitride, no matter which Dielectric films whose growth thickness does not exceed 150 nanometers. 3. The method for preparing a polarization-insensitive semiconductor optical amplifier according to claim 1, characterized in that, in step 3, a large The rate enhancement factor is used to form a steep thickness wedge. When growing the InGaAsP active layer, a small rate enhancement factor is used to reduce the large strain difference in the wedge-shaped growth area and ensure that the non-wedge area InGaAs The arsenic-phosphorus active region is a strain-free region, and its growth height is consistent with the growth strip width, forming a nearly square strip-shaped active region; while the wedge-shaped region is a tensile strain region, thereby ensuring that the overall active region can obtain polarization Insensitive buff. 4. The method for preparing a polarization-insensitive semiconductor optical amplifier according to claim 1, characterized in that the etching solution used in step 4 is exactly the same as the etching solution used in step 2. 5. The method for preparing a polarization-insensitive semiconductor optical amplifier according to claim 1, characterized in that, in step 5, it may be a p-type indium phosphorus structure, or ionization may be carried out on both sides of the current blocking layers in these active regions. injected to reduce leakage current. 6. The method for preparing a polarization-insensitive semiconductor optical amplifier according to claim 1, characterized in that the area etched by photolithography in step 6 is the area used to grow the indium phosphorus window. 7. The method for preparing a polarization-insensitive semiconductor optical amplifier according to claim 1, wherein the indium phosphorus window region in step 7 is an undoped indium phosphorus layer. 8. The method for preparing a polarization-insensitive semiconductor optical amplifier according to claim 1, characterized in that in step 9, the insulating layer can be silicon dioxide, silicon nitride or silicon oxynitride. 9. The method for preparing the polarization-insensitive semiconductor optical amplifier according to claim 1, characterized in that, the electrode preparation in step 11 can adopt the direct stripping technology with glue or the technology of etching electrode patterns. 10. The method for preparing a polarization-insensitive semiconductor optical amplifier according to claim 1, characterized in that in step 12, an optical dielectric film is coated according to actual needs and an anti-reflection film is applied, and the reflectivity must be below 0.01%.

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