CN117406956A - Light quantum number parity check random number chip - Google Patents

Abstract

The light quantum parity check random number chip comprises a light source module, a detector module, a data post-processing module and a chip clock and control module; the detector module converts the photon number generated by the light source module in the integration time into the level through the reading circuit, generates photo-generated current, and outputs the photo-generated current to the random number chip pixel array; the random number chip converts the photo-generated current into a voltage value through sampling capacitance integration; self-checking the voltage signal through a comparator; the random number chip converts the voltage signal into a corresponding digital signal conforming to poisson distribution; the digital signal is connected to the parity check module and carries out parity value judgment, and the random digital chip digital integrated circuit corresponds to the true digital random number output obeying 0-1 uniform distribution in a parity check mode. Realize high-quality true random number generation system chip, miniaturization, strong anti-interference ability, low static power consumption and high random number output rate.

Description

Light quantum number parity check random number chip

Technical Field

The invention relates to an IPC classification G06F7/58 random number or pseudo-random number generator technology, belongs to the random number generation technology in the field of cryptography, and particularly relates to a chip system for generating light quantum numbers based on an integrated circuit, a silicon-based detector and a semiconductor light source and a method for realizing true random numbers by utilizing parity characteristics.

Background

Random numbers are widely used in the field of cryptography, where encryption algorithms require keys. Random Number Generators (RNGs), also known as Random Bit Generators (RBGs), are required in the key generation process to create random or strong keys and for other encryption purposes, such as initializing vectors and random numbers. Many physical properties can be used to generate random numbers in nature, and the essential characteristics are that a certain physical quantity is applied to a certain continuous or discrete distribution, and the signal value which can be detected is a random variable applied to the distribution.

Entropy Source (Entropy Source): i.e. the source of unpredictable data streams, quantum random number generation systems first require an entropy source with uncertainty.

Existing random number generation systems, such as semiconductor integrated circuit and device based systems, include flash memory devices and memristors, and characteristic detectors based on photons; in the generation of quantum random numbers, many methods claim that they can generate true random numbers, despite further detection. In addition, no matter what physical mode is adopted as a random source, the signal generated by the random source needs to be post-processed so as to generate a random number. The post-processing system of the random signal plays an important role in the whole random number generation system. In light quantum random sources, there are various photon characteristics that can be used as sources of random sources, such as a certain distribution obeyed by using the time of arrival of photons at a detector, polarization characteristics of light, and phase characteristics of light, these methods mostly use lasers as entropy sources, and the characteristics of extracted light require additional optical modules that add additional cost to the random number generation system.

Chinese patent application CN 102637122B is a method and system for generating true random numbers based on parity of physical noise. The method for generating the true random number according to the parity of noise after analog-to-digital conversion comprises the following steps: 1) Generating an analog noise signal by a physical noise source; 2) Analog/digital conversion is carried out on an analog noise signal generated by the acquired physical noise source, and the analog noise signal is converted into a digital noise signal; 3) Generating a binary random number according to the parity of the converted digital noise signal; 4) Repeating the steps 2) and 3) to obtain a sequence containing a plurality of random numbers. The purpose is to utilize various noise sources, but the quality, anti-jamming capability and stability of the random number generation are difficult to ensure free from environmental influences. But wherein the most critical physical implementation method involved for entropy sources or noise sources in the random number chip is not involved and the corresponding true random number chipping implementation is not presented.

Chinese patent application 20081017762. X discloses a method for generating true random numbers, which processes a binary random number sequence output from a binary true random number sequence generating device as follows: a) Obtaining a segment of the binary random number sequence, wherein the first bit and the last bit are one of 0 or 1, and the rest bits are the other of 0 or 1; b) Outputting a binary random number 0 or 1 according to the number of bits of the segment; c) Repeating steps a) and b) until a sufficient number of random numbers are obtained. It is required to use an arbitrary true random number generator to ensure that the quality of the generated random numbers is not affected by the environment.

In existing random number generation methods, such as using quantum phase fluctuation (Quantum phase fluctuation), homodyne detection, and vacuum shot noise (Vacuum shot noise), memristors, and various circuit mechanisms, true random numbers are generated. For the disclosed true random number generating device which takes a light source as an entropy source, most of the disclosed true random number generating device needs an additional module for extracting light information, so that the complexity and the cost of a system are increased; in particular, the technical proposal of the high-quality light quantum true random number generation system which has the advantages of chip formation, miniaturization, convenient integration, strong anti-interference capability, low static power consumption and high random number output rate is still less disclosed.

Disclosure of Invention

Aiming at the problems and the technical requirements, the invention provides a method and a chip for generating an odd-even characteristic light quantum true random number based on verification post-processing, so as to realize the research purposes and functions of high-quality true random number generation system, such as chippingization, miniaturization, strong anti-interference capability, low static power consumption and high random number output rate.

The random number chip comprises a light source module, a detector module, a data post-processing module and a chip clock and control module; the detector module converts the photon number generated by the light source module in the integration time into the level through the reading circuit, generates photo-generated current, and outputs the photo-generated current to the random number chip pixel array; the random number chip samples row pixels of the pixel array through a row decoder; the random number chip converts the photo-generated current into a voltage value through sampling capacitance integration; the random number chip leads out the voltage signal of the selected pixel through the column decoder; self-checking the voltage signal through a comparator; the random number chip converts the voltage signal into a corresponding digital signal conforming to poisson distribution; the digital signal is connected to the parity check module and carries out parity value judgment, and the random number chip digital integrated circuit corresponds to the output of digital random numbers which are uniformly distributed and obey 0-1 in a parity check mode, and the digital random numbers are true random numbers.

In particular, the detector module uses a CMOS photodetector, and the detector module further comprises a CIS pixel array and a readout circuit; the CIS pixel array is a detector micro-component formed by arranging silicon-based PN junctions in an array manner to form a pixel array; the read-out circuit includes: a row decoder, a column decoder, a sample and hold circuit, a signal amplifying module AMP and an analog-to-digital conversion module ADC; the chip clock and control module comprises an IC control module, a time sequence module, an interface module and an LED control module. The light source module is a semiconductor light source and adopts an LED or an LD. After a chip clock and control module of the random number chip, namely a time sequence and control unit, is connected with a peripheral control signal of the random number chip, the clock and control module of the random number chip sends out LED luminous driving and control signals, and a control circuit is used for controlling the light source module, namely the switch of the semiconductor light source; meanwhile, a chip clock and control module of the random number chip sends out a CIS reading control signal and accesses a detector module, namely a CIS pixel and a reading circuit, and then the detector module is connected with a data post-processing module and then is connected with and drives a reading voltage reference comparison module and a parity check module in sequence; the analog-to-digital conversion module ADC of the reading circuit in the detector module inputs the digital signal with the width of N bits to the parity check module by the reading voltage reference comparison module after the data is input into the data post-processing module, and finally, the parity check module outputs a serial digital random sequence; the digital random number is obtained after the analog-digital conversion module ADC is subjected to digital-analog conversion and is subjected to Poisson distribution, N-bit digital signals output by the analog-digital conversion module ADC are imported into the parity check module, odd numbers in N-bit two-level system data of the digital random number are corresponding to 1, the probability of 0 and 1 is approximately 1/2, the random number is further output in series, the numerical values corresponding to the multi-bit signals are subjected to uniform distribution, and the parity check circuit is realized through the digital exclusive OR gate.

In particular, the number of photons which can be detected in a certain integration time of the CIS pixel array of the CMOS photodetector module and the readout circuit obeys the Poisson distribution, namely the signal value is a random variable X obeying the Poisson distribution; the digital signal conforming to poisson distribution is converted into a single random bit by means of parity check.

In particular, the parity check mode is realized by a digital integrated circuit, parity check is carried out on the N-bit digital signal after digital-analog conversion, when the odd number of 1 outputs are 1, and when the even number of 1 outputs are 0; alternatively, the digital random number is generated using the parity characteristic of the numerical value of the digital signal itself.

In particular, the light source module uses a semiconductor light source of a group iii-v material; the semiconductor light source of the III-V material is a III-V light emitting diode, and refers to a semiconductor Light Emitting Diode (LED) or a semiconductor Laser (LD) which emits light in a visible wave band based on materials such as gallium arsenide, gallium nitride and the like.

In particular, an analog reference voltage comparison module is additionally arranged in a detector module, namely a readout circuit of the CMOS photodetector, and the readout voltage output by the pixel is compared with a reference voltage value; the analog reference voltage comparison module comprises a primary digital comparator, a register and a secondary digital comparator which are sequentially connected; the data post-processing module is provided with a read-out voltage reference comparison module, and after the read-out circuit of the detector module is accessed to data, the read-out voltage reference comparison module is accessed first, and then the parity check module is accessed. The first-level digital comparator is used for screening and removing blind pixels, and pixel readout voltage of the first-level digital comparator is required to be larger than a reference voltage value and can be output; the secondary digital comparator is used for screening and removing overheat pixels, and the pixel readout voltage is required to be smaller than the reference voltage value to be output. One end of the primary digital comparator is connected with the minimum value of the normal signal, the other end of the primary digital comparator is connected with the read-out signal of the pixel, the output signal is a comparison result, the comparison result is connected with the enabling port of the register, the signal conforming to the minimum value range of the signal is connected with the secondary digital comparator and is compared with the maximum value of the normal signal, the comparison result is connected with the enabling port of the register, the register is connected with the signal value for comparison, and the comparison result is used as the enabling signal to control the output of the read-out signal of the pixel.

In particular, a timing module is designed and arranged in the detector module. In the CIS pixel array of the CMOS photodetector, a row decoder is responsible for selecting a middle row; the row buses of all pixels of each row of the CIS pixel array are connected together, the current readout row is selected through a row decoder in the address decoder, serial readout is carried out on the current readout row through a column decoder, and then row signals are led out through a source follower; the column signals of the pixels in all CIS pixel arrays in the same column are connected together to sample and hold the sampling and holding circuit to generate V used as an analog-to-digital conversion module ADC _REF Signal and V _SIG A signal.

In particular, the CIS pixel array is a silicon-based PN junction detector and has a 3T-pixel structure or a 4T-PPD or 5T-PPD structure with a transmission gate PPD structure (Pinned PhotoDiode).

In particular, an interface module in a chip clock and control module of the random number chip adopts an IIC protocol to control the chip, and outputs a random number sequence through an SPI communication protocol.

In particular, on a random number chip, other modules or circuits are integrated on the same silicon-based circuit wafer (die) except for a light source module using a semiconductor light source of a III-V material; the light source module of the semiconductor light source using the III-V material and other silicon-based modules are integrated in the same chip through once encapsulation, namely, the internal die of the encapsulation structure only comprises LED bare die and silicon-based circuit bare die.

In particular, the light source modules, the detector modules, the data post-processing modules and the chip clock and control module silicon-based circuits are respectively packaged by mutually separated die, and then are connected through the substrate to form a random number chip, namely, different modules are not integrated on the same die, and a plurality of die are connected together by adopting the separation module and utilizing a packaging substrate or other packaging technologies.

Particularly, a detector module, a data post-processing module, a chip clock and control module and other silicon-based circuit modules in the random number chip are packaged separately to form a chip with a transparent top cover, and the packaged transparent top cover is used for receiving a light source of the light source module to the detector module; on the basis, the chip with the transparent top cover is integrated with the light source module through a connection coupling technology to form the random number chip.

Particularly, the light source module is a semiconductor light source chip based on different process structures, and comprises a front-mounted LED with a light emitting surface and an electrode surface on the same surface of the LED chip, a flip-chip LED with the light emitting surface and the electrode on two surfaces of the LED chip, a vertical-structure LED with the electrode on two surfaces of the LED chip, a side light emitting LED with the light emitting surface positioned on the side surface of the LED chip, and semiconductor lasers LD with various structures; or, the random number chip is based on the difference of light emission and electrodes which are formed by integrating the light source module and the electronic circuit module by utilizing different light path coupling modes designed by technologies of technology, packaging and integration.

The invention has the beneficial effects that: 1) The chip integrated light source module, the detector module, the data post-processing module and the chip clock and control module are used for generating random numbers for parity check processing, and the chip integrated light source module has the advantages of miniaturization, strong anti-interference capability and low static power consumption; 2) The light source and the detector are adopted as entropy sources, so that randomness of the entropy sources is ensured compared with random numbers generated by a circuit alone; 3) Designing an analog reference voltage comparison module to realize pixel signal screening, and further ensuring high reliability of random number output; 4) The mature technologies of semiconductor light emitting diode, CMOS detector and integrated circuit are adopted, so that the excellent economical efficiency of low-cost manufacturing of chips is ensured.

Drawings

The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are schematic and should not be interpreted as limiting the invention in any way.

FIG. 1 is a schematic diagram of data flow of a method and chip for generating parity-characteristic photon true random numbers based on post-verification processing in the present invention.

Fig. 2 is a block diagram of internal modules and functional relationships of a method and a chip for generating a parity-characteristic photon true random number based on post-verification processing in embodiment 1 of the present invention.

Fig. 3 is a schematic diagram of a CIS pixel and a readout circuit in embodiment 1 of the present invention.

Fig. 4 is a schematic diagram of a pixel readout voltage comparison circuit according to embodiment 2 of the present invention.

Detailed Description

The contents of the present invention can be more easily understood by referring to the following detailed description of preferred embodiments of the present invention and examples included. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In case of conflict, the present specification, definitions, will control.

The singular forms include plural referents unless the context clearly dictates otherwise. "optional" or "any" means that the subsequently described event or event may or may not occur, and that the description includes both cases where the event occurs and cases where the event does not.

Furthermore, the indefinite articles "a" and "an" preceding an element or component of the invention are not limited to the requirements of the number of elements or components (i.e. the number of occurrences). Thus, the use of "a" or "an" should be interpreted as including one or at least one, and the singular reference of an element or component also includes the plural reference unless the amount is obvious to the singular reference.

In the description of the present invention, some column embodiments may be formed according to the technical solution of the present invention, including adding an auxiliary module in the module connection structure in the present invention, or adjusting the connection relationship of the modules, or changing the package structure of the chip, or performing limited improvement on the extraction algorithm, or superposing application or directly embedding in other chips, modules, systems, or the like.

Typically, a True Random Number Generator (TRNG) provides a random or entropy source to seed a Pseudo Random Number Generation (PRNG), also known as a Deterministic Random Bit Generator (DRBG). Whereas the generation of true random numbers depends on the relevant physical mechanism. The quantum properties of the substance prove useful as a signal source for generating true random numbers. For some application scenarios of random numbers and encryption, such as portable embedded terminal equipment, a random source needs to be chipped, so that a random number generator based on the existing semiconductor device and integrated circuit has important application in the field of information security.

In the present invention, the random number generation system is structurally divided into a random source and a random signal post-processing system.

In the invention, referring to fig. 1, a detector module converts photon numbers generated by a light source module in integration time into electric levels through a read-out circuit, generates photo-generated current, and outputs the photo-generated current to a random number chip pixel array; the random number chip samples row pixels of the pixel array through a row decoder; the random number chip converts the photo-generated current into a voltage value through sampling capacitance integration; the random number chip leads out the voltage signal of the selected pixel through the column decoder; self-checking the voltage signal through a comparator; the random number chip converts the voltage signal into a corresponding digital signal conforming to poisson distribution; the digital signal is connected to the parity check module and carries out parity value judgment, and the random number chip digital integrated circuit corresponds to the output of digital random numbers which are uniformly distributed and obey 0-1 in a parity check mode, and the digital random numbers are true random numbers. Wherein, the voltage stabilizing circuit and the integrating capacitor are integrated in the random number chip. And (3) researching the detection mechanism of the CMOS photodetector module, wherein the detection of the CMOS photodetector module needs a corresponding integration capacitor, and the voltage on the integration capacitor is formed by converting and corresponding light quanta detected by the detector in the integration time.

The parity check mode is realized by a digital integrated circuit, parity check is carried out on the N-bit digital signal after digital-to-analog conversion, when the odd number 1 is output as 1, and when the even number 1 is output as 0; alternatively, the digital random number is generated using the parity characteristic of the numerical value of the digital signal itself.

The invention is further described below with reference to the drawings and examples.

Although embodiments of the present invention have been described with reference to the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Example 1: referring to fig. 2, in this embodiment, the random number chip includes four main modules, namely, a light source module, a detector module, a data post-processing module, and a chip clock and control module; the detector module comprises a CIS pixel array and a readout circuit; the CIS pixel array is a pixel array formed by arranging silicon-based PN junctions in an array manner; the read-out circuit includes: the device comprises a row decoder, a column decoder, a sampling and holding circuit, a signal amplifying module AMP and an analog-to-digital conversion module ADC. The chip clock and control module comprises an IC control module, a time sequence module, an interface module and an LED control module. The light source module is a semiconductor light source and adopts an LED or an LD. The semiconductor light source module irradiates, the time sequence and the control unit of the random number chip control the semiconductor light source switch through the control circuit, and the detected photons are converted into electrons through the CMOS photodetector module.

In the embodiment of the invention, further, the light source module uses a semiconductor light source of a III-V material, and the detector module uses a CMOS light detector, namely the semiconductor light source of the III-V material and the CMOS light detector are used as an entropy source or a random source of random numbers. After a chip clock and control module of the random number chip, namely a time sequence and control unit, is connected with a peripheral control signal of the random number chip, the clock and control module of the random number chip sends out LED luminous driving and control signals, and a control circuit is used for controlling the light source module, namely the switch of the semiconductor light source; meanwhile, a chip clock and control module of the random number chip sends out a CIS reading control signal and accesses a detector module, namely a CIS pixel and a reading circuit, and then the detector module is connected with a data post-processing module and then is connected with and drives a reading voltage reference comparison module and a parity check module in sequence; the analog-to-digital conversion module ADC of the reading circuit in the detector module inputs the digital signal with the width of N bits to the parity check module by the reading voltage reference comparison module after the data is input into the data post-processing module, and finally, the parity check module outputs a serial digital random sequence. The semiconductor light source of the III-V material is a semiconductor Light Emitting Diode (LED) or a semiconductor Laser (LD) which emits light in a visible wave band based on gallium arsenide and gallium nitride materials.

The detector module is a CMOS photodetector, which is also called a CIS detector, and also called a CMOS image sensor. The light quanta in the entropy source are detected using a CIS detector, converting the number of light quanta into the number of electrons. The CMOS photodetector comprises a CIS pixel array and a readout circuit; the CIS pixel array is a detector micro-component formed by a silicon-based PN junction in a certain process structure, and the detector micro-component is arranged in an array to form a pixel array; the read-out circuit comprises a row decoder and a column decoder of an address decoder, a source follower and a sampling and holding circuit.

The data post-processing module generates random bits through parity check according to the digital randomness after analog-to-digital conversion of the analog-to-digital conversion module ADC.

In this embodiment, since the detector module, i.e., the CIS detector occupies a larger area in the main silicon-based circuit of the whole chip, it is preferable that the timing module in the chip clock and control module be designed and arranged in the detector module.

In the foregoing, preferably, the light source module adopts a front-side light-emitting high-brightness LED, and the light path of the light reaching the CIS pixel array in the detector module is designed by calculating the front-side light-emitting high-brightness position and the irradiation angle. The front-side luminous high-brightness LED light source module controls the switch of the front-side luminous high-brightness LED light source module to have a corresponding current stabilizing function through an IC control module in a chip clock and control module.

In this embodiment, the light source module uses the semiconductor light source to emit light to directly or indirectly irradiate the detector module, i.e., the CIS detector. The detection wave band of the detector module, namely the CMOS photodetector, needs to be matched with the wave band of the semiconductor light source for emitting light. The CMOS photodetector using different materials for the light emission of the semiconductor light source with different wavelengths comprises a CMOS photodetector module using Si base for the light emission of the semiconductor light source with visible wave band.

In this embodiment, since sampling and holding of the detector module, that is, the CIS pixel array of the CMOS photodetector module needs time, and the random number chip needs to have a high random number output bit rate, the CMOS photodetector module adopts the CIS pixel array, which is also a CIS image sensing array, and the rate of random number generation can be achieved by adjusting the size of the CIS pixel array. The CIS pixel array can be designed into 320 x 256 arrays and 640 x 512 arrays or even larger arrays, so that the generation rate of random numbers is improved, and further, different application scene requirements are met.

In this embodiment, the circuit structure of the CIS pixel and the readout circuit of the CMOS photodetector is shown in fig. 3. The row decoder is responsible for selecting the row. The row buses of all pixels of each row of the CIS pixel array are connected together, the current readout row is selected through a row decoder in the address decoder, serial readout is carried out on the current readout row through a column decoder, and then row signals are led out through a source follower. The column signals of the pixels in all CIS pixel arrays in the same column are connected together to sample and hold the sampling and holding circuit to generate V used as an analog-to-digital conversion module ADC _REF Signal and V _SIG A signal.

In this embodiment, the CIS pixel array is a silicon-based PN junction detector, and has a 3T-pixel structure, or a 4T-PPD or 5T-PPD structure with a transmission gate PPD structure (Pinned PhotoDiode). Compared with a normal PN structure, the PPD structure limits an N-type doped region below the surface of Si, the surface of the PPD structure maintains P-type doping, and has the characteristics of high quantum efficiency and low dark current, and the PPD is a common CIS structure.

In this embodiment, the sample and hold circuit determines that the sample signal is valid, the detector device transmits a photogenerated carrier, and when the integration time is over, a certain amount of charge is stored in the capacitor, where the amount of charge is an original signal subject to poisson distribution, and the calculated voltage on the integration capacitor is amplified by cooperatively controlling the access amplifying circuit by the column signal in the integration time. At this time, the column signal is a certain analog signal after pixel sampling; introducing the sampled and held obtained signal into an analog-to-digital conversion module ADC, and converting the sampled and held signal into a digital signal with N bits of width; the digital signal of the bit width corresponds to the original data of the random number which is subjected to poisson distribution.

In this embodiment, an interface module in a chip clock and control module of the random number chip adopts IIC protocol to control the chip, and outputs a random number sequence through SPI communication protocol.

In this embodiment, the number of photons that can be detected in a certain integration time between the CIS pixel array of the CMOS photodetector module and the readout circuit follows poisson distribution, i.e., the signal value is a random variable X that follows poisson distribution.

The sum of all probability terms with even k is:

sum all probability terms with k being odd to:

when the parameter lambda has a certain number:

the random signal is digitized through an analog-to-digital conversion module ADC to obtain a digital random number which is compliant with Poisson distribution. The data is input into a parity check module to judge, and the odd numbers of 1 are corresponding to 1, the even numbers of 1 are corresponding to 0, wherein the probabilities of odd numbers and even numbers are approximately 1/2, and the final output random number sequence can be generated at a certain speed.

In the embodiment, a semiconductor light source and a CMOS detector of a III-V material are used as entropy sources of random numbers; converting the photon number in the integration time into a level by a CMOS photodetector readout circuit; the level is subjected to reference value comparison analysis, and a comparison circuit screening and removing mechanism is provided for random signal deviation caused by the process deviation of the CMOS detector; converting the analog detection signal into a digital signal through a digital-to-analog conversion module; and generating random number bits by a digital signal post-processing mode of parity check. The semiconductor light source irradiates by adopting an LED or an LD, the time sequence and the control unit of the random number chip control the switch of the semiconductor light source through a control circuit, the detected photons are converted into electrons through the CMOS photodetector module, the photon number in the integration time is converted into the level through a reading circuit, the photo-generated current is generated, and the photo-generated current is output to the pixel array of the random number chip; the random number chip samples row pixels of the pixel array through a row decoder; the random number chip converts the photo-generated current into a voltage value through sampling capacitance integration; the random number chip leads out the voltage signal of the selected pixel through the column decoder; self-checking the voltage signal through a comparator; the random number chip converts the voltage signal into a corresponding digital signal conforming to poisson distribution; the digital signal is connected to the parity check module and carries out parity value judgment, and the random number chip digital integrated circuit corresponds to the output of digital random numbers which are uniformly distributed and obey 0-1 in a parity check mode, and the digital random numbers are true random numbers.

Example 2: an analog reference voltage comparison module is additionally arranged in a detector module, namely a readout circuit of the CMOS photodetector, and the readout voltage output by the pixel is compared with a reference voltage value. The analog reference voltage comparison module comprises a primary digital comparator, a register and a secondary digital comparator which are sequentially connected. Correspondingly, a read-out voltage reference comparison module is arranged in the data post-processing module, and after the read-out circuit of the detector module is accessed to data, the read-out voltage reference comparison module is accessed first, and then the parity check module is accessed.

In this embodiment, since the CIS may have a certain process deviation in the semiconductor process, there may be blind pixels or overheated pixels in the array. The response rate of the blind Pixel (Pixel) to light is 0, and the readout current is the dark signal value of the detector. The current generated by overheating the picture element tends to be saturated with the detector. Therefore, the voltage value of the integration capacitor of the normal pixel under the illumination of constant LED driving current is within a certain interval voltage. Particularly, for the problem of random number deviation output caused by blind pixels or overheat pixels in the pixels, the analog reference voltage comparison module is used for carrying out secondary digital comparison screening, so that the stability and reliability of random number output are further ensured. The connection structure of the analog reference voltage comparison module is shown in fig. 4, wherein the primary digital comparator is used for screening and removing blind pixels, and pixel readout voltage of the primary digital comparator is required to be larger than a reference voltage value and can be output; the secondary digital comparator is used for screening and removing overheat pixels, and the pixel readout voltage is required to be smaller than the reference voltage value to be output. One end of the primary digital comparator is connected with the minimum value of the normal signal, the other end of the primary digital comparator is connected with the read-out signal of the pixel, the output signal is a comparison result, the comparison result is connected with the enabling port of the register, the signal conforming to the minimum value range of the signal is connected with the secondary digital comparator and is compared with the maximum value of the normal signal, the comparison result is connected with the enabling port of the register, the register is connected with the signal value for comparison, and the comparison result is used as the enabling signal to control the output of the read-out signal of the pixel.

In this embodiment, after digital-to-analog conversion by the analog-to-digital conversion module ADC, a digital random number is obtained and follows poisson distribution, an N-bit digital signal output by the analog-to-digital conversion module ADC is led into the parity check module, an odd number in the N-bit two-level system data is corresponding to 1, wherein the probabilities of 0 and 1 are both approximately 1/2, the random number is further serially output, the numerical value corresponding to the multi-bit signal follows uniform distribution, and the parity check circuit is realized by the digital exclusive or gate.

In this embodiment, the analog reference voltage comparison module is integrated as a comparison self-checking module in the readout circuit of the detector module, and the comparison self-checking module is implemented in an analog integrated circuit manner. The comparison self-checking module performs self-checking on the original analog signals output by the pixels before the analog-to-digital conversion module ADC, and introduces the voltage signals within the normal range of values into the analog-to-digital conversion module ADC.

Example 3: the invention can also utilize the parity of the numerical value of the digital signal to generate random numbers, and lead out the last bit signal of the original signal which is subjected to poisson distribution, thereby realizing the verification by the parity characteristic of the numerical value of the signal.

Example 4: furthermore, the detector module adopts a CCD or PD array, and the detection wave band of the detector module is matched with the light-emitting wave band of the semiconductor light source. With a CCD array, the size of the random number generating chip will be further reduced.

Example 5: the connection structure design of the on-chip functional module in the embodiment 1 shown in fig. 2 can also be connected and coupled by different methods. Comprising the following steps:

preferably, on the random number chip, other modules or circuits are integrated on the same silicon-based circuit wafer (die) except for the light source module using the semiconductor light source of the III-V material. The light source module of the semiconductor light source using the III-V material and other silicon-based modules are integrated in the same chip through once encapsulation, namely, the internal die of the encapsulation structure only comprises LED bare die and silicon-based circuit bare die.

Optionally, the light source modules, the detector modules, the data post-processing module and the chip clock and control module are packaged respectively by mutually separated die, and then are connected through the substrate to form a random number chip, i.e. different modules are not integrated on the same die, but a plurality of die are connected together by adopting a separation module and utilizing a packaging substrate or other packaging technologies.

Optionally, the detector module, the data post-processing module, the chip clock and control module and other silicon-based circuit modules in the random number chip are packaged separately to form a chip with a transparent top cover, and the packaged transparent top cover is used for receiving the light source of the light source module to the detector module. On the basis, the chip with the transparent top cover is integrated with the light source module through a connection coupling technology to form the random number chip.

Optionally, the light source module is a semiconductor light source chip based on different process structures, and comprises a forward-mounted LED with a light emitting surface and an electrode surface on the same surface of the LED chip, a flip-chip LED with the light emitting surface and the electrode on two surfaces of the LED chip, a vertical-structure LED with the electrode on two surfaces of the LED chip, a side light emitting LED with the light emitting surface positioned on the side surface of the LED chip, and semiconductor lasers LD with various structures. The random number chip is based on the different light path coupling modes designed by utilizing the technology, packaging and integration technology, and integrates the light source module and the electronic circuit module to emit light and the electrode.

The present invention will be described in further detail with reference to the above examples, and it should be noted that the present invention is not limited thereto. In the technical field of the present invention, a person of ordinary skill in the art may easily make a plurality of simple deductions or alternative technical solutions without departing from the general inventive concept, and the technical solutions may belong to the protection scope defined by the claims filed by the present invention.

Claims (13)

1. The light quantum parity check random number chip comprises four main modules, namely a light source module, a detector module, a data post-processing module and a chip clock and control module; the detector module converts the photon number generated by the light source module in the integration time into the level through the reading circuit, generates photo-generated current and outputs the photo-generated current to the random number chip pixel array; the random number chip samples row pixels of the pixel array through a row decoder; the random number chip converts the photo-generated current into a voltage value through sampling capacitance integration; the random number chip leads out the voltage signal of the selected pixel through the column decoder; self-checking the voltage signal through a comparator; the random number chip converts the voltage signal into a corresponding digital signal conforming to poisson distribution; the digital signal is connected to the parity check module and carries out parity value judgment, and the random number chip digital integrated circuit corresponds to the output of digital random numbers which are uniformly distributed and obey 0-1 in a parity check mode, and the digital random numbers are true random numbers.

2. The light quantum parity random number chip of claim 1, wherein the detector module uses a CMOS photodetector, the detector module further comprising a CIS pixel array and readout circuitry; the CIS pixel array is a detector micro-component formed by arranging silicon-based PN junctions in an array manner to form a pixel array; the read-out circuit includes: a row decoder, a column decoder, a sample and hold circuit, a signal amplifying module AMP and an analog-to-digital conversion module ADC; the chip clock and control module comprises an IC control module, a time sequence module, an interface module and an LED control module; the light source module is a semiconductor light source and adopts an LED or an LD. After a chip clock and control module of the random number chip, namely a time sequence and control unit, is connected with a peripheral control signal of the random number chip, the clock and control module of the random number chip sends out LED luminous driving and control signals, and a control circuit is used for controlling the light source module, namely the switch of the semiconductor light source; meanwhile, a chip clock and control module of the random number chip sends out a CIS reading control signal and accesses a detector module, namely a CIS pixel and a reading circuit, and then the detector module is connected with a data post-processing module and then is connected with and drives a reading voltage reference comparison module and a parity check module in sequence; the analog-to-digital conversion module ADC of the reading circuit in the detector module inputs the digital signal with the width of N bits to the parity check module by the reading voltage reference comparison module after the data is input into the data post-processing module, and finally, the parity check module outputs a serial digital random sequence; the CIS pixel array is a detector micro-component formed by a silicon-based PN junction in a certain process structure, and the detector micro-component is arranged in an array to form a pixel array; the digital random number is obtained after the analog-digital conversion module ADC is subjected to digital-analog conversion and is subjected to Poisson distribution, N-bit digital signals output by the analog-digital conversion module ADC are imported into the parity check module, odd numbers in N-bit two-level system data of the digital random number are corresponding to 1, the probability of 0 and 1 is approximately 1/2, the random number is further output in series, the numerical values corresponding to the multi-bit signals are subjected to uniform distribution, and the parity check circuit is realized through the digital exclusive OR gate.

3. The optical quantum parity check random number chip according to claim 1, wherein the number of photons which can be detected is in poisson distribution within a certain integration time of the CIS pixel array of the CMOS photodetector module and the readout circuit, i.e. the signal value is a random variable X in poisson distribution; the digital signal conforming to poisson distribution is converted into a single random bit by means of parity check.

4. The optical quantum number parity check random number chip according to claim 1, wherein the parity check mode is implemented by a digital integrated circuit, parity check is performed on the digital-to-analog converted N-bit digital signal, and when an odd number of 1 outputs are 1, and when an even number of 1 outputs are 0; alternatively, the digital random number is generated using the parity characteristic of the numerical value of the digital signal itself.

5. The light quantum parity random number chip of claim 1 wherein the light source module uses a semiconductor light source of a group iii-v material; the semiconductor light source of the III-V material is a III-V light emitting diode, and refers to a semiconductor Light Emitting Diode (LED) or a semiconductor Laser (LD) which emits light in a visible wave band based on materials such as gallium arsenide, gallium nitride and the like.

6. The optical quantum parity check random number chip according to claim 1, wherein an analog reference voltage comparison module is additionally arranged in a readout circuit of a detector module, namely a CMOS photodetector, and the readout voltage output by the pixel is compared with a reference voltage value; the analog reference voltage comparison module comprises a primary digital comparator, a register and a secondary digital comparator which are sequentially connected; setting a read voltage reference comparison module in the data post-processing module, and after the read circuit of the detector module is accessed to data, accessing the read voltage reference comparison module and then accessing the parity check module; the first-level digital comparator is used for screening and removing blind pixels, and pixel readout voltage of the first-level digital comparator is required to be larger than a reference voltage value and can be output; the secondary digital comparator is used for screening and removing overheat pixels, and the pixel readout voltage is required to be smaller than a reference voltage value and can be output; one end of the primary digital comparator is connected with the minimum value of the normal signal, the other end of the primary digital comparator is connected with the read-out signal of the pixel, the output signal is a comparison result, the comparison result is connected with the enabling port of the register, the signal conforming to the minimum value range of the signal is connected with the secondary digital comparator and is compared with the maximum value of the normal signal, the comparison result is connected with the enabling port of the register, the register is connected with the signal value for comparison, and the comparison result is used as the enabling signal to control the output of the read-out signal of the pixel.

7. The light quantum parity random number chip according to claim 1, wherein in the CIS pixel array of the CMOS photodetector, the row decoder is responsible for selecting the row; the row buses of all pixels of each row of the CIS pixel array are connected together, the current readout row is selected through a row decoder in the address decoder, serial readout is carried out on the current readout row through a column decoder, and then row signals are led out through a source follower; the column signals of the pixels in all CIS pixel arrays in the same column are connected together to sample and hold the sampling and holding circuit to generate V used as an analog-to-digital conversion module ADC _REF Signal and V _SIG A signal.

8. The light quantum parity random number chip according to claim 1, wherein the CIS pixel array is a silicon-based PN junction detector having a 3T-pixel structure, or a 4T-PPD or 5T-PPD structure with a transmission gate PPD structure.

9. The optical quantum number parity check random number chip according to claim 1, wherein an interface module in a chip clock and control module of the random number chip adopts an IIC protocol to control the chip, and outputs a random number sequence through an SPI communication protocol.

10. The light quantum parity random number chip of claim 5 wherein on the random number chip, other modules or circuits are integrated on the same silicon-based circuit wafer (die) except for the light source module using the semiconductor light source of group iii-v material; the light source module of the semiconductor light source using the III-V material and other silicon-based modules are integrated in the same chip through once encapsulation, namely, the internal die of the encapsulation structure only comprises LED bare die and silicon-based circuit bare die.

11. The light quantum number parity check random number chip according to claim 1, wherein the light source module, the detector module, the data post-processing module and the chip clock and control module are packaged by mutually separated die, and then connected through a substrate to form the random number chip.

12. The light quantum parity check random number chip according to claim 1, wherein the detector module, the data post-processing module and the chip clock and control module in the random number chip are individually packaged by a silicon-based circuit module to form a chip with a transparent top cover, and the packaged transparent top cover is used for receiving the light source of the light source module into the detector module; on the basis, the chip with the transparent top cover is integrated with the light source module through a connection coupling technology to form the random number chip.

13. The light quantum parity random number chip according to claim 1, wherein the light source module is a semiconductor light source chip, and comprises a front-mounted LED having a light emitting surface and an electrode surface on the same surface of the LED chip, flip-chip LEDs having a light emitting surface and an electrode on both surfaces of the LED chip, vertical structure LEDs having electrodes on both surfaces of the LED chip, side light emitting LEDs having a light emitting surface on a side surface of the LED chip, and semiconductor lasers LD of various structures.