CN117350205A - Verification methods, devices, electronic equipment and storage media for chips - Google Patents

Abstract

The embodiment of the disclosure discloses a chip verification method, a device, an electronic device and a storage medium, wherein the method comprises the following steps: acquiring a physical unit library of a chip to be verified, wherein the physical unit library comprises behavior models corresponding to all physical units of the chip to be verified; converting the physical unit library into a synthesizable physical unit library; the comprehensive physical unit library comprises a comprehensive model meeting the preset conditions of the target verification platform; the synthesizable model is a model which is consistent with the behavior logic of the behavior model and can be synthesized into a netlist; based on the synthesizable model in the synthesizable physical unit library, verifying the chip to be verified through the target verification platform to obtain a verification result. The embodiment of the disclosure can keep the consistency of the synthesized netlist circuit function of the chip to be verified and the original behavior-level code theory simulation function, so that the verification of the structure of the physical unit of the chip to be verified is not influenced, and the improvement of the sufficiency of chip verification is facilitated.

Description

Verification methods, devices, electronic equipment and storage media for chips

Technical field

The present disclosure relates to the field of chip verification technology, and in particular, to a chip verification method, device, electronic equipment and storage medium.

Background technique

When verifying a chip, the model (also called code) provided by the chip manufacturer that describes the physical unit of the chip (that is, the physical standard unit, standard cell) is usually a behavioral model (behavior module, also called a behavioral model). The behavioral model is only applicable to the Simulator verification platform on the server, and is not applicable to simulation accelerator verification platforms such as Emulator. In related technologies, when a chip needs to be verified through an analog accelerator verification platform, it is usually necessary to modify the underlying standard unit code of the chip (i.e., behavioral-level code). The non-synthesizable logic in the underlying standard unit code will lead to the netlist of the chip after synthesis. (netlist) The circuit function is inconsistent with the theoretical simulation function of the underlying standard unit code, and the structure of the physical unit cannot be verified, resulting in insufficient chip verification.

Contents of the invention

In order to solve the above technical problems such as insufficient chip verification, embodiments of the present disclosure provide a chip verification method, device, electronic device and storage medium to implement a comprehensive model based on the behavior logic consistent with the behavior model. The simulation accelerator verification platform's verification of chips helps improve the adequacy of chip verification.

A first aspect of the present disclosure provides a chip verification method, which includes: obtaining a physical unit library of the chip to be verified, where the physical unit library includes behavior models corresponding to each physical unit of the chip to be verified; The physical unit library is converted into a synthesized physical unit library; wherein the synthesized physical unit library includes a synthesized model that meets the preset conditions of the target verification platform; the synthesized model is one that can be synthesized into a netlist A model that is consistent with the behavioral logic of the behavioral model; based on the synthesized model in the synthesized physical unit library, the chip to be verified is verified through the target verification platform to obtain verification results.

A second aspect of the present disclosure provides a chip verification device, including: an acquisition module for obtaining a physical unit library of the chip to be verified, where the physical unit library includes corresponding physical units of the chip to be verified. The behavioral model; the first processing module is used to convert the physical unit library into a comprehensive physical unit library; wherein the comprehensive physical unit library includes a comprehensive model that meets the preset conditions of the target verification platform; the The synthesizable model is a model that can be synthesized into a netlist consistent with the behavioral logic of the behavioral model; the second processing module is used to pass the target verification based on the synthesizable model in the synthesized physical unit library. The platform verifies the chip to be verified and obtains verification results.

A third aspect of the disclosure provides a computer-readable storage medium, the storage medium stores a computer program, and the computer program is used to execute the chip verification method described in any of the above embodiments of the disclosure.

A fourth aspect of the present disclosure provides an electronic device, the electronic device comprising: a processor; a memory for storing instructions executable by the processor; and the processor for reading from the memory. The executable instructions are executed to implement the chip verification method described in any of the above embodiments of the present disclosure.

A fifth aspect of the present disclosure provides a computer program product. When instructions in the computer program product are executed by a processor, the chip verification method provided by any of the above embodiments of the present disclosure is executed.

Based on the chip verification method, device, electronic equipment and storage medium provided by the above embodiments of the present disclosure, by converting the behavioral model of the physical unit of the chip to be verified into a synthetic model that satisfies the conditions of the target verification platform, and then Based on the synthesized model, the chip to be verified is verified through the target verification platform to obtain verification results. It is possible to verify the chip to be verified based on verification platforms such as Emulator without modifying the original design code of the chip to be verified. Since the behavioral logic of the synthesized model and the behavioral model are consistent, the synthesis of the chip to be verified can be maintained. The final netlist circuit function is consistent with the behavioral-level code theoretical simulation function, thereby not affecting the verification of the structure of the physical unit of the chip to be verified, and helping to improve the adequacy of chip verification.

Description of drawings

Figure 1 is an exemplary application scenario of the chip verification method provided by the present disclosure;

Figure 2 is a schematic flowchart of a chip verification method provided by an exemplary embodiment of the present disclosure;

Figure 3 is a schematic flow chart of a chip verification method provided by another exemplary embodiment of the present disclosure;

Figure 4 is a schematic flowchart of a chip verification method provided by yet another exemplary embodiment of the present disclosure;

Figure 5 is a schematic flowchart of a chip verification method provided by yet another exemplary embodiment of the present disclosure;

Figure 6 is a schematic structural diagram of a chip verification device provided by an exemplary embodiment of the present disclosure;

Figure 7 is a schematic structural diagram of a chip verification device provided by another exemplary embodiment of the present disclosure;

FIG. 8 is a structural diagram of an electronic device provided by an embodiment of the present disclosure.

Detailed ways

In order to explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all embodiments. It should be understood that the present disclosure is not intended to be exemplified. Limitations of sexual embodiment.

It should be noted that the relative arrangement of components and steps, numerical expressions, and numerical values set forth in these examples do not limit the scope of the disclosure unless otherwise specifically stated.

Overview of the Disclosure

In the process of realizing the present disclosure, the inventor found that when verifying the chip, the model (also called code) provided by the chip manufacturer to describe the physical unit of the chip (ie, physical standard unit, standard cell) is usually a behavioral-level model. (behavior module, can be called a behavioral model), the behavioral model is only applicable to the Simulator verification platform on the server, and is not applicable to simulation accelerator verification platforms such as Emulator. In related technologies, when a chip needs to be verified through an analog accelerator verification platform, it is usually necessary to modify the underlying standard unit code of the chip (i.e., behavioral-level code). The non-synthesizable logic in the underlying standard unit code will lead to the netlist of the chip after synthesis. (netlist) The circuit function is inconsistent with the theoretical simulation function of the underlying standard unit code, and the structure of the physical unit cannot be verified, resulting in insufficient chip verification.

Illustrative overview

Figure 1 is an exemplary application scenario of the chip verification method provided by the present disclosure.

As shown in Figure 1, for a chip to be verified, using the verification method of the chip of the present disclosure (which can be executed in the verification device of the chip of the present disclosure), the physical unit library of the chip to be verified can be obtained, and the physical unit library includes the chip to be verified. Behavior models corresponding to each physical unit; convert the physical unit library into a synthesized physical unit library; among which, the synthesized physical unit library includes a synthesized model that meets the preset conditions of the target verification platform; the synthesized model is one that can be A model is synthesized into a netlist that is consistent with the behavioral logic of the behavioral model; based on the synthesized model in the synthesized physical unit library, the chip to be verified is verified through the target verification platform to obtain verification results. The target verification platform may include at least one of an Emulator verification platform (which may be referred to as an EMU platform), a prototype verification platform, and the like. Since the behavioral model of the physical unit is converted into a synthesized model that is consistent with the behavior logic of the behavioral model, the synthesis tool can synthesize the hardware description language of the physical unit into a netlist during verification to facilitate verification of the chip to be verified. Verification of the chip to be verified can include RTL (Register Transfer Level, register transfer level) functional verification and netlist functional verification of the chip to be verified, which can be applied to both simulation accelerator verification platforms such as Emulator and prototype verification platforms, such as FPGA (Field Programmable Gate Array, field programmable logic gate array) verification platform can avoid the inconsistency between the synthesized netlist circuit function and the theoretical simulation function of the underlying standard unit code due to modification of the underlying standard unit code of the chip to be verified, making it impossible to verify the physical The structure and function of the unit are verified, which helps to improve the adequacy of chip verification.

Example methods

FIG. 2 is a schematic flowchart of a chip verification method provided by an exemplary embodiment of the present disclosure. This embodiment can be applied to electronic devices, such as terminal devices, servers and other electronic devices. As shown in Figure 2, it includes the following steps:

Step 201: Obtain the physical unit library of the chip to be verified. The physical unit library includes behavioral models corresponding to each physical unit of the chip to be verified.

Among them, the physical unit is the circuit at the bottom of the chip to be verified, such as an NOR circuit, a multiple-select circuit, a register circuit with different reset functions, a power control circuit, etc. A behavioral model is a behavioral-level description of a physical unit, that is, a hardware description language code segment used to describe the functional behavior of a physical unit. For example, a code segment that describes the behavior of the output as the input changes. The physical unit library (which can be called a behavioral-level physical unit library) can be independent of the original design code of the chip to be verified. The original design code of the chip to be verified is the hardware description language code that describes the structure and function of the chip to be verified.

For example, the physical unit is a multi-input single-output unit composed of AND gates and OR gates, and its behavior model may include an input-output truth table (Loop Up Table, referred to as LUT) description, that is, the output corresponding to different inputs.

Step 202: Convert the physical unit library into a synthesized physical unit library; wherein the synthesized physical unit library includes a synthesized model that meets the preset conditions of the target verification platform.

Among them, a synthesizable model is a model that can be synthesized into a netlist and is consistent with the behavioral logic of the behavioral model. Consistent behavioral logic can mean that the input and output behaviors of the synthesized model are logically consistent with the input and output behaviors of the behavioral model, that is, for any same input, the output of the synthesized model is consistent with the output of the corresponding behavioral model. The inputs of the behavioral level model may include inputs such as 0, 1, X, and Z, where 0 and 1 represent logic levels, X represents an unknown state, and Z represents a high-impedance state. On the target verification platform, the input of the model does not have an X state (i.e., an unknown state). For example, for the EMU platform, the input of the model does not have an With the same 0, 1, and Z inputs, the output of the synthesized model is consistent with the output of the corresponding behavioral model.

In some optional embodiments, the preset conditions can be set according to the functional logic that the target verification platform needs to involve in the verification process and the comprehensive description method it supports. Synthesizable description methods refer to description methods that can be recognized by synthesis tools and synthesized into netlists. The synthesis tool can be any implementable synthesis tool for the target verification platform.

For example, redundant logic that cannot be synthesized or is invalid during the verification process of the target verification platform can be eliminated when converting to a synthesized model to reduce resource usage during the verification process. For example, for a physical unit with a power port, if the power port is not involved when being verified on the Emulator verification platform, then the logic related to the power port can be eliminated when converting to a synthesizable model. For another example, when converting to a synthesizable model, the timing status check part has no actual functional impact on the actual physical circuit and is invalid redundant logic. By eliminating this part of logic, the resource usage of the simulation logic unit during the verification process can be reduced.

For example, in the Emulator verification platform, you can ignore the internal structure of the physical unit and only care about the response of the output of the physical unit to the input. When converting the synthesized model, as long as the input and output behaviors of the synthesized model can be made consistent with the behavioral model The behavioral logic is consistent, thereby achieving the same functions as the behavioral model without caring about the specific implementation structure inside the physical unit.

In some optional embodiments, the target verification platform may be an Emulator verification platform, a prototype verification platform (i.e., FPGA verification platform), or a verification platform in the early simulation verification stage, and is not specifically limited.

Step 203: Based on the synthesized model in the synthesized physical unit library, the chip to be verified is verified through the target verification platform to obtain verification results.

The verification of the chip to be verified may include at least one of verification of the RTL code of the chip to be verified, verification of the netlist of the chip to be verified, prototype verification of the chip to be verified, etc., and is not specifically limited.

In some optional embodiments, different target verification platforms can implement different verifications of the chips to be verified.

For example, the Emulator verification platform can perform hardware simulation on the chip to be verified, and perform system-level verification on the function, performance, power consumption, etc. of the chip to be verified (which can be referred to as EMU verification). The hardware authenticity and running speed of EMU verification are between EDA (Electronic Design Automation, electronic design automation) verification and FPGA verification. EDA verification can be implemented based on the Simulator verification platform to verify the consistency between the RTL code of the chip to be verified and the design plan. The FPGA verification platform verifies the correctness of the function and timing of the chip to be verified by transplanting the RTL code of the chip to be verified into the FPGA, which helps reduce tape-out risks, shorten the development cycle, reduce costs, and collaborate with software and hardware to reduce system risks.

In some optional embodiments, when the chip to be verified is verified, the physical unit library of the chip to be verified (which may be called the original physical unit library) can be replaced with a synthesizable physical unit library. That is to replace the behavioral-level hardware description code of the chip to be verified with a synthesized hardware description code, and then configure the replaced synthesized physical unit library of the chip to be verified to the target verification platform. The verification tool based on the target verification platform performs the verification on the chip to be verified. verify. For example, various verification tools based on the Emulator verification platform verify the chip to be verified. Since the original physical unit library can be independent of the original design code of the chip to be verified, when the chip to be verified is verified on the target verification platform, there is no need to modify the original design code of the chip to be verified, but by replacing the original physical unit library with its original design code. A synthesized physical unit library with consistent behavioral logic is used to verify the chip to be verified, so that the functions of the netlist circuit synthesized based on the synthesized physical unit library are consistent with the original behavioral-level code theoretical simulation function of the chip to be verified, so as to facilitate the verification Structural verification of the physical unit of the chip improves the adequacy of chip verification.

The chip verification method provided in this embodiment converts the behavioral model of the physical unit of the chip to be verified into a synthesized model that meets the conditions of the target verification platform, and then verifies the chip to be verified through the target verification platform based on the synthesized model. Get verification results. It is possible to verify the chip to be verified based on verification platforms such as Emulator without modifying the original design code of the chip to be verified. Since the behavioral logic of the synthesized model and the behavioral model are consistent, the synthesis of the chip to be verified can be maintained. The final netlist circuit function is consistent with the original behavioral-level code theoretical simulation function, thereby not affecting the verification of the structure of the physical unit of the chip to be verified, and helping to improve the adequacy of chip verification.

FIG. 3 is a schematic flowchart of a chip verification method provided by another exemplary embodiment of the present disclosure.

In some optional embodiments, as shown in Figure 3, step 202 of converting the physical unit library into a synthesizable physical unit library includes:

Step 2021: For the behavior model corresponding to any physical unit in the physical unit library, determine the conversion rule corresponding to the behavior model based on the identification information of the behavior model.

The identification information of the behavior model may be the name of the behavior model or other possible representation information. The conversion rules corresponding to the behavioral model are rules used to convert the behavioral model into a synthesizeable model. For example, for the behavioral model of the physical unit and (parameter 1, parameter 2, ..., parameter n) composed of the AND gate, the name describing the behavioral model can be used as the identification information of the behavioral model.

In some optional embodiments, corresponding conversion rules can be set in advance for various common types of behavior models. For example, for behavioral models of physical units such as and(), buf(), mux(), and lookup tables, corresponding conversion rules can be set. The conversion rules can be specifically set according to the different code description rules of the behavioral model of the physical unit and the synthesizable model.

In some optional embodiments, the functions implemented by the physical units can be determined according to the physical unit description document of the chip to be verified, and then these physical units can be classified, and the functions of the physical units of each type can be analyzed to find out the same Based on the similarities and differences between the behavioral models of different types of physical units in the synthesized model, the corresponding conversion rules for converting the behavioral models of each type of physical unit into a synthesized model are determined.

In some optional embodiments, for some general physical units, a synthesizable model corresponding to its behavior model can be directly set, and the identification information of the behavior model can be stored correspondingly to the synthesizable model. Then, the conversion rules corresponding to the behavior model may include rules for finding the synthesized model corresponding to the behavior model based on the identification information of the behavior model.

In some optional embodiments, for the lookup table logic inside the physical unit, statistics can be made on the types thereof, and for each lookup table logic, unified and comprehensive logic conversion rules can be set.

In some optional embodiments, the power signal inside the physical unit is analyzed. For logic with power signals, corresponding synthesizable logic conversion rules can be set according to the requirements of the target verification platform for the power port.

In some optional embodiments, the behavior models in the physical unit library can be traversed. For the behavior model of any traversed physical unit, the conversion rules corresponding to the behavior model are determined based on the identification information of the behavior model, and then based on The conversion rules corresponding to the behavior model perform subsequent conversion processing.

In some optional embodiments, the conversion rules may include rules for converting valid logic into synthesized logic, rules for eliminating redundant logic, etc., so that the converted synthesizeable model can comply with the corresponding preset conditions of the target verification platform.

In some optional embodiments, the behavioral model is a more comprehensive description of the theoretical function of the physical unit. When converted into a synthesizable model, the comprehensive theoretical behavioral-level description can be converted into a simple one according to the verification requirements of the target verification platform. A comprehensive description that is more in line with actual verification needs. For example, some parameters in the behavioral model are not used when the target verification platform is used for verification, but are only used when the chip is implemented. These parameters can be simplified to further reduce the resource usage of the verification process. For example, in a behavioral model, there are many logic units (such as AND gates, OR gates, NOT gates, etc.). The synthesized model does not need to consider how many logic units are implemented, as long as the input and output behavior of the synthesized model can be achieved. The logic and behavioral model only need to be consistent, thereby simplifying the model and reducing resource usage in the verification process.

Step 2022: Convert the behavioral model into a synthesized model based on the conversion rules corresponding to the behavioral model.

Among them, after determining the conversion rules corresponding to the behavioral model, the behavioral model can be converted into a synthesized model based on the conversion rules corresponding to the behavioral model, so that the synthesized model obtained by the conversion can meet the corresponding preset conditions of the target verification platform. , and can be synthesized by synthesis tools into the netlist corresponding to the chip to be verified, so as to facilitate the verification of the chip to be verified.

In the related technology verification method of modifying the underlying standard unit code of the chip to adapt to the analog accelerator verification platform, due to the modification of the underlying standard unit code of the chip, on the one hand, the non-synthesizable logic of the underlying standard unit code will cause the chip to be synthesized after The netlist circuit function is inconsistent with the underlying standard unit code theoretical simulation function, resulting in insufficient chip verification. On the other hand, during the verification process on the analog accelerator verification platform, during the UPF (Unified Power Format) verification stage, the UPF design structure needs to be modified, resulting in UPF The associated verification cannot be consistent with the original design. In the later stage of netlist verification, it is necessary to directly use the non-synthesizable model (i.e., behavioral model) and modify the violation constraint check of the Emulator verification platform. Because there may be redundant logic in the non-synthesizable model, it is easy to cause simulation logic unit resources during the verification process. Increased usage. The disclosed embodiments can convert effective logic into synthesized logic through the conversion rules corresponding to the behavioral model, and can eliminate redundant logic. On the one hand, the integrated netlist circuit function of the chip can be kept consistent with the original behavioral-level code theoretical simulation function. It does not affect the subsequent verification of the structure of the physical unit of the chip. On the other hand, during the UPF verification phase, there is no need to modify the UPF design structure, and the consistency of UPF-related verification and the original design can be maintained to avoid verification defects. In addition, because the behavioral logic of the synthesized model and the behavioral model are consistent, in the later netlist verification stage, the synthesized model can be directly synthesized into a netlist for verification without modifying the Emulator violation constraint check, and because the synthesized model can eliminate redundancy logic, helping to reduce the resource usage of the simulation unit of the verification process.

In some optional embodiments, determining the conversion rules corresponding to the behavior model based on the identification information of the behavior model in step 2021 includes:

Based on the identification information of the behavior model, the convertible state corresponding to the behavior model is determined; in response to the convertible state being the first state, the conversion rule corresponding to the behavior model is determined based on the identification information.

Among them, if the behavior model traversed is a relatively common behavior model, the corresponding conversion rule may already exist. If the behavior model traversed is a less commonly used behavior model, the corresponding conversion rule may not be found. Therefore, it can be based on The identification information of the behavior model determines whether the behavior model is convertible (ie, determines the convertible state of the behavior model). Convertible states can include convertible and non-convertible states. If it is determined that a corresponding conversion rule exists, it is determined that the convertible state of the behavior model is convertible. If there is no corresponding conversion rule, it can be determined that the convertible state of the behavior model is unconvertible. When it is determined that the convertible state corresponding to the behavior model is convertible (ie, the first state), the conversion rule corresponding to the behavior model is determined based on the identification information of the behavior model.

In some optional embodiments, a convertible identification library or a convertible identification list can be set for a behavioral model for which conversion rules already exist, and a mapping relationship between convertible identification information and conversion rules can be established. For each behavior model traversed, the identification information of the behavior model is matched with the convertible identification library or the convertible identification list to determine the convertible state of the behavior model. If it is determined that the convertible state of the behavior model is the first state, the conversion rule corresponding to the behavior model can be determined based on the mapping relationship between the convertible identification information and the conversion rule.

In some optional embodiments, the conversion rule may be a conversion code function described in any implementable language. Including but not limited to various high-level languages. This allows the conversion of behavioral models to synthesized models through function calls.

In this embodiment, the convertible state of the behavioral model is first determined to facilitate conversion of the convertible behavioral model. The non-convertible model can be processed in other ways to obtain the final synthesized physical unit library.

In some optional embodiments, determining the conversion rules corresponding to the behavior model based on the identification information of the behavior model in step 2021 also includes:

In response to the convertible state being the second state, prompt information corresponding to the behavior model is output.

Among them, the second state is an unconvertible state. For behavior models that cannot be converted, corresponding prompt information can be output to remind users (such as conversion rule developers) that the behavior model cannot be converted and the user should handle it accordingly. For example, users can provide corresponding conversion rules for the behavior model.

In some optional embodiments, after outputting the prompt information corresponding to the behavior model, the behavior model can be marked to mark that the behavior model has not completed conversion, and then the next behavior model is processed. When the physical unit is traversed, After each behavioral model in the library is traversed twice, the marked behavioral model that has not completed the conversion is traversed again, or the user triggers the second traversal of the behavioral model that has not completed the conversion. For example, when processing is paused after completing a traversal, a pop-up window can prompt the user, such as "There are physical units that have not completed conversion. Do you want to traverse again?" The user can provide corresponding conversion rules for the behavioral models of unconverted physical units, and then trigger a second traversal, so that the device of the present disclosure continues to traverse the unconverted behavioral models until the conversion of all behavioral models in the physical unit library is completed. , obtain a synthesized physical unit library.

In this embodiment, when a non-convertible behavior model is traversed, prompt information can be output, so as to promptly prompt the user to perform corresponding processing.

In some optional embodiments, after outputting the prompt information corresponding to the behavior model, it also includes:

Obtain the conversion rules corresponding to the behavior model input by the user; based on the conversion rules corresponding to the behavior model, convert the behavior model into a comprehensive model.

Among them, the user can input the transformation rules corresponding to the behavior model in any implementable way, for example, in the form of a file. After obtaining the conversion rule corresponding to the behavior model input by the user, the behavior model can be converted into a synthesized model based on the conversion rule.

In some optional embodiments, after obtaining the conversion rule corresponding to the behavior model input by the user, the device of the present disclosure can store the conversion rule corresponding to the identification information of the behavior model, and can add the identification information to A convertible logo library or a convertible logo list to facilitate subsequent determination and conversion of the convertible state.

In some optional embodiments, the user can also input the conversion rules of multiple non-convertible behavior models together. After obtaining the conversion rules of multiple behavior models, the device of the present disclosure stores the conversion rules corresponding to each behavior model. And traverse the behavioral models that failed to be converted in the previous traversal process again. Each behavioral model that failed to be converted is converted according to the above process to obtain a comprehensive physical unit library.

In this embodiment, for the behavioral models that cannot be converted, the user can further provide corresponding conversion rules, so that these behavioral models that cannot be converted can continue to be converted into synthesized models, so that combined with a small amount of labor cost, the synthesized model can be realized Efficient determination of physical cell libraries.

FIG. 4 is a schematic flowchart of a chip verification method provided by yet another exemplary embodiment of the present disclosure.

In some optional embodiments, as shown in Figure 4, step 202 of converting the physical unit library into a synthesizable physical unit library also includes:

Step 2023, in response to completing the conversion of the behavioral model in the physical unit library, obtain an initial synthesizable physical unit library.

Among them, the synthesized physical unit library obtained by completing the above conversion can be used as the initial synthesized physical unit library.

Step 2024: Perform consistency verification on the physical unit library and the initial synthesizable physical unit library, and obtain the consistency verification results corresponding to the initial synthesizable physical unit library.

In some optional embodiments, consistency verification may include at least one of functional consistency verification (ie, simulation consistency verification) and formal consistency verification (ie, Formality consistency verification). Simulation consistency verification is used to verify the behavioral and functional consistency between the obtained initial synthesized physical unit library and the original physical unit library. For example, the same random excitation is applied to the synthesized model and the corresponding behavioral model in the initial synthesized physical unit library, and the first output result corresponding to the synthesized model and the second output result corresponding to the behavioral model are obtained, and the first output result is Compare with the second output result to verify the consistency between the two. Formality consistency verification is used to perform netlist-level consistency verification. The same traversable excitation can be applied to both models and the output results of the two models can be compared.

In some optional embodiments, the consistency verification is based on software simulation tool verification to ensure the accuracy of the conversion of the present disclosure.

In some optional embodiments, the consistency of the initial synthesizable physical unit library and the original physical unit library can also be cross-verified through different verification tools to fully cover the verification of all functions and avoid chip verification caused by inaccurate conversion. Inadequate situation.

Step 2025: In response to the consistency verification result satisfying the consistency condition, use the initial synthesizable physical unit library as the synthesizable physical unit library corresponding to the physical unit library.

Among them, the consistency conditions can be set according to actual needs. For example, if the outputs of the two models are consistent for each identical stimulus applied to the two models, it can be determined that the consistency verification result satisfies the consistency condition. If it is determined that the consistency verification result satisfies the consistency condition, it means that the obtained initial synthesized physical unit library has behavioral logic consistency with the original physical unit library, and the initial synthesized physical unit library can be used as the synthesized physical unit library corresponding to the physical unit library. Unit library for verification of target verification platform.

In this embodiment, the synthesized physical unit library obtained after the conversion is used as the initial synthesized physical unit library, and the consistency between the initial synthesized physical unit library and the original physical unit library is verified. The initial synthesized physical unit that passes the verification The library can be used to replace the original non-synthesizable physical unit library for verification of the chip to be verified, to ensure the accuracy and reliability of the synthesized physical unit library obtained, and to ensure the reliability and comprehensive coverage of the verification of the chip to be verified. .

FIG. 5 is a schematic flowchart of a chip verification method provided by yet another exemplary embodiment of the present disclosure.

In some optional embodiments, step 2024 performs consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain the consistency verification results corresponding to the initial synthesizable physical unit library, including:

Step 20241: Based on the preconfigured functional consistency verification environment, perform functional consistency verification on the physical unit library and the initial synthesizable physical unit library, and obtain the first verification result.

Among them, the simulation environment of the physical unit can be built for the chip to be verified, and the original physical unit library and the generated initial synthesized physical unit library can be configured in the same simulation environment at the same time, and they should be consistent with the simulation environment of the chip to be verified. The two models of the two unit libraries apply the same random excitation to obtain the output results corresponding to the two models. The output results of the two models are compared to determine the consistency of the output results, and then based on the corresponding random excitations, The output results are consistent and the first verification result is determined.

Step 20242: Based on the preconfigured formal consistency verification environment, perform formal consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain the second verification result.

Among them, Formality consistency verification is similar to the above-mentioned simulation consistency verification. You can build the physical unit Formality environment of the chip to be verified, configure the generated initial synthesized physical unit library and the original physical unit library in the same Formality environment, and Consistent with the Formality environment of the chip to be verified, the same traversable excitation is applied to the two models, the output results of the two models are compared, and the second verification result is obtained based on the comparison results.

It should be noted that the above-mentioned steps 20241 and 20242 have no dependency on the execution order and can be executed at the same time or one after another, and there is no restriction on the execution order.

Step 20243: Determine the consistency verification result based on the first verification result and the second verification result.

Among them, the integration method of the first verification result and the second verification result can be set according to actual needs.

This embodiment determines the consistency verification results of the two unit libraries by integrating the verification results of the two verification environments, which can realize cross-validation between different verification tools and improve the accuracy and reliability of the consistency verification results.

In some optional embodiments, the consistency verification result is determined based on the first verification result and the second verification result, including:

In response to both the first verification result and the second verification result being verification passed, it is determined that the consistency verification result satisfies the consistency condition; in response to either one of the first verification result and the second verification result being verification failed, the output verification results are inconsistent. prompt information.

Among them, if the first verification result and the second verification result are both verified, it can be determined that the initial synthesizable physical unit library is consistent with the original physical unit library, and can replace the original physical unit library for verification on the target verification platform. chip for verification. If either the first verification result or the second verification result fails the verification, it means that the initial synthesizable physical unit library is inconsistent with the original physical unit library, and the original physical unit library cannot be replaced for verification of the chip to be verified. . In response to this situation, a prompt message indicating inconsistent verification results can be output to prompt the user in a timely manner, and the user can handle it accordingly. For example, users can troubleshoot the causes of inconsistencies based on the prompt information, and can adjust the initial synthesizeable physical unit library, or adjust the conversion rules used to generate synthesized models. There is no specific limit. The output method of the prompt information and the specific content of the output are not limited. For example, the stimulus that produces inconsistent output and the inconsistent output can be output, as well as the specific location where the stimulus is applied, so that the user can quickly locate the inconsistent location.

In this embodiment, when the consistency verification result fails, corresponding prompt information can be output, so that the user can handle the inconsistency in a timely manner.

In some optional embodiments, step 2022 converts the behavioral model into a synthesizable model based on the conversion rules corresponding to the behavioral model, including:

Based on the detection rules corresponding to the behavior model, detect the start position and end position of the content to be converted in the behavior model; based on the starting position and end position, determine the content to be converted in the behavior model; convert the content to be converted into For target content that meets the preset conditions of the target verification platform, a synthesized model corresponding to the behavioral model is obtained.

Among them, the detection rules can be based on keywords included in the behavior model and parameter settings of the behavior model. For example, for the and() physical unit, the behavior model may include multiple parameters. Set detection rules based on the properties of its parameters and their requirements in the synthesized model that adapts to the target verification platform to identify the pending parameters in the behavior model. Converts the start and end positions of content. The content to be converted may include at least one of content to be replaced, content to be eliminated, and the like. For the content to be replaced, convert it from a non-synthesizable description mode to a synthesizable description mode. For content to be removed, remove it. For example, eliminate redundant parameters and redundant logic.

In some optional embodiments, the same behavioral model may include different numbers of parameters. For example, the and() behavioral model may include different numbers of inputs and different numbers of internal AND logic. The conversion rules corresponding to each behavioral model can also include a synthesized model template corresponding to the behavioral model and template filling rules corresponding to different parameters. The synthesized model template can include shareable parts under different parameters and needs to be targeted. Different parameters fill in different parts. Furthermore, for any behavioral model traversed, the synthesized model template can be filled in according to the specific conditions of the behavioral model to obtain the corresponding synthesized model.

This embodiment detects and identifies the content to be converted of the behavioral model, and then converts the content to be converted to obtain the corresponding synthesized model, thereby achieving accurate and effective conversion of the synthesized model.

In this disclosed embodiment, during the verification process of the chip to be verified based on the target verification platform, the power network of the chip to be verified can be verified in the RTL stage using a synthesized model that is consistent with the design of the chip to be verified. In the later netlist verification stage, , can truly simulate the functions of the chip to be verified, including joint debugging of the power network and other functions, which helps to improve the adequacy of chip verification.

Each of the above-mentioned embodiments of the present disclosure can be implemented individually or in any combination without conflict. The details can be set according to actual needs, and are not limited by this disclosure.

Any chip verification method provided by the embodiments of the present disclosure can be executed by any appropriate device with data processing capabilities, including but not limited to: terminal devices and servers. Alternatively, any of the chip verification methods provided in the embodiments of the present disclosure can be executed by a processor. For example, the processor executes any of the chip verification methods mentioned in the embodiments of the present disclosure by calling corresponding instructions stored in the memory. No further details will be given below.

Exemplary device

FIG. 6 is a schematic structural diagram of a chip verification device provided by an exemplary embodiment of the present disclosure. The device of this embodiment can be used to implement the verification method embodiment of the corresponding chip of the present disclosure. The device shown in Figure 6 includes: an acquisition module 51, a first processing module 52 and a second processing module 53.

The acquisition module 51 is used to acquire the physical unit library of the chip to be verified. The physical unit library includes behavioral models corresponding to each physical unit of the chip to be verified.

The first processing module 52 is used to convert the physical unit library into a synthesized physical unit library; wherein the synthesized physical unit library includes a synthesized model that meets the preset conditions of the target verification platform; the synthesized model is one that can be synthesized into A model of the netlist that is logically consistent with the behavior of the behavioral model.

The second processing module 53 is used to verify the chip to be verified through the target verification platform based on the synthesized model in the synthesized physical unit library, and obtain verification results.

FIG. 7 is a schematic structural diagram of a chip verification device provided by another exemplary embodiment of the present disclosure.

In some optional embodiments, the first processing module 52 includes: a first processing unit 521 and a second processing unit 522.

The first processing unit 521 is configured to determine the conversion rule corresponding to the behavior model based on the identification information of the behavior model for the behavior model corresponding to any physical unit in the physical unit library.

The second processing unit 522 is configured to convert the behavior model into a synthesizable model based on the conversion rules corresponding to the behavior model.

In some optional embodiments, the first processing unit 521 is specifically used to:

Based on the identification information of the behavior model, the convertible state corresponding to the behavior model is determined; in response to the convertible state being the first state, the conversion rule corresponding to the behavior model is determined based on the identification information.

In some optional embodiments, the first processing unit 521 is also configured to output prompt information corresponding to the behavior model in response to the convertible state being the second state.

In some optional embodiments, the first processing module 52 also includes: an acquisition unit 523, configured to acquire the conversion rules corresponding to the behavior model input by the user. The second processing unit 522 is specifically configured to convert the behavior model into a synthesizable model based on the conversion rules corresponding to the behavior model.

In some optional embodiments, the first processing module 52 also includes: a third processing unit 524, a fourth processing unit 525 and a fifth processing unit 526.

The third processing unit 524 is configured to obtain an initial synthesizable physical unit library in response to completing the conversion of the behavioral model in the physical unit library.

The fourth processing unit 525 is used to perform consistency verification on the physical unit library and the initial synthesizable physical unit library, and obtain the consistency verification result corresponding to the initial synthesizable physical unit library.

The fifth processing unit 526 is configured to use the initial synthesizable physical unit library as the synthesizable physical unit library corresponding to the physical unit library in response to the consistency verification result satisfying the consistency condition.

In some optional embodiments, the fourth processing unit 525 is specifically used to:

Based on the preconfigured functional consistency verification environment, the functional consistency verification is performed on the physical unit library and the initial synthesizable physical unit library, and the first verification result is obtained. Based on the preconfigured formal consistency verification environment, formal consistency verification is performed on the physical unit library and the initial synthesizable physical unit library, and the second verification result is obtained. Based on the first verification result and the second verification result, the consistency verification result is determined.

In some optional embodiments, the fourth processing unit 525 is specifically used to:

In response to both the first verification result and the second verification result being verification passed, it is determined that the consistency verification result satisfies the consistency condition; in response to either one of the first verification result and the second verification result being verification failed, the output verification results are inconsistent. prompt information.

In some optional embodiments, the second processing unit 522 is specifically used to:

Based on the detection rules corresponding to the behavior model, detect the start position and end position of the content to be converted in the behavior model; based on the starting position and end position, determine the content to be converted in the behavior model; convert the content to be converted into For target content that meets the preset conditions of the target verification platform, a synthesized model corresponding to the behavioral model is obtained.

The beneficial technical effects corresponding to the exemplary embodiments of this device can be found in the corresponding beneficial technical effects in the above exemplary method section, and will not be described again here.

Example electronic device

FIG. 8 is a structural diagram of an electronic device provided by an embodiment of the present disclosure, including at least one processor 11 and a memory 12 .

The processor 11 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

Memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and/or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 11 may execute the one or more computer program instructions to implement the methods and/or other desired functions of the various embodiments of the disclosure above.

In one example, the electronic device 10 may further include an input device 13 and an output device 14, and these components are interconnected through a bus system and/or other forms of connection mechanisms (not shown).

The input device 13 may also include, for example, a keyboard, a mouse, and the like.

The output device 14 can output various information to the outside, which can include, for example, a display, a speaker, a printer, a communication network and its connected remote output devices, etc.

Of course, for simplicity, only some of the components in the electronic device 10 related to the present disclosure are shown in FIG. 8 , and components such as buses, input/output interfaces, etc. are omitted. In addition, the electronic device 10 may also include any other appropriate components depending on the specific application.

Example computer program products and computer-readable storage media

In addition to the above methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions. When executed by a processor, the computer program instructions cause the processor to perform the present invention described in the “Exemplary Method” section above. Steps in methods of various embodiments are disclosed.

The computer program product may have program code for performing operations of embodiments of the present disclosure written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and Includes conventional procedural programming languages, such as the "C" language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server execute on.

In addition, embodiments of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon. The computer program instructions, when executed by a processor, cause the processor to perform each of the steps of the present disclosure described in the "Exemplary Methods" section above. Steps in the method of an embodiment.

Computer-readable storage media can take the form of any combination of one or more computer-readable media. The readable medium may be a readable signal medium or a readable storage medium. Readable storage media include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or devices, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.

The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, the advantages, advantages, effects, etc. mentioned in the present disclosure are only examples and not limitations, and cannot be considered to be necessary for each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and to facilitate understanding, and are not limiting. The above details do not limit the present disclosure to be implemented by using the above specific details.

Various changes and modifications can be made to the present disclosure by those skilled in the art without departing from the spirit and scope of the application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present disclosure and its equivalent technology, the present disclosure is also intended to include these modifications and variations.

Claims (12)

1. A method of chip verification, comprising:

acquiring a physical unit library of a chip to be verified, wherein the physical unit library comprises behavior models corresponding to physical units of the chip to be verified;

converting the physical unit library into a synthesizable physical unit library; the comprehensive physical unit library comprises a comprehensive model meeting the preset conditions of the target verification platform; the synthesizable model is a model which is consistent with the behavior logic of the behavior model and can be synthesized into a netlist;

And verifying the chip to be verified through the target verification platform based on the synthesizable model in the synthesizable physical unit library to obtain a verification result.

2. The method of claim 1, wherein the converting the physical unit library into a synthesizable physical unit library comprises:

determining a conversion rule corresponding to a behavior model corresponding to any physical unit in the physical unit library based on identification information of the behavior model;

and converting the behavior model into a synthesizable model based on conversion rules corresponding to the behavior model.

3. The method of claim 2, wherein the determining the conversion rule corresponding to the behavior model based on the identification information of the behavior model includes:

determining a convertible state corresponding to the behavior model based on the identification information of the behavior model;

and responding to the convertible state as a first state, and determining a conversion rule corresponding to the behavior model based on the identification information.

4. A method according to claim 3, further comprising:

and responding to the convertible state as the second state, and outputting prompt information corresponding to the behavior model.

5. The method according to claim 4, wherein after outputting the prompt information corresponding to the behavior model, further comprising:

acquiring a conversion rule corresponding to the behavior model input by the user;

and converting the behavior model into a synthesizable model based on conversion rules corresponding to the behavior model.

6. The method of any of claims 2-5, wherein said converting said library of physical units into a synthesizable library of physical units further comprises:

obtaining an initial synthesizable physical cell library in response to completion of the conversion of the behavioral model in the physical cell library;

performing consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a consistency verification result corresponding to the initial synthesizable physical unit library;

and responding to the consistency verification result to meet a consistency condition, and taking the initial synthesizable physical unit library as the synthesizable physical unit library corresponding to the physical unit library.

7. The method of claim 6, wherein the performing consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a consistency verification result corresponding to the initial synthesizable physical unit library comprises:

Based on a pre-configured function consistency verification environment, performing function consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a first verification result;

based on a preconfigured form consistency verification environment, performing form consistency verification on the physical unit library and the initial synthesizable physical unit library to obtain a second verification result;

and determining the consistency verification result based on the first verification result and the second verification result.

8. The method of claim 7, wherein the determining the consistency verification result based on the first verification result and the second verification result comprises:

responding to the first verification result and the second verification result to pass verification, and determining that the consistency verification result meets the consistency condition;

and outputting prompt information of inconsistent verification results in response to any one of the first verification result and the second verification result being that verification is failed.

9. The method according to any one of claims 2-5, wherein the converting the behavior model into a synthesizable model based on the conversion rules corresponding to the behavior model comprises:

Detecting the starting position and the ending position of the content to be converted in the behavior model based on the detection rule corresponding to the behavior model;

determining the content to be converted in the behavior model based on the starting position and the ending position;

and converting the content to be converted into target content meeting the preset conditions of the target verification platform, and obtaining the synthesizable model corresponding to the behavior model.

10. A chip verification apparatus, comprising:

the acquisition module is used for acquiring a physical unit library of the chip to be verified, wherein the physical unit library comprises behavior models corresponding to all physical units of the chip to be verified;

the first processing module is used for converting the physical unit library into a synthesizable physical unit library; the comprehensive physical unit library comprises a comprehensive model meeting the preset conditions of the target verification platform; the synthesizable model is a model which is consistent with the behavior logic of the behavior model and can be synthesized into a netlist;

and the second processing module is used for verifying the chip to be verified through the target verification platform based on the synthesizable model in the synthesizable physical unit library to obtain a verification result.

11. A computer readable storage medium storing a computer program for executing the method of verification of a chip as claimed in any one of the preceding claims 1-9.

12. An electronic device, the electronic device comprising:

a processor;

a memory for storing the processor-executable instructions;

the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for verifying a chip according to any one of claims 1-9.