CN117347818A - A delay measurement method, device, system and interface circuit - Google Patents

Abstract

The application discloses a delay line delay measurement method, a delay line delay measurement device, a delay line delay measurement system and an interface circuit, wherein the delay line delay measurement method comprises the following steps: and acquiring a measurement mode of the delay line and a bit width of a delay control signal of the delay line, wherein the measurement mode is used for showing a target measurement time of the delay line, determining a pre-delay stage number of the delay control signal for controlling the delay line to realize delay according to the bit width, judging the coincidence of a delay output result under the action of the delay control signal corresponding to the pre-delay stage number and the target measurement time, and adjusting the pre-delay stage number of the delay control signal according to the coincidence until the delay output result under the action of the delay control signal corresponding to the pre-delay stage number coincides with the target measurement time, so as to obtain the delay stage number corresponding to the target measurement time. Thus, the measurement can be flexibly performed for different measurement modes, and the number of measurement turns is remarkably reduced.

Description

A delay measurement method, device, system and interface circuit

Technical field

The present application relates to the field of integrated circuit technology, and in particular to a delay measurement method, device, system and interface circuit.

Background technique

Delay lines are widely used in various interface circuits. For example, when SOC (system on chip) chips read data in DDR (Double Data Rate) memories, they need to use delay lines to separate DQS ( data strobe signal, data strobe signal) signal is delayed by 1/4 clock cycle. The delay time of the delay line has a linear positive correlation with dly_code (a set of multi-bit signals). Every time dly_code increases by 1, the delay time of the delay line increases by the delay of a delay unit (Dly_element). The step delay time of the delay line is the delay of a delay unit (Dly_element).

The delay time of the delay unit is related to the ambient temperature, voltage, etc. During the chip initialization phase, it is necessary to measure the delay time of the delay line equivalent to the target clock cycle, record the dly_code value corresponding to the equivalent delay time, and then set different dly_code values for the delay line to obtain the expected delay time. For example, the dly_code value corresponding to measuring the equivalent delay time of one clock cycle is 100, then the dly_code value corresponding to 1/4 clock cycle is 25.

Therefore, the target delay time cannot be accurately generated before the delay line delay time measurement is completed, so before using the delay line for delay, the delay measurement should be completed first, and the shorter the delay measurement time, the better. At the same time, the higher the accuracy of delay time measurement, the better.

Currently, the main solution used is to sample the clock after the reference clock delay, and use a fixed half cycle for measurement. However, if the duty cycle of the clock to be measured is not exactly 50%, the error in the measurement results will increase. Moreover, dly_code needs to be increased step by step during the measurement period, and the measurement time is very long.

Contents of the invention

Embodiments of the present application provide a delay measurement method, device, system and interface circuit.

According to a first aspect of the present application, a delay measurement method of a delay line is provided. The method includes: obtaining a measurement mode of the delay line and a bit width of a delay control signal of the delay line, and the measurement mode is used to Shows the target measurement time of the delay line; determines the pre-delay level of the delay control signal that controls the delay line to achieve delay according to the bit width; determines the role of the delay control signal corresponding to the pre-delay level The delay output result under is consistent with the target measurement time; adjust the pre-delay series of the delay control signal according to the compliance, until the delay output under the action of the delay control signal corresponding to the pre-delay series The result is consistent with the target measurement time, and a delay series corresponding to the target measurement time is obtained.

According to an embodiment of the present application, determining the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay according to the bit width includes: taking the median of the delay control signal according to the bit width. as the pre-delay level.

According to an embodiment of the present application, taking the median of the delay control signal as the pre-delay level includes: setting the highest position of the delay control signal as 1 and other positions as zero.

According to an embodiment of the present application, the delay output result is used to show the actual delay time under the action of the delay control signal corresponding to the delay level; accordingly, the judgment is made based on the delay control signal corresponding to the delay level. The conformity of the delay output result under the action of the signal with the target measurement time includes: judging the size relationship between the actual delay time and the target measurement time; the size relationship obtained in two adjacent delay series is opposite. In this case, it is determined that the delay output result is consistent with the target measurement time, and it is determined that the delay level of the delay control signal corresponding to the test with a smaller delay difference among the two adjacent tests is equal to the target measurement time. The delay series corresponding to time; where the delay difference is the difference between the actual delay time and the target measurement time.

According to an embodiment of the present application, the delay output result is used to show the actual delay time under the action of the delay control signal corresponding to the delay level; accordingly, the delay control signal is adjusted according to the compliance The pre-delay series includes: when the actual delay time is greater than the target measurement time, the dichotomy method is used to adjust the pre-delay series until the actual delay time obtained by two adjacent delay series is the same as the target measurement time. The relationship between the size of the above-mentioned target measurement time is opposite.

According to an embodiment of the present application, the adjustment of the pre-delay series using a dichotomy method includes: when the actual delay time is greater than the target measurement time, setting the position of the previous pre-delay series to 1 is zero, and other bits remain unchanged; when the actual delay time is less than the target measurement time, the bits set to 1 in the previous pre-delay series remain unchanged.

According to a second aspect of the present application, a delay measurement device for a delay line is also provided. The device includes: an acquisition module for acquiring the measurement mode of the delay line and the bit width of the delay control signal of the delay line. , the measurement mode is used to show the target measurement time of the delay line; the determination module is used to determine the pre-delay level of the delay control signal that controls the delay line to achieve delay according to the bit width; the judgment module , used to determine the compliance of the delay output result under the action of the delay control signal corresponding to the pre-delay series with the target measurement time; an adjustment module, used to adjust the pre-delay control signal according to the compliance Delay the series until the delay output result under the action of the delay control signal corresponding to the pre-delay series matches the target measurement time, and obtain the delay series corresponding to the target measurement time.

According to the third aspect of the present application, a delay measurement system for a delay line is also provided. The system includes: a file storage unit for receiving and storing control files and status files for delay measurement of the delay line; The detection circuit unit is used to perform delay detection on the delay line based on the status file when triggered by the measurement control unit, and send the delay output result; the measurement control unit is used to obtain the control file from the file storage unit, The delay detection circuit unit is triggered to perform delay detection, the delay output result is obtained from the delay detection circuit unit, and the status file is updated according to the delay output result.

According to an embodiment of the present application, the status file includes a measurement mode sub-file and a bit-width sub-file. The measurement mode sub-file is used to show the target measurement time of the delay line, and the bit-width sub-file is used to show The bit width of the delay control signal is output; accordingly, the measurement control unit updates the status file according to the delay output result, including: determining the delay control signal that controls the delay line to achieve delay according to the bit width. Pre-delay series; determine the compliance of the delay output result under the action of the delay control signal corresponding to the pre-delay series with the target measurement time; adjust the pre-delay series of the delay control signal according to the compliance , until the delay output result under the action of the delay control signal corresponding to the pre-delay series matches the target measurement time, and a delay series corresponding to the target measurement time is obtained.

According to a fourth aspect of the present application, an interface circuit that requires delay measurement is also provided, and the interface circuit includes the above delay measurement system.

The delay measurement method of the delay line in the embodiment of the present application obtains the measurement mode of the delay line and the bit width of the delay control signal of the delay line. The measurement mode is used to show the target measurement time of the delay line. According to the The above-mentioned bit width is used to determine the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay, and to determine whether the delay output result under the action of the delay control signal corresponding to the pre-delay stage is consistent with the target measurement time. property, and adjust the pre-delay series of the delay control signal according to the compliance, until the delay output result under the action of the delay control signal corresponding to the pre-delay series is consistent with the target measurement time, and the result is obtained as described The delay series corresponding to the target measurement time. In this way, measurements can be flexibly performed for different measurement modes. For example, measurements can be performed in 0.25T, 0.5T or 1T modes respectively. When the measurement mode is 1T mode, it is not affected by the clock duty cycle and the measurement results are more accurate. Further, the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay is determined based on the bit width, and based on the delay output result under the action of the delay control signal corresponding to the pre-delay stage and the target measurement time. The compliance adjustment of the pre-delay series of the delay control signal can significantly reduce the number of measurement rounds.

It should be understood that the teachings of the present application do not need to achieve all the beneficial effects mentioned above, but specific technical solutions can achieve specific technical effects, and other embodiments of the present application can also achieve beneficial effects not mentioned above. Effect.

Description of drawings

The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the application are shown by way of example and not by way of limitation, in which:

In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

Figure 1 shows a schematic diagram of the application scenario of the delay measurement method of the delay line of the present application according to the embodiment of the present application;

Figure 2 shows the timing diagram of the register sampling setup and hold times of DDR memory;

Figure 3 shows a schematic diagram of the circuit structure of the delay line;

Figure 4 shows a schematic circuit structure diagram of a delay unit of the delay line;

Figure 5 shows a schematic flow chart of the implementation of the delay measurement method of a delay line provided by an embodiment of the present application;

Figure 6 shows a schematic implementation flow diagram of a specific application example of the delay line delay measurement method provided by the embodiment of the present application;

Figure 7 shows a schematic structural diagram of a delay measurement device for a delay line provided by an embodiment of the present application;

Figure 8 shows a schematic structural diagram of a delay measurement system for a delay line provided by an embodiment of the present application;

Figure 9 shows a state transition diagram of the state machine of dly_ms_ctrl based on the delay measurement system shown in Figure 8;

Figure 10 is a delay measurement circuit of a delay line provided by an embodiment of this application;

Figure 11 shows a schematic waveform diagram of a delay line delay measurement example with a dly_code bit width of 8 and 1T mode.

Detailed ways

The principles and spirit of the present application will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement the present application, and are not intended to limit the scope of the present application in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The technical solution of the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

First, in order to better explain the solutions of the embodiments of the present application, the application scenarios of the embodiments of the present application are briefly described here. A delay line is a component or device used to delay electrical signals for a period of time. It is widely used in various interface circuits. For example, as shown in Figure 1, when the SoC (System on Chip) chip reads the data in the DDR memory, it needs to use a delay line to delay the DQS signal by 1/4 clock cycle. Figure 2 shows the timing diagram of the register sampling setup and hold time of the DDR memory. As shown in Figure 2, first, the DDR memory returns edge-aligned DQS and DQ[7:0] after receiving the read command sent by the SoC chip. In order to meet the setup and hold time of register sampling within the SoC, DQS needs to be delayed by 1/4 clock cycle to become DQS_dly, and then the rising edge and falling edge of DQS_dly are used to sample DQ[7:0] respectively to obtain DQ_pos and DQ_neg. At this time, a delay line is needed to delay the DQS signal.

Secondly, here is a brief explanation of the circuit structure of the delay line to explain the reasons for measuring the delay time of the delay line. The circuit structure of the delay line is shown in Figure 3. din is the signal that needs to be delayed; dout is the signal after delay; dly_code is a set of multi-bit signals used to control the delay size of the delay line. The delay line contains several delay units (Dly_element) and a decoder (delayline_decoder). When dly_code=0, en[n:0]='b0 generated by the decoder; when dly_code=1, en[n:0]='b1; when dly_code=2, en[n:0]= 'b11; When dly_code=3, en[n:0]='b111; and so on. Among them, the circuit structure of a delay unit is shown in Figure 4.

From the above analysis, it can be seen that the delay time of the delay line has a linear positive correlation with dly_code. Every time dly_code increases by 1, the delay time of the delay line increases by the delay time of a delay unit (Dly_element). The step delay time of the delay line is the delay time of a delay unit (Dly_element). The delay time of a delay unit is related to the ambient temperature, voltage, etc. of the delay line, and is a dynamically changing parameter. Therefore, during the chip initialization phase, it is necessary to measure the delay time of the delay line that is equivalent to the target clock cycle, record the dly_code value corresponding to the equivalent delay time, and then set different dly_code values for the delay line to obtain the expected delay time. For example, the dly_code value corresponding to measuring the equivalent delay time of one clock cycle T is 100. If you need to obtain the delay time of 1/4 clock cycle, the corresponding dly_code value is 25.

In view of this, an embodiment of the present application provides a delay measurement method for a delay line. FIG. 5 shows a schematic flow chart of the implementation of the delay measurement method of a delay line provided by an embodiment of the present application.

Referring to Figure 5, the delay measurement method of the delay line in the embodiment of the present application at least includes the following operation process: Operation 501, obtain the measurement mode of the delay line and the bit width of the delay control signal of the delay line. The measurement mode is used to show the delay line The target measurement time; operation 502, determine the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay according to the bit width; operation 503, determine the delay output result under the action of the delay control signal corresponding to the pre-delay stage and Compliance of the target measurement time; operation 504, adjust the pre-delay series of the delay control signal according to the compliance, until the delay output result under the action of the delay control signal corresponding to the pre-delay series is consistent with the target measurement time, and obtain the target measurement time Measure the delay level corresponding to the time.

In operation 501, a measurement pattern of a delay line and a bit width of a delay control signal of the delay line are acquired, the measurement pattern being used to show a target measurement time of the delay line.

In this embodiment of the present application, the measurement modes may include 0.25T, 0.5T, 1T, etc., where T represents one clock cycle of the delay line. The delay control signal can be represented by a set of binary digits, and its bit width is the number of bits in this binary digit.

The measurement mode of the delay line is obtained here. The purpose is to flexibly select the delay time of 0.25T, 0.5T or 1T for measurement according to actual needs. Specifically, when the signal transmission frequency of the interface circuit that needs to use a delay line is low frequency, such as 100M or 200M, and the maximum delay time of the delay line is less than 1T, the 0.5T measurement mode is used; when the interface circuit that needs to use a delay line When the signal transmission frequency is high frequency, for example: 1G, the maximum delay of the delay line is greater than 1T, use the 1T measurement mode. The selected 0.5T or 1T is called the target measurement time.

In operation 502, the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay is determined according to the bit width.

In this embodiment of the present application, according to the bit width, the median number of the delay control signal is taken as the pre-delay level, so as to determine the pre-delay level of the delay control signal that controls the delay line to achieve delay according to the bit width.

In this implementation of the present application, the following method can be used to achieve taking the median of the delay control signal as the pre-delay level: setting the highest position of the delay control signal as 1 and other positions as zero.

For example: the bit width of the delay control signal is 3, here you can directly take the delay stage as binary 100, that is, the pre-delay stage is 4.

Here, the pre-delay level means that the delay unit corresponding to the pre-delay level is connected to delay the line signal, and it is detected whether the actual delay time matches the target delay time.

In operation 503, it is determined whether the delay output result under the action of the delay control signal corresponding to the pre-delay stage is consistent with the target measurement time.

In this embodiment of the present application, the delay output result is used to show the actual delay time under the action of the delay control signal corresponding to the delay level. Correspondingly, the following operations can be used to determine the consistency of the delay output result under the action of the delay control signal corresponding to the delay stage and the target measurement time: determine the relationship between the actual delay time and the target measurement time, and determine the relationship between the actual delay time and the target measurement time. If the magnitude relationship obtained by the number is opposite, determine that the delay output result is consistent with the target measurement time, and determine that the delay level of the delay control signal corresponding to the test with a smaller delay difference between the two adjacent tests is the same as the target measurement time. The delay series corresponding to the time. Among them, the delay difference is the difference between the actual delay time and the target measurement time.

Here, by judging the consistency of the delay output result under the action of the delay control signal corresponding to the pre-delay stage and the target measurement time, the delay stage that best meets the target measurement time is determined.

In operation 504, the pre-delay series of the delay control signal is adjusted according to the compliance, until the delay output result under the action of the delay control signal corresponding to the pre-delay series is consistent with the target measurement time, and a value corresponding to the target measurement time is obtained. Delay level.

In this embodiment of the present application, the delay output result is used to show the actual delay time under the action of the delay control signal corresponding to the delay level. Correspondingly, the following operations can be used to adjust the pre-delay series of the delay control signal according to compliance: when the actual delay time is greater than the target measurement time, the dichotomy method is used to adjust the pre-delay series until the two adjacent delay series are obtained The actual delay time is inversely related to the target measurement time.

In this implementation of the present application, the use of the dichotomy method to adjust the pre-delay series can be achieved through the following operations: when the actual delay time is greater than the target measurement time, the position set to 1 in the previous pre-delay series is set to zero, The other bits remain unchanged. When the actual delay time is less than the target measurement time, the bit set to 1 in the previous pre-delay series remains unchanged.

In this way, the half-point method is used to gradually approach the target measurement time, effectively speeding up the measurement speed and shortening the measurement time.

FIG. 6 shows a schematic flowchart of an implementation example of a specific application example of the delay line delay measurement method provided by the embodiment of the present application.

Referring to Figure 6, a specific application example of the delay line delay measurement method provided by the embodiment of the present application includes at least the following operation process:

In this implementation of the present application, after determining the measurement mode of 0.25T, 0.5T or 1T mode according to the measurement mode, first according to the bit width of the delay control signal dly_code, the highest value is 1, and the other positions are 0. If the delay time of the line is greater than the target delay time, its highest bit remains unchanged, the second bit is 1, and the other bits are zero. The delay time until the delay line is no greater than the target delay time. The delay series corresponding to the smaller difference between the actual delay time and the target delay time in the last two measurement processes is taken as the final target delay series corresponding to the target delay time. It should be noted here that the target delay time here is consistent with the target measurement time concept above.

Therefore, if the dly_code bit width is n bit, the number of controlled delay line step levels is 2 to the nth power. Using the half-division method, in the process of measuring the delay line delay time, only n times of dly_code need to be traversed to obtain the measurement result. For example, the dly_code bit width corresponding to a 256-level delay unit is 8 bits, and the measurement result only needs to be traversed 8 times through dly_code. Compared with the existing technology that requires up to 256 traversals of dly_code to obtain the measurement results, the measurement time is effectively shortened.

The other specific implementation processes in Figure 6 are similar to the specific implementation processes of operations 501-504 in the embodiment shown in Figure 5, and will not be described again here.

The delay measurement method of the delay line in the embodiment of the present application obtains the measurement mode of the delay line and the bit width of the delay control signal of the delay line. The measurement mode is used to show the target measurement time of the delay line. According to the bit width, the control delay line is determined. Realize the pre-delay stages of the delayed delay control signal, determine the compliance of the delay output result under the action of the delay control signal corresponding to the pre-delay stage and the target measurement time, and adjust the pre-delay stage of the delay control signal according to the compliance number until the delay output result under the action of the delay control signal corresponding to the pre-delay series matches the target measurement time, and the delay series corresponding to the target measurement time is obtained. In this way, measurements can be flexibly performed for different measurement modes. For example, measurements can be performed in 0.25T, 0.5T or 1T modes respectively. When the measurement mode is 1T mode, it is not affected by the clock duty cycle and the measurement results are more accurate. Further, the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay is determined based on the bit width, and the delay control is adjusted based on the compliance of the delay output result under the action of the delay control signal corresponding to the pre-delay stage and the target measurement time. The pre-delay series of signals can significantly reduce the number of measurement rounds.

Similarly, based on the above delay line delay measurement method, embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium stores a program. When the program is executed by the processor, the processor at least executes The following operation steps: Operation 501, obtain the measurement mode of the delay line and the bit width of the delay control signal of the delay line. The measurement mode is used to show the target measurement time of the delay line; Operation 502, determine the control delay line implementation based on the bit width. The pre-delay series of the delayed delay control signal; Operation 503, determine the compliance of the delay output result under the action of the delay control signal corresponding to the pre-delay series with the target measurement time; Operation 504, adjust the delay control signal according to the compliance pre-delay series until the delay output result under the action of the delay control signal corresponding to the pre-delay series matches the target measurement time, and the delay series corresponding to the target measurement time is obtained.

Furthermore, based on the above delay line delay measurement method, embodiments of the present application also provide a delay line delay measurement device, as shown in Figure 7. The device 70 includes: an acquisition module 701, used to obtain the measurement mode of the delay line. and the bit width of the delay control signal of the delay line, the measurement mode is used to show the target measurement time of the delay line; the determination module 702 is used to determine the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay according to the bit width. ; Judgment module 703, used to determine the compliance of the delay output result under the action of the delay control signal corresponding to the pre-delay series with the target measurement time; Adjustment module 704, used to adjust the pre-delay series of the delay control signal according to compliance , until the delay output result under the action of the delay control signal corresponding to the pre-delay series matches the target measurement time, and the delay series corresponding to the target measurement time is obtained.

Furthermore, based on the above delay line delay measurement method, embodiments of the present application also provide a delay line delay measurement system, as shown in Figure 8. The system includes: a file storage unit reg_file, used to receive and Stores the control file and status file for delay measurement of the delay line; the delay detection circuit unit dly_ms is used to perform delay detection on the delay line based on the status file and send the delay output result when triggered by the measurement control unit; measurement control The unit dly_ms_ctrl is used to obtain the control file from the file storage unit, trigger the delay detection circuit unit to perform delay detection, obtain the delay output result from the delay detection circuit unit, and update the status file according to the delay output result.

In this embodiment of the present application, the status file includes a measurement mode sub-file and a bit-width sub-file. The measurement mode sub-file is used to show the target measurement time of the delay line, and the bit-width sub-file is used to show the bits of the delay control signal. width; correspondingly, the measurement control unit updates the status file according to the delay output result, including: according to the bit width, determining the pre-delay level of the delay control signal that controls the delay line to achieve delay; judging the delay control signal corresponding to the pre-delay level The delay output result under the action is consistent with the target measurement time; adjust the pre-delay series of the delay control signal according to the compliance, until the delay output result under the action of the delay control signal corresponding to the pre-delay series is consistent with the target measurement time , obtain the delay series corresponding to the target measurement time.

Here is the following explanation of the signals transmitted between each unit:

reg_access_bus: Interface signal for reading and writing registers inside reg_file.

dly_ms_start: When the user configuration register triggers delay time measurement, dly_ms_start will take effect (usually defined as 1 as a valid value and 0 as a non-valid value).

dly_code_upd: Instruction signal to update dly_code.

dly_code_upd_value: When dly_code_upd is valid, the dly_code register inside reg_file will be updated to the dly_code_upd_value value.

dly_ms_finish: Indicates the end of delay time measurement.

dly_ms_mode: Used to distinguish between 0.5T and 1T delay time measurement modes. For example, you can define dly_ms_mode equal to 0 as 1T measurement mode, and dly_ms_mode equal to 1 as 0.5T measurement mode.

dly_code: Controls the delay level of the delay line.

dly_ms_trig: Pulse signal. After receiving the dly_ms_trig pulse, dly_ms will measure the delay of the delay line corresponding to the current dly_code value.

dly_ms_result: The result of the current delay measurement. For example, a dly_ms_result of 0 means that the delay line delay time corresponding to the current dly_code value is greater than the target measurement time, and a dly_ms_result of 1 means that the delay line delay time corresponding to the current dly_code value is less than the target measurement time.

Furthermore, in this embodiment of the present application, the file registration unit reg_file is essentially a register file, which may include control registers and status registers required for delay measurement. Users can achieve the following goals by reading and writing reg_file: (1) Trigger the delay time measurement of the delay line; (2) Query whether the delay measurement is completed; (3) Query the delay time measurement result, that is, the dly_code value.

The measurement control unit dly_ms_ctrl is a control module that controls the delay line delay time measurement. Figure 9 shows the state transition diagram of the state machine of dly_ms_ctrl based on the delay measurement system shown in Figure 8.

specific:

DLY_MS_IDLE: idle state. When the user triggers the delay measurement through the configuration register file, dly_code is restored to the initial value 0, and the state machine jumps from the idle state to the DLY_MS_CODE_UPD state.

HALF_CODE_SET: This status will update the dly_code value according to the dichotomy. For example, the bit width of dly_code is n, that is, dly_code[n-1:0]. After triggering delay measurement, entering HALF_CODE_SET for the first time will set dly_code[n-1] to 1, and other bits of dly_code will remain unchanged from the initial value 0. Entering HALF_CODE_SET for the second time will set dly_code[n-2] to 1, and the other bits of dly_code will remain unchanged. By analogy, the nth time you enter HALF_CODE_SET sets dly_code[0] to 1, and the other bits of dly_code remain unchanged.

DLY_MS_WAIT_TRIG: Usually after the dly_code changes, the delay time of the delay line needs to wait for a period of time to stabilize. The specific waiting time can be selected according to the actual situation, or the user can configure the waiting time.

DLY_MS_TRIG: In this state, the control module will generate a pulse signal on the dly_ms_trig signal to notify the dly_ms module to perform delay measurement.

DLY_MS_WAIT_RESULT: Wait for the dly_ms module to return a valid dly_ms_result.

DLY_MS_CHECK_RESULT: If dly_ms_result is 0, it means that the delay time of the delay line corresponding to the current dly_code value is greater than the target measurement time. It is necessary to clear the dly_code set to 1 during the previous HALF_CODE_SET bit to 0. If dly_ms_result is 1, it means that the delay time of the delay line corresponding to the current dly_code value is less than the target measurement time, and the bit where dly_code is set to 1 during the previous HALF_CODE_SET remains 1 unchanged.

DLY_MS_FINISH: If all bits of dly_code are traversed and then enter this end status bit, the control module will generate a valid dly_ms_finish signal to the register module.

Figure 10 is a delay measurement circuit of a delay line provided by an embodiment of the present application. The interface circuit includes the above delay measurement system.

In this implementation of the present application, registers 1, 2, 3, 5 and 6 use the same clock clk_dly_ms, and the clock paths are of equal length. dly_ms_mode is 0 to select the 1T measurement mode, and the target measurement time is 1 clk_dly_ms clock cycle. dly_ms_mode is 1 to select the 0.5T measurement mode, and the target measurement time is 0.5 clk_dly_ms clock cycles. Register 2 uses falling edge sampling, and registers 1, 3, 4, 5, and 6 use rising edge sampling. Register 1 is responsible for sampling dly_ms_trig for one beat, and the sampling result is dly_ms_trig_r. dly_ms_trig_r passes through register 2, register 3, MUX_1 becomes trig_dly_0. dly_ms_trig_r changes to trig_dly1 through delay_line and MUX_0. Register 4 uses the rising edge of trig_dly0 to sample trig_dly1. Register 5 and register 6 are responsible for synchronizing the sampling results of register 4 to the clk_dly_ms clock domain. The function of MUX_0 is to offset the delay of MUX_1.

Figure 11 shows a schematic waveform diagram of a delay line delay measurement example with a dly_code bit width of 8 and 1T mode. From the waveform of the delay line delay measurement example of dly_code bit width 8 and 1T mode in Figure 11, we can see that the final measurement result is: dly_code[7:0]=8'b0111_1110 The delay of the corresponding delay line is closest to 1 clk_dly_ms clock cycle.

It should be pointed out here that the above description of the delay measurement device, system and interface circuit embodiments for the delay line is similar to the description of the method embodiments shown in Figures 1 to 6, and has the same features as the aforementioned Figures 1 to 6. The method embodiment shown in 6 has similar beneficial effects, so no further description is given. For technical details that are not disclosed in the embodiments of the delay measurement device, system and interface circuit of the delay line of this application, please refer to the description of the method embodiments shown in Figures 1 to 6 of this application. To save space, we will not Again.

It should be noted that, in this document, the terms "comprising", "comprises" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements, It also includes other elements not expressly listed or inherent in the process, method, article or apparatus. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or apparatus that includes that element.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be electrical, mechanical, or other forms. of.

The units described above as separate components may or may not be physically separated; the components shown as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, all functional units in the embodiments of the present application can be integrated into one processing unit, or each unit can be separately used as a unit, or two or more units can be integrated into one unit; the above-mentioned integration The unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

Those of ordinary skill in the art can understand that all or part of the steps to implement the above method embodiments can be completed through hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the execution includes: The steps of the above method embodiment; and the aforementioned storage media include: mobile storage devices, read-only memory (Read Only Memory, ROM), magnetic disks or optical disks and other various media that can store program codes.

Alternatively, if the integrated units mentioned above in this application are implemented in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of software products in essence or those that contribute to the existing technology. The computer software products are stored in a storage medium and include a number of instructions to A computer device (which may be a personal computer, a server, a network device, etc.) is caused to execute all or part of the methods of various embodiments of the present application. The aforementioned storage media include: mobile storage devices, ROMs, magnetic disks or optical disks and other media that can store program codes.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, and all of them should be covered. within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (10)

1. A delay measurement method for a delay line, the method includes: Obtain a measurement mode of the delay line and a bit width of the delay control signal of the delay line, where the measurement mode is used to show the target measurement time of the delay line; According to the bit width, determine the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay; Determine the consistency of the delay output result under the action of the delay control signal corresponding to the pre-delay series and the target measurement time; The pre-delay stages of the delay control signal are adjusted according to the compliance, until the delay output result under the action of the delay control signal corresponding to the pre-delay stage is consistent with the target measurement time, and the target measurement time is obtained. The delay level corresponding to the measurement time. 2. The method according to claim 1, determining the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay according to the bit width, including: According to the bit width, the median number of the delay control signal is taken as the pre-delay level. 3. The method according to claim 2, said taking the median of the delay control signal as the pre-delay level, including: Set the highest position of the delay control signal to 1 and other positions to zero. 4. The method according to claim 1, the delay output result is used to show the actual delay time under the action of the delay control signal corresponding to the delay series; accordingly, Determining the consistency of the delay output result under the action of the delay control signal corresponding to the delay series and the target measurement time includes: Determine the relationship between the actual delay time and the target measurement time; When the relationship between the magnitudes obtained by two adjacent delay stages is opposite, it is determined that the delay output result is consistent with the target measurement time, and the test with the smaller delay difference among the two adjacent tests is determined. The corresponding delay control signal delay level is the delay level corresponding to the target measurement time; The delay difference is the difference between the actual delay time and the target measurement time. 5. The method according to claim 1, the delay output result is used to show the actual delay time under the action of the delay control signal corresponding to the delay series; accordingly, The adjusting the pre-delay level of the delay control signal according to the compliance includes: When the actual delay time is greater than the target measurement time, the dichotomy method is used to adjust the pre-delay series until the actual delay time obtained by two adjacent delay series has an opposite relationship with the target measurement time. . 6. The method according to claim 5, said adjusting the pre-delay series using a dichotomy method, including: When the actual delay time is greater than the target measurement time, the position set to 1 in the previous pre-delay series is set to zero, and other bits remain unchanged; When the actual delay time is less than the target measurement time, the bit set to 1 in the previous pre-delay series remains unchanged. 7. A delay measurement device for a delay line, the device comprising: An acquisition module, configured to acquire the measurement mode of the delay line and the bit width of the delay control signal of the delay line, where the measurement mode is used to show the target measurement time of the delay line; A determination module configured to determine, according to the bit width, the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay; A judgment module, used to judge whether the delay output result under the action of the delay control signal corresponding to the pre-delay series is consistent with the target measurement time; an adjustment module, configured to adjust the pre-delay series of the delay control signal according to the compliance, until the delay output result under the action of the delay control signal corresponding to the pre-delay series is consistent with the target measurement time, Obtain the delay series corresponding to the target measurement time. 8. A delay measurement system for a delay line, the system comprising: The file storage unit is used to receive and store the control file and status file for delay measurement of the delay line; A delay detection circuit unit, configured to perform delay detection on the delay line based on the status file when triggered by the measurement control unit, and send the delay output result; A measurement control unit, configured to obtain the control file from the file storage unit, trigger the delay detection circuit unit to perform delay detection, obtain the delay output result from the delay detection circuit unit, and obtain the delay output result according to the Delayed output results update the state file. 9. The delay measurement system according to claim 8, the status file includes a measurement mode sub-file and a bit width sub-file, the measurement mode sub-file is used to show the target measurement time of the delay line, the bit width sub-file The wide subfile is used to show the bit width of the delay control signal; accordingly, The measurement control unit updates the status file according to the delayed output result, including: According to the bit width, determine the number of pre-delay stages of the delay control signal that controls the delay line to achieve delay; Determine the consistency of the delay output result under the action of the delay control signal corresponding to the pre-delay series and the target measurement time; The pre-delay stages of the delay control signal are adjusted according to the compliance, until the delay output result under the action of the delay control signal corresponding to the pre-delay stage is consistent with the target measurement time, and the target measurement time is obtained. Measure the delay level corresponding to the time. 10. An interface circuit that requires delay measurement, the interface circuit comprising the delay measurement system according to claim 8 or 9.