CN117335947B - Full duplex communication circuit, chip, electronic device and communication system - Google Patents
Full duplex communication circuit, chip, electronic device and communication system Download PDFInfo
- Publication number
- CN117335947B CN117335947B CN202311269398.4A CN202311269398A CN117335947B CN 117335947 B CN117335947 B CN 117335947B CN 202311269398 A CN202311269398 A CN 202311269398A CN 117335947 B CN117335947 B CN 117335947B
- Authority
- CN
- China
- Prior art keywords
- resistor
- full duplex
- communication circuit
- duplex communication
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004891 communication Methods 0.000 title claims abstract description 94
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 12
- 230000005540 biological transmission Effects 0.000 claims abstract description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000003190 augmentative effect Effects 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 235000019800 disodium phosphate Nutrition 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/30—Signalling arrangements; Manipulation of signalling currents
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Transceivers (AREA)
Abstract
The application provides a full duplex communication circuit, a chip, an electronic device and a communication system. The full duplex communication circuit comprises a current signal generating module, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a transmitting operational amplifier and a receiving operational amplifier, wherein: the current signal generation module is used for generating a current signal; the first end of the first resistor is connected with the output end of the current signal generating module and the first end of the third resistor, and the second end of the first resistor is connected with the input end of the transmission operational amplifier and the first end of the second resistor; the second end of the second resistor is connected with the output end of the transmission operational amplifier and the first end of the fourth resistor; the second end of the third resistor is connected with the second end of the fourth resistor, the first end of the fifth resistor and the input end of the receiving operational amplifier; the second end of the fifth resistor is connected with the output end of the receiving operational amplifier. The full duplex communication circuit is capable of canceling echo interference.
Description
Technical Field
The application belongs to the technical field of communication, and relates to a communication circuit, in particular to a full duplex communication circuit, a chip, electronic equipment and a communication system.
Background
In modern communication systems, full duplex communication (Full-Duplex Communication) technology has become increasingly important. Full duplex communication allows the communication device to simultaneously transmit and receive data, improving communication efficiency and instantaneity. Full duplex communication technology has found application in many areas, such as mobile communications, satellite communications, wireless local area networks, communication base stations, and the like. However, when implementing full duplex communication, a common problem is echo interference (Echo Interference), which can negatively impact communication quality and performance.
Disclosure of Invention
The purpose of the application is to provide a full duplex communication circuit, a chip, an electronic device and a communication system, which are used for solving the problem of echo interference in full duplex communication.
In a first aspect, embodiments of the present application provide a full duplex communication circuit including a current signal generating module, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a transmitting operational amplifier, and a receiving operational amplifier, wherein: the current signal generation module is used for generating a current signal; the first end of the first resistor is connected with the output end of the current signal generation module and the first end of the third resistor, and the second end of the first resistor is connected with the input end of the transmission operational amplifier and the first end of the second resistor; the second end of the second resistor is connected with the output end of the transmission operational amplifier and the first end of the fourth resistor; the second end of the third resistor is connected with the second end of the fourth resistor, the first end of the fifth resistor and the input end of the receiving operational amplifier; the second end of the fifth resistor is connected with the output end of the receiving operational amplifier; the third resistor has a resistance value much greater than the first resistor, and the ratio of the resistance values of the second resistor and the fourth resistor is the same as the ratio of the resistance values of the first resistor and the third resistor.
In one implementation of the first aspect, the current signal generation module includes a current-mode digital-to-analog converter.
In one implementation of the first aspect, the full duplex communication circuit is applied in an ethernet communication network.
In one implementation manner of the first aspect, the resistance value R3 of the third resistor and the resistance value R1 of the first resistor satisfy the following conditions: r3> n R1, where n is greater than 50.
In one implementation manner of the first aspect, the signal input at the first end of the third resistor is vtx_replica, the signal input at the first end of the fourth resistor is vrx+vtx, where vtx_replica=idac×r1, idac is a current value of the current signal, R1 is a resistance value of the first resistor, vrx is a voltage signal received by the full duplex communication circuit, and Vtx is a voltage signal sent by the full duplex communication circuit.
In one implementation of the first aspect, the full duplex communication circuit is configured to transmit and receive differential signals.
In a second aspect, embodiments of the present application provide a chip comprising a full duplex communication circuit according to any one of the first aspects of embodiments of the present application.
In a third aspect, embodiments of the present application provide an electronic device comprising a full duplex communication circuit according to any one of the first aspects of embodiments of the present application.
In a fourth aspect, embodiments of the present application provide a communication system comprising a first communication device and a second communication device, the first communication device and/or the second communication device comprising a full duplex communication circuit according to any one of the first aspects of embodiments of the present application.
The full duplex communication circuit provided by the embodiment of the application comprises a current signal generating module, a resistor, a transmitting operational amplifier and a receiving operational amplifier. By reasonably configuring the connection relation between the modules and the devices and the parameter values of the related devices, the echo in the output signal of the receiving operational amplifier can be eliminated, so that the communication quality is improved.
Drawings
Fig. 1 is a schematic diagram of an ethernet communication system according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a full duplex communication circuit according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a chip according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Description of element reference numerals
1. Full duplex communication circuit
11. First resistor
12. Second resistor
13. Third resistor
14. Fourth resistor
15. Fifth resistor
16. Current signal generation module
17. Transmission operational amplifier
18. Receiving operational amplifier
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some of the embodiments of the present application, but not all of the embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure. Accordingly, the following detailed description of the embodiments of the present application, provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the apparatus or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In this application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The embodiment of the application provides a full duplex communication circuit, which can be applied to electronic equipment. The electronic device according to the embodiment of the application may include a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (augmented reality, AR)/Virtual Reality (VR) device, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (personal digital assistant, PDA) and other terminal devices, and may also be applied to a database, a server and a service response system based on terminal artificial intelligence.
For example, the electronic device may be a Station (ST) in a WLAN (Wireless Local Area Network ), may be a cellular telephone, a cordless telephone, a Session initiation protocol (Session InitiationProtocol, SIP) telephone, a wireless local loop (WirelessLocal Loop, WLL) station, a personal digital processing (Personal Digital Assistant, PDA) device, a handheld device with wireless communication capabilities, a computing device or other processing device connected to a wireless modem, a computer, a laptop computer, a handheld communication device, a handheld computing device, and/or other devices for communicating over a wireless system, as well as next generation communication systems, such as a mobile terminal in a 5G network, a mobile terminal in a future evolved public land mobile network (PublicLand Mobile Network, PLMN), or a mobile terminal in a future evolved Non-terrestrial network (Non-terrestrial Network, NTN), etc.
The electronic device described in the embodiments of the present application may be used as a device in an Ethernet (Ethernet) communication system. Ethernet is a data link layer based local area network (Local Area Network, LAN) communication protocol that specifies data frame formats, frame transmission modes, frame processing rules, and physical layer characteristics between devices to achieve reliable data communication.
In some implementations, the ethernet communication system may employ a full duplex mode, and the upstream data and downstream data of the device may be transmitted and received simultaneously using the same bandwidth. Fig. 1 shows a schematic diagram of a communication between two devices in an ethernet communication system, the two devices communicating in a full duplex mode. As shown in fig. 1, for either device, it contains a transmitter (Tx) and a receiver (Rx). The transmitter has an embedded termination resistance Rterm whose impedance matches the channel impedance, for example 50 ohms. The receiver receives two parts of data, one from the physical layer (PHY) in which it is communicating and the other from the data sent by the transmitter, which results in echo interference in the signal received by the receiver. In particular, in the case of a long channel, echo interference is particularly serious because the amplitude of the signal received by the receiver is small and the amplitude of the signal transmitted by itself is large after a large amplitude signal attenuation.
At least in view of the foregoing, embodiments of the present application provide a full duplex communication circuit, which includes a current signal generating module, a resistor, a transmitting operational amplifier, and a receiving operational amplifier. By reasonably configuring the connection relation between the modules and the devices and the parameter values of the related devices, the echo in the output signal of the receiving operational amplifier can be eliminated, so that the communication quality is improved.
Fig. 2 is a schematic diagram of a full duplex communication circuit 1 according to an embodiment of the present application. As shown in fig. 2, the full duplex communication circuit 1 includes a first resistor 11, a second resistor 12, a third resistor 13, a fourth resistor 14, a fifth resistor 15, a current signal generation module 16, a transmission operational amplifier 17, and a reception operational amplifier 18. Wherein the resistance value of the third resistor 13 is much larger than the resistance value of the first resistor 11. The ratio of the resistance values of the second resistor 12 and the fourth resistor 14 is the same as or similar to the ratio of the resistance values of the first resistor 11 and the third resistor 13.
The current signal generation module 16 is configured to generate a current signal Idac. Since the resistance value of the third resistor 13 is much larger than that of the first resistor 11, most of Idac flows into the first resistor 11, and only a very small portion flows into the third resistor 13.
The first terminal of the first resistor 11 is connected to the output of the current signal generating module 16 and to the first terminal of the third resistor 13. The second terminal of the first resistor 11 is connected to the input of the transmit op-amp 17 and to the first terminal of the second resistor 12. The second terminal of the second resistor 12 is connected to the output of the transmit op-amp 17 and to the first terminal of the fourth resistor 14. The second terminal of the third resistor 13 is connected to the second terminal of the fourth resistor 14, the first terminal of the fifth resistor 15 and the input terminal of the receiving operational amplifier 18. A second terminal of the fifth resistor 15 is connected to the output of the receive op-amp 18.
In some possible implementations, the transmit op-amp 17 is in closed loop mode, with an output impedance Rterm.
In some possible implementations, the Current signal generation module 16 may be a Current digital-to-analog converter (Current DAC) for converting a digital signal into an analog output of the Current signal.
In the embodiment of the present application, the resistance value of the third resistor 13 is far greater than the resistance value of the first resistor 11, so as to ensure that most of Idac flows into the first resistor 11, but only a small part flows into the third resistor 13, and thus the voltage across the first resistor 11 is approximately r1×idac. As long as the resistance values of the third resistor 13 and the first resistor 11 can achieve the above object, the resistance value of the third resistor 13 can be considered to be much larger than the resistance value of the first resistor 11.
In some possible implementations, the resistance value R3 of the third resistor and the resistance value R1 of the first resistor satisfy the following conditions: r3> n R1, where n is a number greater than 50. Preferably, n is a number greater than 100. Further preferably, n is a number greater than 1000.
In some possible implementations, the signal input at the first end of the third resistor is vtx_reply. The signal input by the first end of the fourth resistor is Vrx+Vtx. Where vtx_replica=idac×r1, idac is a current value of the current signal, and R1 is a resistance value of the first resistor. Vrx is the voltage received by the full duplex communication circuit and is a useful signal. Vtx is the voltage sent by the full duplex communication circuit and belongs to the echo interference signal. The potentials of the input terminals of the transmission operational amplifier 17 and the reception operational amplifier 18 are fixed values, and may be, for example, 0. The transmit op-amp 17 has a relatively high input impedance and thus it can be considered that Idac mostly flows into the second resistor 12 and only a very small portion flows into the transmit op-amp 17, the voltage tx=idac×r2 across the second resistor 12. The receiving operational amplifier 17 has a high input impedance, so that it can be considered that a substantial part of the current flows into the fifth resistor 15 and only a small part flows into the receiving operational amplifier 18. As can be seen from this, the output voltage of the receiving operational amplifier 18 is vout= (vrx+vtx) × (R5/R4) -vtx_replica× (R5/R3) =vrx× (R5/R4), where R1 to R5 are the resistance values of the first resistor 11 to the fifth resistor R5, respectively. Thus, only the signal Vrx received by the full duplex communication circuit 1 appears in the output voltage Vout of the receiving operational amplifier 18, the echo signal Vtx having been cancelled from Vout.
As can be seen from the above description, the full duplex communication circuit 1 provided in the embodiment of the present application includes the first resistor 11 to the fifth resistor 15, the current signal generating module 16, the transmitting operational amplifier 17, and the receiving operational amplifier 18. By reasonably configuring the resistance values of the resistors and the connection relation between different devices, the embodiment of the application only includes the signal Vrx in the output voltage Vout of the receiving operational amplifier 18, and eliminates the echo signal Vtx.
The embodiment of the application also provides a chip which comprises at least part of circuit devices in the full duplex communication circuit. For example, the chip contains all of the full duplex communication circuitry. Chips may be represented as commercially available active devices that package full duplex communication circuits fabricated on a wafer using semiconductor technology; or as a commercially available active device that encapsulates the full duplex communication circuit using PCB encapsulation technology. Referring to fig. 3, a schematic diagram of the packaging of a chip in one possible implementation is shown. As shown in fig. 3, the chip includes a first pin for receiving signals, a second pin for transmitting signals, a third pin for connecting to power and/or ground, and so on.
The embodiment of the application also provides electronic equipment, which comprises the full duplex communication circuit provided by the embodiment of the application.
In some possible implementations, the electronic device may also include a memory and a processor. The memory is used for storing a computer program. In some possible implementations, the memory may include: various media capable of storing program codes, such as ROM, RAM, magnetic disk, U-disk, memory card, or optical disk.
In embodiments of the present application, the memory may include computer system readable media in the form of volatile memory, such as RAM and/or cache memory. The electronic device may further include other removable/non-removable, volatile/nonvolatile computer system storage media. The memory may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the embodiments of the present application.
The processor is connected with the memory and is used for executing the computer program stored in the memory so as to enable the electronic device to execute the corresponding method.
In some embodiments, the processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), or the like. In other embodiments, the processor may also be a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.
In some possible implementations, the electronic device provided in the embodiments of the present application may further include a display. A display is in communication with the memory and the processor for displaying an associated graphical user interface (Graphical User Interface, GUI).
In an embodiment of the present application, the display may include a display screen (display panel). In some implementations, the display panel may be configured in the form of a liquid crystal display (Liquid Crystal Display, LCD), an Organic Light-Emitting Diode (OLED), or the like. In addition, the display may also be a touch panel (touch screen ), which may include a display screen and a touch sensitive surface. When the touch-sensitive surface detects a touch operation thereon or thereabout, it is communicated to the processor to determine the type of touch event, and the processor then provides a corresponding visual output on the display device based on the type of touch event.
The embodiment of the application also provides a communication system which at least comprises the first communication device and the second communication device. The first communication device and/or the second communication device comprise the full duplex communication circuit provided by the embodiment of the application.
It should be noted that, the above division of modules is only a division of logic functions, and may be fully or partially integrated into one physical entity or may be physically separated. And these modules may all be implemented in software in the form of calls by the processing element; or can be realized in hardware; the method can also be realized in a form of calling software by a processing element, and the method can be realized in a form of hardware by a part of modules. For example, the x module may be a processing element that is set up separately, may be implemented in a chip of the apparatus, or may be stored in a memory of the apparatus in the form of program code, and the function of the x module may be called and executed by a processing element of the apparatus. The implementation of the other modules is similar. In addition, all or part of the modules can be integrated together or can be independently implemented. The processing element described herein may be an integrated circuit having signal processing capabilities.
In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in a software form. For example, the modules above may be one or more integrated circuits configured to implement the methods above, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (Digital Singnal Processor, DSPs), or one or more field programmable gate arrays (Field Programmable Gate Array, FPGAs), etc. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (CentralProcessing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a System-On-a-Chip (SOC).
The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.
Claims (9)
1. A full duplex communication circuit comprising a current signal generation module, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a transmit operational amplifier, and a receive operational amplifier, wherein:
the current signal generation module is used for generating a current signal;
the first end of the first resistor is connected with the output end of the current signal generation module and the first end of the third resistor, and the second end of the first resistor is connected with the input end of the transmission operational amplifier and the first end of the second resistor;
the second end of the second resistor is connected with the output end of the transmission operational amplifier and the first end of the fourth resistor;
the second end of the third resistor is connected with the second end of the fourth resistor, the first end of the fifth resistor and the input end of the receiving operational amplifier;
the second end of the fifth resistor is connected with the output end of the receiving operational amplifier;
the resistance value of the third resistor is far larger than that of the first resistor, and the ratio of the resistance values of the second resistor and the fourth resistor is the same as that of the first resistor and the third resistor;
the signal input at the first end of the third resistor is vtx_replica, the signal input at the first end of the fourth resistor is vrx+vtx, the output voltage of the receiving operational amplifier is vout= (vrx+vtx) × (R5/R4) -vtx_replica× (R5/R3) =vrx× (R5/R4), where Vrx is the voltage signal received by the full duplex communication circuit, vtx is the voltage signal sent by the full duplex communication circuit, R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, and R5 is the resistance value of the fifth resistor.
2. The full duplex communication circuit according to claim 1, wherein the current signal generation module comprises a current mode digital to analog converter.
3. The full duplex communication circuit according to claim 1, wherein the full duplex communication circuit is used in an ethernet communication network.
4. The full duplex communication circuit according to claim 1, wherein the resistance value R3 of the third resistor and the resistance value R1 of the first resistor satisfy the following condition: r3> n R1, where n is greater than 50.
5. The full duplex communication circuit according to claim 1, wherein vtx_replica = Idac x R1, idac is a current value of the current signal, and R1 is a resistance value of the first resistor.
6. The full duplex communication circuit according to claim 1, wherein the full duplex communication circuit is configured to transmit and receive differential signals.
7. A chip comprising the full duplex communication circuit of any one of claims 1 to 6.
8. An electronic device comprising the full duplex communication circuit of any of claims 1 to 6.
9. A communication system comprising a first communication device and a second communication device, the first communication device and/or the second communication device comprising the full duplex communication circuit of any of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311269398.4A CN117335947B (en) | 2023-09-28 | 2023-09-28 | Full duplex communication circuit, chip, electronic device and communication system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311269398.4A CN117335947B (en) | 2023-09-28 | 2023-09-28 | Full duplex communication circuit, chip, electronic device and communication system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117335947A CN117335947A (en) | 2024-01-02 |
| CN117335947B true CN117335947B (en) | 2024-04-02 |
Family
ID=89291150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311269398.4A Active CN117335947B (en) | 2023-09-28 | 2023-09-28 | Full duplex communication circuit, chip, electronic device and communication system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117335947B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7106235B1 (en) * | 2005-05-31 | 2006-09-12 | Semiconductor Co., Ltd. | Active hybrid circuit for a full duplex channel |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8027377B2 (en) * | 2006-08-14 | 2011-09-27 | Intersil Americas Inc. | Differential driver with common-mode voltage tracking and method |
| TWI339513B (en) * | 2006-12-21 | 2011-03-21 | Realtek Semiconductor Corp | Passive echo cancellation device and signal transmission method thereof |
| CN107113023B (en) * | 2014-05-20 | 2020-12-29 | 美国莱迪思半导体公司 | Echo cancellation for high speed full duplex data transmission |
| US11405044B2 (en) * | 2020-11-12 | 2022-08-02 | Avago Technologies International Sales Pte. Limited | System for and method of cancelling a transmit signal echo in full duplex transceivers |
-
2023
- 2023-09-28 CN CN202311269398.4A patent/CN117335947B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7106235B1 (en) * | 2005-05-31 | 2006-09-12 | Semiconductor Co., Ltd. | Active hybrid circuit for a full duplex channel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117335947A (en) | 2024-01-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10033431B2 (en) | Training optimization of multiple lines in a vectored system using a prepared-to-join group | |
| US5483576A (en) | Method and apparatus for communicating data over a radio transceiver with a modem | |
| CN112533291B (en) | A resource scheduling method and related equipment | |
| CN109565291A (en) | It is tuned by the centre frequency and Q of the biquadratic filter of the calibration based on amplitude limiting oscillation | |
| TW201021456A (en) | Method and system for transmit diversity for chip-to-chip communications | |
| CN117335947B (en) | Full duplex communication circuit, chip, electronic device and communication system | |
| EP3665777A1 (en) | Integrated circuit with clock distribution | |
| CN112673664B (en) | Channel information processing method, device and storage medium | |
| CN105429693B (en) | Satellite mobile terminal | |
| CN109802815A (en) | The method and communication device of instruction | |
| CN209170677U (en) | A broadband ad hoc network device based on mobile network access | |
| US7454229B2 (en) | Electronic apparatus and wireless communication terminal | |
| CN218275054U (en) | A satellite antenna transceiver module and mobile terminal | |
| US20060268833A1 (en) | Mobile to mobile and voice over internet protocol communication system and apparatus | |
| CN112715009B (en) | Indication method, communication device and storage medium of precoding matrix | |
| CN117595972A (en) | Physical layer configuration indication method and related devices | |
| CN117836785A (en) | Model generation method and device | |
| US8805438B2 (en) | Analog baseband interface for communication systems | |
| WO2015062363A1 (en) | Anti-interference method and apparatus for fixed wireless terminal | |
| CN115915187A (en) | Data transmission method and related device | |
| WO2011049692A1 (en) | Enhanced calibration for multiple signal processing paths in a frequency division duplex system | |
| CN201557261U (en) | A remote access device based on WIFI standard | |
| CN118632250B (en) | Terminal authentication method for 5G terminal zero trust security | |
| KR20010018110A (en) | Device for LAN Data Transmission | |
| US12431941B2 (en) | Transmission configuration method and apparatus for multiple transmission and reception points (TRPs) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |