CN1172364C - Method for integrating antireflection layer and metal silicide block - Google Patents

Abstract

A method for integrating an anti-reflective layer with a self-aligned silicide block, comprising: providing a substrate which can be at least divided into a detector region and a transistor region, wherein the detector region at least comprises a doped region, and the transistor region at least comprises a transistor formed by a grid electrode, a source electrode and a drain electrode; forming a composite layer on the substrate, wherein the composite layer covers the doped region and the transistor at the same time and is used for increasing the reflectivity of light rays entering the composite layer from the doped region; removing part of the composite layer by an etching process to ensure that the top of the grid, the source and the drain are not covered by the composite layer; and performing a self-aligned silicide process to form metal silicide on the top of the gate, the source and the drain. The method is mainly characterized in that the composite layer can be simultaneously used as an anti-reflection layer of a detector area and a self-aligned silicide block of a transistor area, wherein the composite layer is formed by alternately overlapping a plurality of base layers, and the refractive indexes of the adjacent base layers are different.

Description

Method of integrating anti-reflection layer with metal silicide block

The present invention relates to a method for integrating an anti-reflection layer and a self-aligned salicide block, especially a method for simplifying the manufacturing process of a light detection element.

With the advancement of semiconductor technology and the increasing demand for small-sized components in the market, the importance of miniature high-function components that integrate many different functional units in one chip is becoming more and more important. For example, photodiodes (photodiodes) and Transistor light detection element. However, since any unit with a specific function has its specific structure and manufacturing process, when integrating many units with different functions, it often encounters the problem of incompatible manufacturing processes, especially when a unit When it is obviously more complicated (such as CMOS). The most common solution is to divide the entire component (chip) into several parts, and different parts are manufactured separately (that is, when a part is processed, other parts are covered with photoresist, etc. ), however, this approach will inevitably encounter defects such as increased manufacturing time and increased consumption of reactants.

As far as the photodetection elements commonly used in digital cameras and scanners are concerned, the basic structural diagram shown in FIG. Area (transistor area) 12 two parts. There are a plurality of insulating layers 102 on the substrate 10, there are some doped regions 101 separated from each other by the insulating layers 102 in the detector region 11, and there are some doped regions 101 separated by the gate 121 and the source 122 in the transistor region 12. , a transistor composed of the drain 123 and the spacer 124 , and the metal silicide 125 is located on the gate 121 , the source 122 and the drain 123 . In addition, the dielectric layer 13 is located on the substrate 10 and covers all the aforementioned structures, the multiple interconnection line 14 is located on the dielectric layer 13 and can be further connected to each transistor, and the cover layer 15 is located on the dielectric layer 13 and completely covers the Multiple interconnects 14 are located, and filters 16 are located on the cover layer 15 within the detector area 11 . In addition, since the optical filter 16 is used to allow light of a specific wavelength to directly project on a specific doped region 101, there is not only one optical filter 16 on any doped region 101, but also Except for the wires at the edge of 11 , there will not be any opaque structures (such as multiple interconnects 14 ) between any doped region 101 and the corresponding optical filter 16 .

In any case, in the detector region 11, part of the light incident on the doped region 101 through the optical filter 16 will be reflected, and since the incident light is not always vertically incident, the reflected light is possible in any direction . Apparently, if the reflected light is reflected by the opaque multiple interconnection lines 14, the different doped regions 101 may interfere with each other, resulting in a so-called crosstalk phenomenon. That is, none of the doped regions 101 can distinguish whether the received light comes directly from the corresponding filter 16 or is noise from the multiple interconnection lines 14 . Therefore, as shown in FIG. 1B , it is necessary to form an anti-reflection layer 17 on each doped region 101 before forming the dielectric layer 13, so as to ensure that the light reflected from any doped region will be reflected back without interfering with each other. . Generally, the material of the anti-reflection layer 17 is titanium nitride, titanium or tungsten-titanium compound.

In addition, the importance of the metal suicide 125 in the transistor region 12 increases with scaling. However, since the metal silicide 125 does not need to be formed in the entire transistor region 12, it is necessary to form a self-aligned silicide block 18 on the substrate 10 and cover all unnecessary parts in the transistor region 12 before forming the metal silicide 125. The region where the metal silicide 125 is formed, as shown in FIG. 1B , can then enter the process of forming the metal silicide. Generally speaking, the material of the self-aligned silicide block 18 must be a material that does not react with metals, such as TETRAETHYL-ORTHOSILICATE (TEOS).

It can be seen from the previous discussion that since the materials of the anti-reflection layer 17 and the self-aligned silicide block 18 are different, although the doped region 101 and the insulating layer 102 of the two regions can be formed together to simplify the manufacturing process, the subsequent The following manufacturing processes need to be performed in the two regions separately, and the manufacturing processes of the two regions cannot be combined until the metal silicide 125 is formed. In any case, it can be seen from FIG. 1B that the two regions basically cannot be merged in the manufacturing process only due to the completely different structure of the gate 121 manufacturing process, the metal silicide 125 manufacturing process and the optical filter 16 manufacturing process. Therefore, how to integrate the manufacturing processes of the anti-reflection layer 17 and the self-aligned silicide block becomes an important key to simplify the manufacturing process of the light detection element and reduce the process cost.

The main purpose of the present invention is to provide a method that can integrate the manufacturing process of the anti-reflection layer and the manufacturing process of the self-aligned silicide block.

Another object of the present invention is to provide a method for simultaneously forming an anti-reflection layer and self-aligning silicide blocks.

The object of the present invention also includes forming the anti-reflection layer and the self-aligned silicide block with the same material, so that both the anti-reflection layer and the self-aligned silicide block can be formed simultaneously.

Another object of the present invention is to provide a method for forming an anti-reflection layer and self-aligned silicide blocks that can be practically applied in a production line.

Another object of the present invention is to provide a method for forming a light detection element, wherein the anti-reflection layer for preventing cross-interference between different pixels (pixels) and the self-aligned silicide block for determining the position of the metal silicide are one And formed, thereby simplifying the manufacturing process and improving production efficiency.

The preferred embodiment proposed by the present invention includes at least the following steps: providing a substrate that can be divided into at least a detector region and a transistor region, wherein the detector region includes at least a doped region and the transistor region includes at least a gate, a source The transistor formed with the drain; form a composite layer on the substrate, this composite layer covers the doped region and the transistor at the same time, and can increase the reflectivity of light entering the composite layer from the doped region; by etching (photolithography) The process removes part of the composite layer so that the top of the gate, the source and the drain are not covered by the composite layer; and performs a self-aligned silicide process to form a metal silicide on the top of the gate, the source with the drain above.

Furthermore, when this embodiment is specifically applied to forming photodetection elements, the following steps are further included: removing the remaining reactants in the self-aligned silicide process; forming multiple multiple interconnections between these transistors and these isolation Above the layer, these multiple interconnects are located above the composite layer; cover the substrate with a dielectric layer, and complete the covering of these doped regions and these multiple interconnects; and form a plurality of optical filters on the dielectric layer , wherein the filters are located above the doped regions.

Apparently, the main feature of the present invention is that the composite layer is simultaneously used as the anti-reflection layer of the detector region and the self-aligned silicide block of the transistor region, so after the doped region and the transistor are formed, the detector region and The fabrication process for the transistor area is consolidated. The composite layer is formed by interlacing and stacking multiple base layers, wherein the refractive index of several adjacent base layers is different to change the direction of incident light, and the metal used to form the metal silicide will not adhere to the composite layer.

First of all, the inventor of the present invention pointed out that the self-aligned silicide block is used to prevent the metal used to form the metal silicide from adhering to the area on the substrate where the metal silicide does not need to be formed, so its material can be made of a dielectric Such as tetraethylorthosilicate. Relatively, the anti-reflection layer is used to reduce the reflection intensity of the light incident on the substrate, so the selection condition of the anti-reflection layer material should be focused on its reflectivity to the incident light from the substrate (preferably total reflection to completely eliminate the possibility of interference).

Next, the inventors of the present invention propose a breakthrough point to solve this problem: Since the dielectric layer generally used to form the self-aligned silicide block is a light-transmitting material with a certain refractive index, it is possible to utilize optically high light The concept that total reflection may occur when a material with a refractive index is incident on a material with a low refractive index, it can be reasonably inferred that if more than one layer of dielectrics with different refractive indices are stacked to form a composite layer, the composite layer may reflect light in a specific direction. The incident light is completely reflected back, that is, it can be used as an anti-reflection layer. In other words, the inventors of the present invention pointed out that by stacking a plurality of dielectric layers into a composite layer capable of total reflection, the anti-reflection layer can be formed from a material that forms a self-aligned silicide block, thereby At the same time, the anti-reflection layer can change the direction of light propagation and self-align the silicide block with proper insulating metal and part of the substrate, that is, the anti-reflection layer manufacturing process and the self-alignment silicide block manufacturing process can be integrated.

1A to 1B are schematic diagrams for explaining the positions and functions of the anti-reflection layer and the self-aligned silicide blocks; and

2A to 2G are a series of cross-sectional schematic diagrams for explaining the basic steps of a preferred embodiment of the present invention.

Labels of main parts:

10 substrates

101 doped area

102 insulating layer

11 detector area

12 Transistor Regions

121 grid

122 source

123 drain

124 spacers

125 Metal Silicide

13 dielectric layer

14 multiple internal connections

15 overlays

16 filters

20 substrates

201 insulating layer

21 detector area

22 transistor area

23 doped area

241 grid

242 source

243 drain

244 gap wall

25 composite layers

26 metal silicides

27 first dielectric layer

28 multiple internal connections

29 second dielectric layer

295 filter

The following will use a preferred embodiment of the present invention, a method for integrating an anti-reflection layer and a self-aligned silicide block, to specifically introduce the main content of the present invention. Please refer to the basic steps depicted in FIG. 2A to FIG. 2D :

As shown in FIG. 2A , a substrate 20 is provided, and the substrate 20 can be at least divided into a detector region 21 and a transistor region 22, wherein the detector region 21 includes at least a doped region 23 and the transistor region 22 includes at least a gate 241, a source The transistor formed by the pole 242 , the drain 243 and the spacer 244 . Here, the detector region 21 and the transistor region 22 are separated by an insulating layer 201 .

As shown in FIG. 2B , a composite layer 25 is formed on the substrate 20 , and the composite layer 25 also covers the doped region 23 and the transistor. Here, the composite layer 25 is used to increase the reflectivity of light entering the composite layer 25 from the doped region 23 , that is, it is used as an anti-reflection layer.

Here, the composite layer 25 is formed by interlacing and stacking a plurality of base layers, wherein the refractive index of each base layer is different from that of other adjacent base layers. Since total reflection may occur when light enters a low-refraction series material from a high-refractive-index material, total reflection cannot occur when light enters a high-refractive-index material from a low-refractive-index material, so by properly adjusting the refraction of each base layer Obviously, the light entering the composite layer 25 from the doped region 23 can be completely reflected (at least the probability of passing through the composite layer 25 is greatly reduced). That is, even if the material forming the composite layer 25 is a light-transmitting dielectric, the composite layer 25 can still function as an anti-reflection layer. Of course, the relationship between the refractive index and the thickness of each base layer can be adjusted according to actual needs, but generally the closer to the doped region 23 the higher the refractive index of the base layer, and the farther away from the doped region 23 the lower the refractive index of the base layer.

Generally speaking, the material of the composite layer 25 at least includes light-transmitting dielectrics such as plasma enhanced tetraethylorthosilicate (plasma enhanced TEOS) and plasma enhanced silicon nitride (Plasma enhanced siliconnitride), and in order to cooperate The self-aligned silicide block in the transistor region 22 is usually formed by interlacing at least one plasma-enhanced tetraethylorthosilicate layer with at least one plasma-enhanced silicon nitride layer. Herein, the plasma-enhanced tetraethyl orthosilicate layer is generally formed by a plasma-enhanced chemical vapor deposition process, and the plasma-enhanced silicon nitride layer is formed by a plasma-enhanced chemical vapor deposition process. Also, the composite layer 25 has a thickness of about 500 angstroms.

As shown in FIG. 2C , part of the composite layer 25 is removed by an etching process, so that the top of the gate 241 , the source 242 and the drain 243 are not covered by the composite layer 25 . The material on the top of the gate 241 is polysilicon.

As shown in FIG. 2D , a self-aligned silicide process is performed to form a metal silicide 26 on top of the gate 241 , and on the source 242 and the drain 243 . Here, since the material of the composite layer 25 is equivalent to that of the self-aligned silicide block in the known technology, there will be no adverse side effects when the composite layer 25 is used as the self-aligned silicide block.

Apparently, in this embodiment, the composite layer 25 has the function of self-aligning the silicide blocks during the process of forming the metal silicide 26 in the transistor region 22; the composite layer 25 formed on the doped region 23 It can also function as an anti-reflection layer. In other words, the present invention is a method that successfully integrates the fabrication process of the anti-reflection layer and the fabrication process of the self-aligned silicide block. In particular, since the process of forming the composite layer 25 is only to continuously form more than one dielectric layer, this method is also a method that can be practically applied in a production line.

Furthermore, when this embodiment is actually applied to provide a method for forming a light detection element, it also includes at least the following basic steps:

As shown in FIG. 2E , the remaining reactants of the self-aligned silicide process are removed, and a first dielectric layer 27 is formed to cover the composite layer 25 and the metal silicide 26 .

As shown in FIG. 2F , a plurality of multiple interconnections 28 are first formed on the first dielectric layer 27 , and then a second dielectric layer 29 is used to cover the first dielectric layer 27 and the multiple interconnections 28 . These multiple interconnects 28 are located above the transistors and the insulating layer 201 , and are usually connected to the transistors and may also be coupled to the doped regions 23 .

As shown in FIG. 2G , a plurality of color filters 295 are formed on the second dielectric layer 29 , and these color filters 295 are located above the doped region 23 . The possible types of the optical filter 295 include at least a red light filter, a blue light filter and a green light filter, and generally, there is one optical filter 295 above each doped region 23 .

In addition, as the structure of the semiconductor device becomes more and more complex, the substrate 20 also includes a plurality of resistors (resistors) (not shown in the figures), which are coupled to the transistors and completely formed by the composite layer 25 covered, and is used to provide the resistors needed to complete the circuit. Typically, the resistors are located on polysilicon structures on insulating layer 201, and typically these polysilicon structures are formed with polysilicon portions on top of the gates 241 of the respective transistors.

By comparing FIG. 2G with FIG. 1B, it can be seen that since the composite layer 25 can effectively play the role of an anti-reflection layer in this method, the opaque multiple interconnection 28 enables any one of the doped regions 23 to receive self-reflection. The probability of light reflected by other doped regions 23 can be minimized. In other words, the present invention can effectively prevent the phenomenon of cross-talk, so it is a method suitable for the manufacturing process of light detecting elements.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention; all other equivalent changes or amendments that do not deviate from the spirit disclosed by the present invention should be included in the following within the scope of the patent application.

Claims (29)

1. A method for integrating an anti-reflection layer and self-aligning silicide blocks, characterized in that it at least includes: A substrate is provided, and the substrate can be divided into at least a detector region and a transistor region, wherein the detector region includes at least a doped region and the transistor region includes at least a gate, a source and a transistor region. a transistor formed by a drain; forming a composite layer on the substrate, the composite layer covering both the doped region and the transistor, where the composite layer is used to increase light entering the composite layer from the doped region reflectivity; part of the composite layer is removed by an etching process, so that the top of the gate, the source and the drain are not covered by the composite layer, but remain in the detector area said composite layer on; and A salicide process is performed to form a metal silicide on top of the gate, over the source and the drain. 2. The method of claim 1, wherein the detector region is separated from the transistor region by an insulating layer. 3. The method according to claim 1, wherein the material at the top of the gate is polysilicon. 4. The method according to claim 1, wherein the composite layer is formed by interlacing and stacking a plurality of base layers. 5. The method of claim 4, wherein each of said base layers has a different refractive index than the adjacent other said base layers. 6. The method of claim 4, wherein the base layer closer to the doped region has a higher refractive index, and the base layer farther away from the doped region has a lower refractive index. 7. The method according to claim 1, wherein the material of the composite layer at least comprises plasma enhanced tetraethylorthosilicate and plasma enhanced silicon nitride. 8. The method according to claim 1, wherein the composite layer is formed of at least one layer of plasma-enhanced tetraethylorthosilicate layer and at least one layer of plasma-enhanced silicon nitride layer. stacked. 9. The method of claim 8, wherein the plasma-enhanced tetraethylorthosilicate layer is formed by a plasma-enhanced chemical vapor deposition process. 10. The method of claim 8, wherein the plasma-enhanced silicon nitride layer is formed by a plasma-enhanced chemical vapor deposition process. 11. The method of claim 1, wherein the composite layer has a thickness of 500 Angstroms. 12. A method of forming a photodetection element, comprising at least: A substrate is provided, the substrate at least includes a plurality of doped regions, a plurality of transistors and a plurality of insulating layers: forming a composite layer on the substrate and covering all of the doped regions, the transistors and the insulating layer, where the composite layer is used to increase the intensity of light entering the composite layer from the substrate Reflectivity; performing an etching process to define a region where a metal silicide is to be subsequently formed and remove the composite layer at a portion of the region, wherein the region includes at least tops of a plurality of gates, a plurality of sources and a plurality of drains pole; performing a self-aligned silicide process to form a metal silicide on top of the gate, over the source and the drain; removing reactants remaining from the self-aligned silicide process; forming a first dielectric layer on the composite layer and the metal silicide; forming a plurality of multiple interconnects on the first dielectric layer, the multiple interconnects are located above the transistor and the insulating layer; covering the first dielectric layer and the multiple interconnection lines with a second dielectric layer; and A plurality of optical filters are formed on the second dielectric layer, the optical filters are located above the doped region. 13. The method of claim 12, wherein the substrate further comprises a plurality of resistors. 14. The method of claim 13, wherein the resistor is a polysilicon structure on the insulating layer. 15. The method of claim 14, wherein the polysilicon structure is formed with a polysilicon portion on top of a gate of the transistor. 16. The method of claim 12, wherein the plurality of resistors are coupled to the transistor. 17. The method of claim 12, wherein the composite layer also completely covers the resistor. 18. The method according to claim 12, wherein the composite layer is formed by interlacing and stacking a plurality of base layers. 19. The method of claim 18, wherein each of said base layers has a different refractive index than the adjacent other said base layers. 20. The method of claim 18, wherein the base layer closer to the substrate has a higher refractive index, and the base layer farther away from the substrate has a lower refractive index. 21. The method according to claim 12, wherein the material of the composite layer at least comprises plasma-enhanced tetraethylorthosilicate and plasma-enhanced silicon nitride. 22. The method according to claim 12, wherein the composite layer is an alternating phase of at least one layer of plasma-enhanced tetraethyl orthosilicate layer and at least one layer of plasma-enhanced silicon nitride layer. stacked. 23. The method of claim 22, wherein the plasma-enhanced tetraethylorthosilicate layer is formed by a plasma-enhanced chemical vapor deposition process. 24. The method of claim 22, wherein the plasma enhanced silicon nitride layer is formed by a plasma enhanced chemical vapor deposition process. 25. The method of claim 12, wherein the composite layer has a thickness of 500 Angstroms. 26. The method of claim 12, wherein the plurality of multiple interconnects are connected to the transistor. 27. The method of claim 12, wherein the plurality of multiple interconnects are coupled to the doped region. 28. The method according to claim 12, wherein the types of the optical filters at least include a red light filter, a blue light filter and a green light filter. 29. The method of claim 12, wherein each of the doped regions is above one of the optical filters.

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