CN117221252A - Multi-physical interface control communication method and system of Ethernet and Ethernet chip - Google Patents

Abstract

The application discloses a method and a system for controlling communication by multiple physical interfaces of Ethernet and an Ethernet chip, wherein the method comprises the following steps: when the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration serial number to an arbitration bus for arbitration; the Ethernet chip inquires the arbitration result of each PHY chip and receives the data sent by the PHY chip which wins the arbitration. In the application, when a plurality of PHY chips send data to the Ethernet chip, the PHY chips send arbitration sequences to the arbitration bus, then the arbitration serial numbers returned by the arbitration bus are compared with the arbitration serial numbers sent by the PHY chips until the comparison results are consistent, and the PHY chips can send data to the Ethernet chip, so that the data sending sequences of the PHY chips can be sequenced successively, thereby realizing the communication between one Ethernet chip and the plurality of PHY chips, and reducing the cost.

Description

Ethernet multi-physical interface control communication method, system and Ethernet chip

Technical field

The present invention relates to the technical field of Ethernet, and in particular to an Ethernet multi-physical interface control communication method and system and an Ethernet chip.

Background technique

Ethernet is a computer network, and it is also the most widely used network access technology in local area networks. Ethernet has its own advantages in data transmission and can be connected to the Internet to achieve a wider range of remote access control. The IEEE organization has formulated the technical standards for Ethernet in the IEEE 802.3 standard. The Media Access Control (MAC) layer of Ethernet can communicate with the physical layer (PHY) through the media independent interface. The default media independent interface is media independent. Interface (Media Independent Interface, MII) and simplified Reduced Media Independent Interface (RMII), the communication rate can reach 10/100Mbit/s.

The current Ethernet MAC can support access to up to 32 PHY chips through the station management interface (Serial Management Interface, SMI). The application can select one PHY from 32 PHYs to send control data or receive status information, so one PHY can be used at the same time. The MAC of the Ethernet chip can only communicate with one PHY. However, when it comes to communication between the MAC of an Ethernet chip and multiple PHY chips, it is necessary to configure a PHY chip for each Ethernet chip, which requires the use of multiple Ethernet chips and the cost is high.

Therefore, the existing technology still needs to be improved and developed.

Contents of the invention

In view of the shortcomings of the above-mentioned existing technologies, the purpose of the present invention is to provide an Ethernet multi-physical interface control communication method, system and Ethernet chip to solve the problem that the MAC of the existing Ethernet chip needs to be used when communicating with multiple PHY chips. The problem of higher cost caused by multiple Ethernet chips.

The technical solution of the present invention is as follows:

An Ethernet multi-physical interface control communication method, which includes:

When the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration sequence number to the arbitration bus for arbitration;

The Ethernet chip queries the arbitration results of each PHY chip and receives the data sent by the PHY chip that wins the arbitration.

In a further arrangement of the present invention, when the Ethernet chip receives data sent by more than two PHY chips, the step of each PHY chip sending an arbitration sequence number to the arbitration bus for arbitration includes:

Each PHY chip sends the arbitration sequence number to the arbitration bus;

The PHY chip compares the arbitration sequence number sent with the arbitration sequence number returned by the arbitration bus. When the comparison results are consistent, the PHY chip wins the arbitration and sends data to the Ethernet chip;

When the arbitration sequence number sent by the PHY chip is inconsistent with the arbitration sequence number returned by the arbitration bus, the PHY chip is controlled to continue sending the arbitration sequence number to the arbitration bus until the comparison results are consistent.

In a further arrangement of the present invention, the step of the Ethernet chip querying the arbitration results of each PHY chip and receiving the data sent by the PHY chip that wins the arbitration includes:

The Ethernet chip sends address requests to each PHY chip in the form of broadcast;

Get the address of the PHY chip that wins the arbitration;

Receive the data sent by the PHY chip that wins the arbitration.

In a further arrangement of the present invention, the step of each PHY chip sending an arbitration sequence number to the arbitration bus includes:

When the PHY chip receives data, it caches the data and sends an arbitration sequence number to the arbitration bus.

In a further arrangement of the present invention, the arbitration sequence numbers of each PHY chip are inconsistent.

In a further configuration of the present invention, the multi-physical interface control communication method of Ethernet also includes:

When the Ethernet chip communicates with a PHY chip, disconnect the arbitration bus and obtain the address of the PHY chip;

Receive data sent by the PHY chip.

In a further configuration of the present invention, the multi-physical interface control communication method of Ethernet also includes:

When the Ethernet chip sends data to the PHY chip, it obtains the address of the PHY chip that needs to be accessed;

The Ethernet chip sends data to the PHY chip according to the address of the PHY chip.

An Ethernet multi-physical interface control communication system, which includes: an Ethernet chip, a PHY chip, an arbitration bus, a media independent interface bus and a station management interface bus; wherein,

The Ethernet chip has a media access control unit;

Each PHY chip is connected through the arbitration bus;

The medium independent interface bus is connected between the medium access control unit and the PHY chip;

The station management interface bus is connected between the media access control unit and the PHY chip;

The Ethernet chip sends data to the PHY chip through the medium independent interface bus, and receives the data sent by the PHY chip;

The PHY chip is configured to send an arbitration sequence number to the arbitration bus when receiving data, and arbitrate the sent arbitration sequence number with the arbitration sequence number returned by the arbitration bus;

The Ethernet chip is also used to query the arbitration results of each PHY chip through the station management interface bus.

In a further arrangement of the present invention, the PHY chip includes: a cache module and an arbitration module; wherein,

The cache module is connected to the media access control unit through the media independent interface bus and is used to receive data and cache the data;

The arbitration module is connected to the media access control unit through the station management interface bus, and is used to send an arbitration sequence number to the arbitration bus when the PHY chip receives data, and compare the sent arbitration sequence number with the arbitration module. The arbitration sequence numbers returned by the bus are compared, and the comparison results are fed back to the Ethernet chip when the Ethernet chip queries the arbitration results of each PHY chip through the station management interface bus.

An Ethernet chip includes a memory and a processor. A computer program is stored on the memory. When the computer program is executed by the processor, it is used to implement the above-mentioned multi-physical interface control communication method of Ethernet.

The invention provides an Ethernet multi-physical interface control communication method, system and Ethernet chip. The Ethernet multi-physical interface control communication method includes: when the Ethernet chip receives data sent by more than two PHY chips, each The PHY chip sends an arbitration sequence number to the arbitration bus for arbitration; the Ethernet chip queries the arbitration results of each PHY chip and receives the data sent by the PHY chip that wins the arbitration. In the present invention, when multiple PHY chips send data to the Ethernet chip, first the PHY chip sends an arbitration sequence to the arbitration bus, and then compares the arbitration sequence number returned by the arbitration bus with the arbitration sequence number sent by the PHY chip until the comparison result Only when they are consistent, the PHY chip will send data to the Ethernet chip, so that the data sending order of the PHY chip can be sorted, thereby realizing communication between one Ethernet chip and multiple PHY chips and reducing costs.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments of the present invention. For ordinary people in the art, without exerting creative efforts, other drawings can be obtained based on the structures shown in these drawings.

Figure 1 is a schematic flowchart of the multi-physical interface control communication method of Ethernet in the present invention.

Figure 2 is a flow chart of data sent by an Ethernet chip in an embodiment of the present invention.

FIG. 3 is a flow chart of an Ethernet chip receiving data in an embodiment of the present invention.

Figure 4 is a schematic diagram of the Ethernet multi-physical interface control communication system in the present invention.

Figure 5 is a schematic diagram of communication between an Ethernet chip and a single PHY chip in the present invention.

Labels in the drawing: 100, Ethernet chip; 110, media access control unit; 200, PHY chip; 210, cache module; 220, arbitration module.

Detailed ways

The present invention provides an Ethernet multi-physical interface control communication method, system and Ethernet chip. In order to make the purpose, technical solution and effect of the present invention clearer and clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

In the embodiments and patent applications, unless the context specifically limits the article, "a", "an", "the" and "the" may also include plural forms. If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are for descriptive purposes only and cannot be understood as indicating or implying their relative Significance or implicit indication of the quantity of a technical feature indicated. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features.

It should be further understood that the word "comprising" used in the description of the present invention refers to the presence of stated features, integers, steps, operations, elements and/or components, but does not exclude the presence or addition of one or more other features, Integers, steps, operations, elements, components and/or groups thereof. It will be understood that when we refer to an element being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Additionally, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. As used herein, the term "and/or" includes all or any unit and all combinations of one or more of the associated listed items.

It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should also be understood that terms, such as those defined in general dictionaries, are to be understood to have meanings consistent with their meaning in the context of the prior art, and are not to be used in an idealistic or overly descriptive manner unless specifically defined as here. to explain the formal meaning.

In addition, the technical solutions in various embodiments can be combined with each other, but it must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor within the protection scope required by the present invention.

Please refer to Figures 1 to 3 at the same time. The present invention provides a preferred embodiment of a multi-physical interface control communication method of Ethernet.

The invention provides an Ethernet multi-physical interface control communication method, as shown in Figure 1, which includes the steps:

S100. When the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration sequence number to the arbitration bus for arbitration;

In this embodiment, when the PHY chip receives the data, it begins to prepare to send data to the media access control unit MAC of the Ethernet chip. At this time, each PHY chip sends an arbitration sequence number to the arbitration bus, and at the same time, the arbitration bus will also reply An arbitration sequence number. If the arbitration sequence number returned by the arbitration bus is the same as the arbitration sequence number sent by the PHY chip, it means that the arbitration has won. The PHY chip that currently wins the arbitration can send data to the media access control unit MAC of the Ethernet chip. Among them, if the PHY chip does not receive data, the PHY chip will not send the arbitration sequence number to the arbitration neutral line.

S200 and the Ethernet chip query the arbitration results of each PHY chip and receive the data sent by the PHY chip that wins the arbitration.

In this embodiment, the Ethernet chip will query the arbitration results of each PHY chip through the station management interface bus. When the query finds that the arbitration result of one of the PHY chips is consistent, the data sent by the PHY chip that satisfies the arbitration result will be received first. , until the data transmission of all PHY chips is completed.

It can be seen that in the present invention, when multiple PHY chips send data to the Ethernet chip, first the PHY chip will send the arbitration sequence to the arbitration bus, and then compare the arbitration sequence number returned by the arbitration bus with the arbitration sequence number sent by the PHY chip. , when the comparison results are consistent, that is, only when the arbitration is successful, the PHY chip will send data to the Ethernet chip, so that the data sending order of the PHY chips can be sorted to avoid two or more PHY chips at the same time. Send data to the Ethernet chip, thereby realizing communication between one Ethernet chip and multiple PHY chips, reducing costs.

In some embodiments, when the Ethernet chip receives data sent by more than two PHY chips, the step of each PHY chip sending an arbitration sequence number to the arbitration bus for arbitration includes sub-steps:

S110. Each PHY chip sends the arbitration sequence number to the arbitration bus;

S120. The PHY chip compares the arbitration sequence number sent with the arbitration sequence number returned by the arbitration bus. When the comparison results are consistent, the PHY chip wins the arbitration and sends data to the Ethernet chip;

S130. When the arbitration sequence number sent by the PHY chip is inconsistent with the arbitration sequence number returned by the arbitration bus, the PHY chip continues to send the arbitration sequence number to the arbitration bus until the comparison results are consistent.

In this embodiment, the PHY chip compares the arbitration sequence number sent with the arbitration sequence number returned by the arbitration bus. If the comparison results are consistent, it means that the current PHY chip has won the arbitration. If the arbitration sequence number returned by the arbitration bus is the same as the arbitration sequence number sent by the PHY chip, If the arbitration sequence numbers are inconsistent, it means that the arbitration has failed. The PHY chip will continue to send data to the arbitration bus, wait for an arbitration sequence number to be returned on the arbitration bus for comparison, and will not send data to the Ethernet chip until the arbitration is successful. It should be noted that each PHY chip defines an arbitration sequence number. That is to say, the arbitration sequence numbers of each PHY chip are inconsistent. Then when each PHY chip sends the arbitration sequence number to the arbitration bus and compares it, at the same time Only one PHY chip will succeed, and the PHY chip with successful arbitration can send data to the Ethernet chip.

In some embodiments, the step of sending each PHY chip to the arbitration bus includes sub-steps:

S111. When the PHY chip receives data, it caches the data and sends an arbitration sequence number to the arbitration bus.

In this embodiment, when the PHY chip receives data and needs to send data to the Ethernet, the received data will first be cached, and the data will not be sent to the Ethernet chip until the PHY chip wins the arbitration.

In some embodiments, the step of the Ethernet chip querying the arbitration results of each PHY chip and receiving the data sent by the PHY chip that wins the arbitration includes sub-steps:

S210, the Ethernet chip sends an address request to each PHY chip in the form of broadcast;

S220. Obtain the address of the PHY chip that wins the arbitration;

S230. Receive data sent by the PHY chip that wins the arbitration.

In this embodiment, the Ethernet chip controls the PHY chip that needs to send data through the station management interface bus SMI. During the arbitration process of the PHY chip, the Ethernet chip will query the arbitration results of the PHY chip and send address requests to each PHY chip in the form of broadcast. When it is found that a certain PHY chip has won the arbitration, it will pass the station management The interface bus SMI obtains the address of the PHY chip that wins the arbitration, and receives the data sent by the PHY chip through the media independent interface bus MII.

In some embodiments, the Ethernet multi-physical interface control communication method further includes:

S300. When the Ethernet chip communicates with a PHY chip, disconnect the arbitration bus and obtain the address of the PHY chip;

S400. Receive data sent by the PHY chip.

In this embodiment, when only a single PHY chip needs to communicate with the Ethernet chip, there is no need for the PHY chip to arbitrate with the arbitration bus. Therefore, the arbitration bus can be disconnected, and the Ethernet chip directly obtains the address of the PHY chip. You can receive the data sent by the PHY chip. Therefore, while the present application realizes communication between an Ethernet chip and multiple PHY chips, it is also compatible with the communication between a traditional single PHY chip and an Ethernet chip.

In some embodiments, the Ethernet multi-physical interface control communication method further includes:

S101. When the Ethernet chip sends data to the PHY chip, obtain the address of the PHY chip that needs to be accessed;

S102. The Ethernet chip sends data to the PHY chip according to the address of the PHY chip.

In this embodiment, the medium access control unit MAC of the Ethernet chip and the PHY chip are connected using the medium independent interface bus MII or the refined medium independent interface bus RMII to realize the sending and receiving of data. Moreover, the media access control unit MAC of the Ethernet chip is also connected to the PHY chip through the station management interface bus SMI. The Ethernet chip controls the PHY chip that needs to send data through the station management interface bus, and the Ethernet chip obtains the PHY that needs to send data. After the address of the chip, data is sent to each PHY chip through the media independent interface bus or the refined media independent interface bus.

The following uses the Ethernet chip as a single-chip microcomputer MCU as an example to explain the communication principle between the Ethernet chip and the PHY chip. As shown in Figure 2 and Figure 3, the microcontroller MCU transmits the required data through the FIFO memory to the media access control unit through the AHB interface. The media access control unit accesses the PHY chip through the station management interface bus SMI and writes the PHY chip address and data. , the media access control unit sends data to the PHY chip to be accessed through the media independent interface bus MII or the refined media independent interface bus RMII. This process is the data sending process of the Ethernet chip. After the PHY chip receives the data, it prepares to send it to the media access control unit, stores the data in the cache module, and waits for the comparison result of the arbitration module. The arbitration module begins to continuously send arbitration sequence numbers to the arbitration bus, and the arbitration bus returns an arbitration sequence. number, compare the returned arbitration sequence number with the arbitration sequence number sent by the PHY chip. If the comparison results are consistent, the arbitration will win. Otherwise, the arbitration will fail. After the arbitration wins, the data received by the PHY chip will be sent from the cache module to the media independent The interface bus MII or the reduced medium independent interface bus RMII is sent to the media access control unit of the microcontroller through the medium independent interface bus MII or the reduced medium independent interface bus to complete the data transmission of the PHY chip, that is, to complete the receiving process of the Ethernet chip data.

In some embodiments, as shown in Figure 4, this application also provides an Ethernet multi-physical interface control communication system, which includes: an Ethernet chip 100, a PHY chip 200, an arbitration bus AB, and a media independent interface bus MII with the station management interface bus SMI. Wherein, the Ethernet chip 100 has a media access control unit 110; each PHY chip 200 is connected through the arbitration bus AB; the media independent interface bus MII is connected between the media access control unit 110 and the PHY chip 200; The station management interface bus SMI is connected between the media access control unit 110 and the PHY chip 200; the Ethernet chip 100 sends data to the PHY chip 200 through the media independent interface bus MII, and receives the Data sent by the PHY chip 200; the PHY chip 200 is used to send an arbitration sequence number to the arbitration bus AB when receiving data, and arbitrate the sent arbitration sequence number with the arbitration sequence number returned by the arbitration bus AB. ; The Ethernet chip 100 is also used to query the arbitration results of each PHY chip 200 through the station management interface bus SMI.

In this embodiment, when the Ethernet chip 100 communicates with multiple PHY chips 200, each PHY chip 200 is connected through the arbitration bus AB, and each PHY chip 200 sends an arbitration sequence number to the arbitration bus AB, and replies with the arbitration bus AB. After the arbitration serial number is arbitrated, only the PHY chip 200 that wins the arbitration can send data to the Ethernet chip 100 to avoid the arbitration priority when two or more PHY chips 200 send data to the Ethernet chip 100 at the same time. Preemption problem. The medium independent interface bus MMI is connected between the Ethernet chip 100 and the PHY chip 200, and is used to realize data transmission (including sending and receiving) between the Ethernet chip 100 and the PHY chip 200. The station management interface bus SMI is connected between the Ethernet chip 100 and the PHY chip 200. The Ethernet chip 100 controls each PHY chip 200 through the station management interface bus SMI. For example, when sending data, it can control the need to send The PHY chip 200 of the data obtains the address of the PHY chip 200 that needs to send the data. When receiving the data, each PHY chip 200 can be queried to obtain the address of the PHY chip 200 that wins the arbitration, so as to obtain the address of the PHY chip 200 that wins the arbitration. The sent data is received.

In some embodiments, the Ethernet chip 100 may be a microcontroller MCU.

In specific implementation, taking the MCU as an example, when the MCU sends data to the PHY chip 200, the MCU transmits the data to be sent to the media access control unit 110 through the FIFO (First Input First Output) buffer through the AHB bus, and then the media The access control unit 110 then accesses the PHY chip 200 through the station management interface bus SMI and writes the address and data of the PHY chip 200, and then transmits the data to be sent to the PHY chip 200 that needs to be accessed through the media independent interface bus MII.

When multiple PHY chips 200 send data to the microcontroller MCU, first the PHY chip 200 sends an arbitration sequence to the arbitration bus AB, and then compares the arbitration sequence number returned by the arbitration bus AB with the arbitration sequence number sent by the PHY chip 200. When the comparison results are consistent time, that is, only when the arbitration is successful, the PHY chip 200 will send data to the microcontroller. In this way, the data sending sequence of the PHY chips 200 can be sorted to prevent two or more PHY chips 200 from sending data to the microcontroller at the same time. data, thereby realizing communication between one Ethernet chip 100 and multiple PHY chips 200, reducing costs.

In some embodiments, as shown in Figure 5, in this embodiment, when only a single PHY chip is required to communicate with the Ethernet chip 100, there is no need for the PHY chip 200 to arbitrate with the arbitration bus AB, so the arbitration can be When bus AB is disconnected, the Ethernet chip 100 can receive the data sent by the PHY chip 200 directly by obtaining the address of the PHY chip 200 . Therefore, while the present application realizes the communication between the Ethernet chip 100 and multiple PHY chips 200, it can also be compatible with the communication between the traditional single PHY chip and the Ethernet chip.

In some embodiments, as shown in Figure 4, the PHY chip 200 includes: a cache module 210 and an arbitration module 220; wherein the cache module 210 communicates with the media access control unit 110 through the media independent interface bus MII. connection, used to receive data and cache the data; the arbitration module 220 is connected to the media access control unit 110 through the station management interface bus SMI, and is used to report to the arbitration bus when the PHY chip 200 receives data. AB sends an arbitration sequence number, compares the sent arbitration sequence number with the arbitration sequence number returned by the arbitration bus AB, and arbitrates each PHY chip 200 on the Ethernet chip 100 through the station management interface bus SMI. When querying the result, the comparison result is fed back to the Ethernet chip 100 .

In this embodiment, the cache module 210 is mainly used to cache data received by the PHY chip 200. When the PHY chip 200 receives data that needs to be sent to the Ethernet chip 100, the data will first be cached in the cache module 210. . The arbitration module 220 defines an arbitration sequence number for the PHY chip 200. Each time the PHY chip 200 receives data, the arbitration module 220 will always send the arbitration sequence number to the arbitration bus AB, and the arbitration bus AB will also reply with an arbitration sequence number. Arbitration sequence number. The arbitration module 220 will compare the sent arbitration sequence number with the arbitration sequence number returned by the arbitration bus AB. If the comparison result is consistent, that is, the arbitration sequence number sent by the arbitration module 220 is consistent with the received arbitration sequence number. , indicating that the arbitration has won. The Ethernet chip 100 can query the arbitration results of each PHY chip 200 through the station management interface bus SMI, and send an address request to each PHY chip 200 in the form of a broadcast. The PHY that wins the arbitration The data cached in the cache module 210 of the chip 200 will be sent to the Ethernet chip 100 . If the PHY chip 200 fails in arbitration, the arbitration module 220 will continue to send the arbitration sequence number and wait for the next arbitration sequence number to be returned on the arbitration bus for comparison until the arbitration is won.

In some embodiments, the cache module 210 may be a FIFO cache, a static random access memory (Static Random-Access Memory, SRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM), etc., and the arbitration bus AB may be CAN bus, I2C bus and other arbitration buses, then the arbitration module 220 can be a CAN bus arbitration module, an I2C bus arbitration module, etc.

In some embodiments, this application also provides an Ethernet chip, which includes a memory and a processor. A computer program is stored on the memory. The computer program is used to implement the following methods when executed by the processor. A step of:

S100. When the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration sequence number to the arbitration bus for arbitration;

S200 and the Ethernet chip query the arbitration results of each PHY chip and receive the data sent by the PHY chip that wins the arbitration.

To sum up, the Ethernet multi-physical interface control communication method, system and Ethernet chip provided by the present invention have the following beneficial effects:

When multiple PHY chips send data to the Ethernet chip, first the PHY chip will send the arbitration sequence to the arbitration bus, and then compare the arbitration sequence number returned by the arbitration bus with the arbitration sequence number sent by the PHY chip until the comparison results are consistent. Only the PHY chip will send data to the Ethernet chip, so that the data sending order of the PHY chip can be sorted, thereby realizing communication between one Ethernet chip and multiple PHY chips. One Ethernet chip can receive and analyze multiple PHYs. Chip data can effectively reduce costs and improve communication efficiency.

It should be understood that the application of the present invention is not limited to the above examples. Those of ordinary skill in the art can make improvements or changes based on the above descriptions. All these improvements and changes should fall within the protection scope of the appended claims of the present invention.

Claims (10)

1. A method for controlling communication by multiple physical interfaces of an ethernet network, comprising:

when the Ethernet chip receives data sent by more than two PHY chips, each PHY chip sends an arbitration serial number to an arbitration bus for arbitration;

the Ethernet chip inquires the arbitration result of each PHY chip and receives the data sent by the PHY chip which wins the arbitration.

2. The method of claim 1, wherein when the ethernet chip receives data transmitted from two or more PHY chips, each PHY chip transmits an arbitration sequence number to an arbitration bus to perform arbitration, comprising:

each PHY chip sends an arbitration serial number to an arbitration bus;

the PHY chip compares the transmitted arbitration serial number with the arbitration serial number returned by the arbitration bus, and when the comparison result is consistent, the PHY chip arbitrates out and transmits data to the Ethernet chip;

when the arbitration serial number sent by the PHY chip is inconsistent with the arbitration serial number returned by the arbitration bus, the PHY chip continues to send the arbitration serial number to the arbitration bus until the comparison result is consistent.

3. The method for ethernet multi-physical interface control communication according to claim 1, wherein the step of the ethernet chip querying the arbitration result of each PHY chip and receiving the data transmitted by the PHY chip that has winning arbitration comprises:

the Ethernet chip sends address requests to each PHY chip in a broadcast mode;

acquiring the address of a PHY chip which wins arbitration;

and receiving the data transmitted by the PHY chip which wins arbitration.

4. The method of claim 2, wherein the step of each PHY chip transmitting an arbitration sequence number to an arbitration bus comprises:

and when the PHY chip receives the data, caching the data and sending an arbitration serial number to an arbitration bus.

5. The method of claim 1, wherein the arbitration sequence number of each PHY chip is not identical.

6. The method of claim 1, further comprising:

when the Ethernet chip communicates with one PHY chip, disconnecting the arbitration bus and acquiring the address of the PHY chip;

and receiving the data sent by the PHY chip.

7. The method of claim 1, further comprising:

when the Ethernet chip sends data to the PHY chip, the address of the PHY chip to be accessed is acquired;

the ethernet chip sends data to the PHY chip according to the address of the PHY chip.

8. A multi-physical interface control communication system for an ethernet network, comprising: an Ethernet chip, a PHY chip, an arbitration bus, a medium independent interface bus and a station management interface bus; wherein,

the Ethernet chip is provided with a medium access control unit;

each PHY chip is connected through the arbitration bus;

the medium independent interface bus is connected between the medium access control unit and the PHY chip;

the station management interface bus is connected between the medium access control unit and the PHY chip;

the Ethernet chip sends data to the PHY chip through the medium independent interface bus and receives the data sent by the PHY chip;

the PHY chip is used for sending an arbitration serial number to the arbitration bus when receiving data, and arbitrating the sent arbitration serial number with an arbitration serial number returned by the arbitration bus;

the Ethernet chip is also used for inquiring the arbitration result of each PHY chip through the station management interface bus.

9. The ethernet multi-physical interface control communication system according to claim 8, wherein said PHY chip comprises: the system comprises a cache module and an arbitration module; wherein,

the buffer memory module is connected with the medium access control unit through the medium independent interface bus and is used for receiving data and buffering the data;

the arbitration module is connected with the medium access control unit through the station management interface bus, and is used for sending an arbitration serial number to the arbitration bus when the PHY chip receives data, comparing the sent arbitration serial number with the arbitration serial number returned by the arbitration bus, and feeding back the comparison result to the Ethernet chip when the Ethernet chip inquires the arbitration result of each PHY chip through the station management interface bus.

10. An ethernet chip comprising a memory and a processor, said memory having stored thereon a computer program which, when executed by said processor, is adapted to implement the ethernet multi-physical interface control communication method of any of claims 1-7.