CN117116974B - Semiconductor devices - Google Patents

Abstract

The invention discloses a semiconductor device, which comprises: a drift layer; a pressure ring; the polycrystalline silicon field plate is arranged above the surface of the compression ring and provided with a first via hole; the first dielectric layer is arranged above the surface of the polysilicon field plate, the first dielectric layer is provided with a second via hole and a third via hole, the second via hole corresponds to the first via hole, and the third via hole and the second via hole are arranged on the surface of the first dielectric layer at intervals; the metal field plate is arranged above the surface of the first dielectric layer, the metal field plate is provided with a first electric connection bulge and a second electric connection bulge, the first electric connection bulge sequentially penetrates through the second through hole and the first through hole and is electrically connected with the pressure-resistant ring, and the second electric connection bulge penetrates through the third through hole and is electrically connected with the polysilicon field plate. Therefore, the voltage resistance ring, the polysilicon field plate and the metal field plate can be equipotential, so that the voltage resistance capability and the reliability of the semiconductor device are improved.

Description

Semiconductor devices

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device.

Background Art

For semiconductor devices, the PN junction at the edge of the chip is a curved surface, where the electric field lines are relatively concentrated, the electric field strength is strong, and the voltage per unit length is large, so it is easier for voltage breakdown to occur there. To improve this situation, terminal structures are designed at the edge of the chip to optimize the electric field distribution and increase the breakdown voltage. Furthermore, a metal field plate is usually designed at the last voltage-resistant ring to improve the electric field distribution at the cutoff ring, thereby improving the voltage resistance and reliability of the device.

In the related art, for the terminal containing a polysilicon field plate structure, there is a dielectric layer between the polysilicon field plate and the metal field plate at the last voltage-resistant ring. The dielectric layer separates the metal field plate and the polysilicon field plate, resulting in the metal field plate and the polysilicon field plate not contacting each other and having different electric potentials; or when there is field oxygen above the terminal well region, the polysilicon field plate, the metal field plate and the well region, the three or two of them do not contact each other, forming a floating electric field, which will affect the electric field distribution in the area and reduce reliability.

Summary of the invention

The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device with higher voltage resistance and reliability.

According to an embodiment of the present invention, a semiconductor device includes: a drift layer of a first conductivity type; a voltage-resistant ring of a second conductivity type, the voltage-resistant ring being arranged at a portion of the drift layer corresponding to a terminal region of the semiconductor device; a polysilicon field plate, the polysilicon field plate being arranged above a surface of the voltage-resistant ring and being electrically connected to the voltage-resistant ring, the polysilicon field plate being provided with a first via hole; a first dielectric layer, the first dielectric layer being arranged above the surface of the polysilicon field plate, the first dielectric layer being provided with a second via hole and a third via hole, the second via hole corresponding to the first via hole, the third via hole and the second via hole being arranged at intervals on the surface of the first dielectric layer; a metal field plate, the metal field plate being arranged above the surface of the first dielectric layer, the metal field plate being provided with a first electrical connection protrusion and a second electrical connection protrusion, the first electrical connection protrusion being sequentially provided with the second via hole and the first via hole and being electrically connected to the voltage-resistant ring, the second electrical connection protrusion being provided with the third via hole and being electrically connected to the polysilicon field plate.

Therefore, by allowing the first electrical connection protrusion to pass through the second via and the first via in sequence and be electrically connected to the voltage-resistant ring, and the second electrical connection protrusion to pass through the third via and be electrically connected to the polysilicon field plate, the voltage-resistant ring, the polysilicon field plate and the metal field plate can be made to have the same electric potential, thereby improving the voltage resistance and reliability of the semiconductor device.

In some examples of the present invention, the second via hole and the first via hole are arranged above and within the boundaries of both sides of the voltage-resistant ring, and both sides of the metal field plate and the polysilicon field plate extend out of the boundaries of both sides of the voltage-resistant ring respectively.

In some examples of the present invention, a diameter of the first via hole is larger than a diameter of the second via hole.

In some examples of the present invention, the first electrical connection protrusion and the polysilicon field plate are circumferentially spaced apart from each other on the inner wall of the first via hole corresponding to the first via hole.

In some examples of the present invention, there are multiple first vias, and the multiple first vias are spaced apart on the surface of the polysilicon field plate. There are multiple first electrical connection protrusions, and the multiple first electrical connection protrusions correspond one-to-one to the multiple first vias.

In some examples of the present invention, the semiconductor device also includes a field oxide layer, which is arranged above the surface of the voltage-resistant ring and between the polysilicon field plate and the voltage-resistant ring. The field oxide layer is provided with a fourth via, and the fourth via corresponds to the first via and the second via. The first electrical connection protrusion passes through the second via, the first via and the fourth via in sequence and is electrically connected to the voltage-resistant ring.

In some examples of the present invention, a diameter of the fourth via hole is equal to a diameter of the second via hole.

In some examples of the present invention, the semiconductor device also includes an active area and a transition area, the transition area is arranged between the active area and the terminal area, there are multiple voltage-resistant rings, the multiple voltage-resistant rings are arranged at intervals, and the polysilicon field plate and the metal field plate are correspondingly arranged above one of the multiple voltage-resistant rings far away from the transition area.

In some examples of the present invention, there are a plurality of the pressure-resistant rings, the plurality of the pressure-resistant rings are arranged at intervals, and the polysilicon field plate and the metal field plate are correspondingly arranged above at least one of the plurality of the pressure-resistant rings.

In some examples of the present invention, there are multiple polysilicon field plates, and the multiple polysilicon field plates are arranged at intervals. The multiple polysilicon field plates are all provided with a first via hole, and a second dielectric layer is provided between two adjacent polysilicon field plates. The first via holes on the multiple polysilicon field plates correspond to each other, and the second dielectric layer is provided with a fifth via hole, which corresponds to the first via hole, and the first electrical connection protrusion passes through the fifth via hole, the first via hole and the second via hole and is electrically connected to the voltage-resistant ring.

Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

FIG1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;

2 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention;

3 is a partial cross-sectional view of another position of a semiconductor device according to an embodiment of the present invention;

4 is a partial cross-sectional view of a semiconductor device according to another embodiment of the present invention;

FIG. 5 is a partial schematic diagram of a polysilicon field plate according to an embodiment of the present invention.

Reference numerals:

100, semiconductor device; 101, termination region; 102, active region; 103, transition region;

10. Drift layer;

20. Pressure-resistant ring;

30. polysilicon field plate; 31. first via hole;

40. first dielectric layer; 41. second via hole; 42. third via hole;

50. Metal field plate; 51. First electrical connection protrusion; 52. Second electrical connection protrusion;

60. Field oxide layer; 61. Fourth via hole;

70. Field stop layer; 80. Collector layer; 90. Collector metal layer.

DETAILED DESCRIPTION

Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

The semiconductor device 100 according to an embodiment of the present invention is described below with reference to FIGS. 1 to 5. The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor). In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description.

As shown in FIG. 1 , the semiconductor device 100 according to the present invention may mainly include: a drift layer 10 of a first conductivity type, a voltage-resistant ring 20 of a second conductivity type, a polysilicon field plate 30 , a first dielectric layer 40 and a metal field plate 50 .

Specifically, a first conductive type field stop layer 70 is arranged below the first conductive type drift layer 10, a second conductive type collector layer 80 is arranged below the field stop layer 70, and a collector metal layer 90 is arranged below the collector layer 80, thereby forming the basic structure of the semiconductor structure and ensuring the normal operation of the semiconductor device 100.

Taking into account that the electric field strength in the terminal region 101 of the semiconductor device 100 is relatively strong and the voltage per unit length is relatively large, it is easier for voltage breakdown to occur there. By arranging the voltage-resistant ring 20 on the surface of the drift layer 10 corresponding to the terminal region 101 of the semiconductor device, the voltage-resistant ring 20 can optimize the electric field distribution in the terminal region 101 and improve the voltage resistance of the terminal region 101.

Further, in combination with Figures 1 and 3, the polysilicon field plate 30 is arranged above the surface of the voltage-resistant ring 20 and is electrically connected to the voltage-resistant ring 20. The polysilicon field plate 30 is provided with a first via 31. The first dielectric layer 40 is arranged above the surface of the polysilicon field plate 30. The first dielectric layer 40 is provided with a second via 41 and a third via 42. The second via 41 corresponds to the first via 31. The third via 42 and the second via 41 are spaced apart on the surface of the first dielectric layer 40. The metal field plate 50 is provided with a first electrical connection protrusion 51 and a second electrical connection protrusion 52. The first electrical connection protrusion 51 passes through the second via 41 and the first via 31 in sequence and is electrically connected to the voltage-resistant ring 20. The second electrical connection protrusion 52 passes through the third via 42 and is electrically connected to the polysilicon field plate 30.

Specifically, considering that a PN junction usually has a curved surface, the electric field at the curved junction is larger, which makes the semiconductor device 100 prone to breakdown at these locations. By arranging the polysilicon field plate 30 above the surface of the voltage-resistant ring 20, arranging the first dielectric layer 40 above the surface of the polysilicon field plate 30, and arranging the metal field plate 50 above the surface of the first dielectric layer 40, the main junction depletion region can be effectively widened outward, avoiding the electric field concentration phenomenon, and increasing the breakdown voltage, thereby further improving the voltage resistance of the terminal region 101 and even the semiconductor device 100.

Furthermore, by opening a first via 31 in the polysilicon field plate 30, a second via 41 is provided in the first dielectric layer 40, the first via 31 corresponds to the second via 41, and a first electrical connection protrusion 51 is provided on the metal field plate 50, so that the first electrical connection protrusion 51 can pass through the second via 41 and the first via 31 in sequence, and the first electrical connection protrusion 51 can be in contact with the voltage-resistant ring 20 for electrical connection, thereby realizing electrical connection between the metal field plate 50 and the voltage-resistant ring 20, so that the metal field plate 50 and the voltage-resistant ring 20 have the same electric potential.

Furthermore, by providing a third via hole 42 in the first dielectric layer 40 and correspondingly providing a second electrical connection protrusion 52 on the metal field plate 50, it is only necessary to make the second electrical connection protrusion 52 pass through the third via hole 42, so that the second electrical connection protrusion 52 can be in contact and electrically connected with the polysilicon field plate 30, thereby realizing electrical connection between the metal field plate 50 and the polysilicon field plate 30, and making the metal field plate 50 and the polysilicon field plate 30 have the same electric potential.

Among them, the third via hole 42 and the second via hole 41 are arranged at intervals on the surface of the first dielectric layer 40. In a specific embodiment of the present invention, the third via hole 42 and the second via hole 41 are arranged at intervals in the left-right direction of the first dielectric layer 40. In this way, it is necessary to extend the length of the polysilicon field plate 30 in the left-right direction accordingly, so that the polysilicon field plate 30 can correspond to the second via hole 41 and the third via hole 42, thereby increasing the area of the polysilicon field plate 30, improving the electric field modulation capability of the polysilicon field plate 30 on the terminal area 101, avoiding electric field concentration, and making the electric field distribution of the terminal area 101 more uniform, thereby further improving the breakdown voltage of the semiconductor device 100 and the withstand voltage capability of the semiconductor device 100.

Furthermore, the third via 42 and the second via 41 are spaced apart on the surface of the first dielectric layer 40, and the first electrical connection protrusion 51 and the second electrical connection protrusion 52 are also spaced apart on the metal field plate 50 accordingly. This not only facilitates the opening of the second via 41 and the first via 31 on the first dielectric layer 40, and facilitates the setting of the first electrical connection protrusion 51 and the second electrical connection protrusion 52 on the metal field plate 50, which can reduce the manufacturing difficulty, but also allows the first electrical connection protrusion 51 to penetrate the first via 31 and the second via 41, and the second electrical connection protrusion 52 to penetrate the third via 42 at the same time, which can improve the assembly efficiency.

In this way, the equipotential of the voltage-resistant ring 20, the polysilicon field plate 30 and the metal field plate 50 can be achieved, thereby avoiding the occurrence of a floating electric field due to the lack of interconnection among the structures, and avoiding the floating electric field being disturbed by the outside world when the semiconductor device 100 is working, resulting in uneven electric field distribution in the terminal area 101 and causing reduced voltage resistance and reliability. The voltage resistance capability of the semiconductor device 100 can be improved, and the reliability of the semiconductor device 100 can be improved.

Therefore, by allowing the first electrical connection protrusion 51 to penetrate the second via 41 and the first via 31 in sequence and be electrically connected to the voltage-resistant ring 20, and by allowing the second electrical connection protrusion 52 to penetrate the third via 42 and be electrically connected to the polysilicon field plate 30, the voltage-resistant ring 20, the polysilicon field plate 30 and the metal field plate 50 are made to have the same electric potential, thereby improving the voltage resistance and reliability of the semiconductor device 100.

1 to 4 , the second via 41 and the first via 31 are disposed above and within the boundaries of both sides of the voltage-resistant ring 20 , and both sides of the metal field plate 50 and the polysilicon field plate 30 extend out of the boundaries of both sides of the voltage-resistant ring 20 .

Specifically, by arranging the second via 41 and the first via 31 above the boundaries of the two sides of the voltage-resistant ring 20, after the first electrical connection protrusion 51 on the metal field plate 50 passes through the second via 41 and the first via 31 in sequence, it can directly contact and electrically connect with the voltage-resistant ring 20, and it can be ensured that the end of the first electrical connection protrusion 51 is in full contact with the voltage-resistant ring 20, thereby not only making it easier to realize the electrical connection between the metal field plate 50 and the voltage-resistant ring 20, but also ensuring that there is sufficient contact area between the metal field plate 50 and the voltage-resistant ring 20, and ensuring the stability of the electrical connection between the metal field plate 50 and the voltage-resistant ring 20, and thus more stably and reliably ensuring the equipotential between the metal field plate 50 and the voltage-resistant ring 20.

Furthermore, the two sides of the metal field plate 50 and the polysilicon field plate 30 are respectively extended out of the two side boundaries of the voltage-resistant ring 20, so that the electric field modulation capability of the metal field plate 50 and the polysilicon field plate 30 on the terminal area 101 can be improved, and the electric field concentration can be avoided, so that the electric field distribution of the terminal area 101 is more uniform, thereby further improving the breakdown voltage of the semiconductor device 100 and enhancing the voltage resistance capability of the semiconductor device 100.

As shown in combination with FIG3 and FIG4 , the aperture of the first via hole 31 is larger than the aperture of the second via hole 41. Specifically, the polysilicon field plate 30 is located below the first dielectric layer 40. During the production process, the first via hole 31 can be opened on the polysilicon field plate 30 first, and then the first dielectric layer 40 is set on the polysilicon field plate 30, and then the second via hole 41 is opened on the first dielectric layer 40 accordingly. By setting the aperture of the first via hole 31 larger than the aperture of the second via hole 41, it is possible to avoid affecting the morphology and size of the first via hole 31 when opening the second via hole 41, thereby ensuring the reliability of the polysilicon field plate 30 and even the semiconductor device 100.

Further, in combination with FIG3 , the first electrical connection protrusion 51 is circumferentially spaced apart from the inner wall of the first via hole 31 corresponding to the polysilicon field plate 30. Specifically, the first electrical connection protrusion 51 is sequentially penetrated through the first through hole and the second through hole, and by circumferentially spaced apart from the inner wall of the first via hole 31 corresponding to the polysilicon, the first electrical connection protrusion 51 can be conveniently penetrated through the first through hole 31, and damage to the inner wall of the first via hole 31 corresponding to the polysilicon field plate 30 can be avoided during the penetration of the first electrical connection protrusion 51, thereby improving the reliability of the semiconductor device 100.

As shown in FIG5 , the first via hole 31 is at least one of a square, a rectangle, a circle and a rhombus. Specifically, the design shape of the first via hole 31 can be at least one of a square, a rectangle, a circle and a rhombus. Correspondingly, the shape of the second via hole 41 and the shape of the cross section of the first electrical connection protrusion 51 can be designed, so that the shape of the first via hole 31 can be simple, the opening of the first via hole 31 and the second via hole 41, and the manufacture of the first electrical connection protrusion 51 can be facilitated, and the production difficulty of the semiconductor device 100 can be reduced.

Further, as shown in FIG. 5 , there are multiple first vias 31 , which are spaced apart on the upper surface of the polysilicon field plate 30 , and there are multiple first electrical connection protrusions 51 , which correspond one-to-one to the multiple first vias 31 .

Specifically, the first via 31 can be set to be multiple, and correspondingly, the first electrical connection protrusion 51 and the second via 41 can also be set to be multiple. By making the multiple first electrical connection protrusions 51 correspond to the multiple first vias 31 one by one, the multiple first electrical connection protrusions 51 can pass through the first via 31 and the second via 41, and contact and electrically connect with the voltage-resistant ring 20, so that the metal field plate 50 and the voltage-resistant ring 20 can have multiple electrical connections, thereby improving the stability and reliability of the electrical connection between the metal field plate 50 and the voltage-resistant ring 20, and can more stably and reliably ensure the equipotential between the metal field plate 50 and the voltage-resistant ring 20.

It should be noted that the plurality of first via holes 31 are arranged at intervals on the polysilicon field plate 30 , so as to ensure that the polysilicon field plate 30 remains intact after the holes are opened.

As shown in Figure 4, the semiconductor device 100 may also include a field oxide layer 60, which is arranged above the surface of the voltage-resistant ring 20 and at least partially located between the polysilicon field plate 30 and the voltage-resistant ring 20. The field oxide layer 60 is provided with a fourth via 61, and the fourth via 61 corresponds to the first via 31 and the second via 41. The first electrical connection protrusion 51 passes through the second via 41, the first via 31 and the fourth via 61 in sequence and is electrically connected to the voltage-resistant ring 20.

Specifically, there may be a field oxide layer 60 between the voltage-resistant ring 20 and the polysilicon field plate 30. The field oxide layer 60 can isolate the voltage-resistant ring 20 from the polysilicon field plate 30 and the first electrical connection protrusion 51 of the metal field plate 50, resulting in failure of the electrical connection between the voltage-resistant ring 20 and the metal field plate 50. By opening a fourth via 61 corresponding to the first via 31 and the second via 41 in the field oxide layer 60, the field oxygen between the polysilicon field plate 30 and the voltage-resistant ring 20 can be at least partially removed. After the first electrical connection protrusion 51 can pass through the second via 41, the first via 31 and the fourth via 61 in sequence, the first electrical connection protrusion 51 can be electrically connected to the voltage-resistant ring 20, that is, the contact electrical connection between the metal field plate 50 and the voltage-resistant ring 20 can be achieved, thereby ensuring the equipotential of the voltage-resistant ring 20 and the metal field plate 50.

Further, in combination with what is shown in FIG. 4 , the aperture of the fourth via 61 is equal to the aperture of the second via 41 . This not only ensures that the first electrical connection protrusion 51 can smoothly pass through the fourth via 61 , facilitating the electrical connection between the metal field plate 50 and the voltage-resistant ring 20 , but also facilitates the synchronous forming of the fourth via 61 and the second via 41 , thereby improving the production efficiency of the semiconductor device 100 .

As shown in FIG. 1 , the semiconductor device 100 includes an active region 102 and a transition region 103 . The transition region 103 is disposed between the active region 102 and the terminal region 101 . There are a plurality of pressure-resistant rings 20 , which are disposed at intervals.

Specifically, the active region 102 can bear most of the forward current during forward conduction and can also bear a high blocking voltage when a reverse voltage is applied. When a reverse voltage is applied to the semiconductor device 100, the terminal region 101 can alleviate the electric field crowding at the edge of the active region 102, thereby achieving the purpose of increasing the reverse breakdown voltage of the semiconductor device 100.

Considering that the terminal area 101 bears a relatively large voltage, multiple voltage-resistant rings 20 are arranged in the terminal area 101 and are arranged at intervals. In this way, the multiple voltage-resistant rings 20 can further optimize the electric field distribution of the terminal area 101 and increase the breakdown voltage of the terminal area 101, thereby improving the voltage resistance of the terminal area 101.

In some embodiments of the present invention, as shown in FIG1 , a polysilicon field plate 30 and a metal field plate 50 are correspondingly arranged above one of the plurality of voltage-resistant rings 20 that is far from the transition region 103. Specifically, one of the plurality of voltage-resistant rings 20 that is far from the transition region 103 bears the largest voltage, and by correspondingly arranging the polysilicon field plate 30 and the metal field plate 50 above it, the structure of the semiconductor device 100 can be simplified, and the production difficulty and production cost of the semiconductor device 100 can be reduced, while the voltage-resistant capability and reliability of the terminal region 101 can be improved.

In other embodiments of the present invention, a polysilicon field plate 30 and a metal field plate 50 are correspondingly disposed above at least one of the plurality of voltage-resistant rings 20. Specifically, a polysilicon field plate 30 and a metal field plate 50 may also be correspondingly disposed above at least one of the plurality of voltage-resistant rings 20, so that the number of polysilicon field plates 30 and metal field plates 50 can be increased, thereby further optimizing the electric field distribution of the terminal region 101, further improving the voltage-resistant capability of the terminal region 101 and even the semiconductor device 100, and improving the reliability of the semiconductor device 100.

Of course, whether a polysilicon field plate 30 and a metal field plate 50 are correspondingly arranged above one of the multiple voltage-resistant rings 20 that is away from the transition zone 103, or a polysilicon field plate 30 and a metal field plate 50 are correspondingly arranged above at least one of the multiple voltage-resistant rings 20, it is necessary to ensure the equipotential of the polysilicon field plate 30, the first dielectric layer 40 and the metal field plate 50, which will not be elaborated here.

In some embodiments of the present invention, there are multiple polysilicon field plates 30, and the multiple polysilicon field plates 30 are arranged at intervals. The multiple polysilicon field plates 30 are all provided with a first via 31, and a second dielectric layer is provided between two adjacent polysilicon field plates 30. The first vias 31 on the multiple polysilicon field plates 30 correspond to each other, and the second dielectric layer is provided with a fifth via, which corresponds to the first via 31. The first electrical connection protrusion 51 passes through the fifth via, the first via 31 and the second via 41 and is electrically connected to the voltage-resistant ring 20.

Specifically, when the terminal region 101 includes a plurality of polysilicon field plates 30 that are spaced apart and a second dielectric layer is disposed between the plurality of polysilicon field plates 30, first vias 31 corresponding to each other can be disposed on the plurality of polysilicon field plates 30, and a fifth via corresponding to the first via 31 can be disposed on the second dielectric layer, so that the first electrical connection protrusion 51 can simultaneously penetrate a plurality of fifth vias, a plurality of first vias 31 and a second via 41, and be electrically connected to the voltage-resistant ring 20, thereby realizing mutual electrical connection between the metal field plate 50 and the voltage-resistant ring 20, and the plurality of polysilicon field plates 30 can also be electrically connected to the metal field plate 50 by opening holes in the polysilicon field plate 30 and the second dielectric layer located above the polysilicon field plates 30, so that even if a plurality of polysilicon field plates 30 are contained, the improvement of the electric field distribution in the terminal region 101 can be ensured, and the voltage resistance and reliability of the semiconductor device 100 can be improved.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims (7)

1. A semiconductor device, comprising:

A drift layer of the first conductivity type;

A second conductivity type voltage-resistant ring provided at a portion of the drift layer corresponding to a terminal region of the semiconductor device;

The polycrystalline silicon field plate is arranged above the surface of the pressure-resistant ring and provided with a first via hole;

The first dielectric layer is arranged above the surface of the polysilicon field plate, a second via hole and a third via hole are formed in the first dielectric layer, the second via hole corresponds to the first via hole, and the third via hole and the second via hole are arranged on the surface of the first dielectric layer at intervals;

The metal field plate is arranged above the surface of the first dielectric layer, the metal field plate is provided with a first electric connection protrusion and a second electric connection protrusion, the first electric connection protrusion sequentially penetrates through the second through hole and the first through hole and is electrically connected with the pressure-resistant ring, and the second electric connection protrusion penetrates through the third through hole and is electrically connected with the polysilicon field plate;

the device comprises an active region and a transition region, wherein the transition region is arranged between the active region and the terminal region, a plurality of pressure-resistant rings are arranged at intervals, a plurality of well layers of a second conductive type are arranged on the transition region, the dimension of each well layer in the interval direction of the pressure-resistant rings is larger than that of each pressure-resistant ring in the direction, the polycrystalline silicon field plate and the metal field plate are correspondingly arranged above one part, which is only farthest from the transition region, of each pressure-resistant ring, a plurality of first through holes are arranged on the surface of the polycrystalline silicon field plate at intervals, a plurality of first electric connection protrusions are arranged on one side, which is far away from the active region, of each second through hole, and each third through hole is arranged on one side, which is far away from the active region, of each second through hole is provided with a plurality of first through holes.

2. The semiconductor device of claim 1, wherein the second via and the first via are disposed above within two side boundaries of the voltage-resistant ring, and two sides of the metal field plate and the polysilicon field plate extend beyond two side boundaries of the voltage-resistant ring, respectively.

3. The semiconductor device of claim 1, wherein a pore size of the first via is larger than a pore size of the second via.

4. The semiconductor device of claim 3, wherein the first electrical connection bumps are circumferentially spaced apart from the inner wall of the polysilicon field plate corresponding to the first vias.

5. The semiconductor device of claim 1, further comprising a field oxide layer disposed above the surface of the pressure resistant ring and between the polysilicon field plate and the pressure resistant ring, the field oxide layer being provided with a fourth via corresponding to the first via and the second via, the first electrical connection bump passing through the second via, the first via, and the fourth via in sequence and electrically connected to the pressure resistant ring.

6. The semiconductor device according to claim 5, wherein an aperture of the fourth via is equal to an aperture of the second via.

7. The semiconductor device according to claim 1, wherein the plurality of polysilicon field plates are arranged at intervals, the plurality of polysilicon field plates are each provided with a first via hole, a second dielectric layer is arranged between two adjacent polysilicon field plates, the first via holes on the plurality of polysilicon field plates correspond to each other, the second dielectric layer is provided with a fifth via hole, the fifth via hole corresponds to the first via hole, and the first electrical connection protrusion penetrates through the fifth via hole, the first via hole, the second via hole, and the voltage-resistant ring.