CN1171154C - Control chip set and data transaction method therebetween - Google Patents

Abstract

A method for controlling chip group and data transaction between them features that the data buffers in internal queue of each control chip in the control chip group have a fixed size and number, and the read-write command order sent out between chips is completely responded according to the read-write command order, so the control chip can master the use of buffer in internal queue of another control chip. The arbitration method of the bus between the control chip groups sets a certain control chip to normally master the control right of the inter-chip bus, but the other control chip enjoys higher bus priority and matches the inter-chip bus specification without waiting period. The data transaction efficiency of the control chip set is improved, and the types and the number of signal lines in the control chip set are simplified.

Description

Controls the method of data transactions between the chipset and

The invention relates to a chip set, in particular to a control chip set in a computer system, a method for controlling data transactions between chips in the chip set, and an arbitration method for controlling a bus between chips in the chip set.

What Fig. 1 depicts is exactly a kind of structure that uses PCI system in computer structure. The CPU 10 is coupled to the PCI bus 14 via a host bridge 12 . The PCI bus 14 can couple the main controller (master) of a plurality of PCI compatible peripheral devices, and it can be as shown in the figure adapter (graphic adapter) 16a, expansion bus bridge (expansion busbridge) 16b, network Adapter (LAN adapter) 16c and small computer system main bus adapter (SCSI host bus adapter) 16d etc. Each master controller can send a request signal (request, REQ) to request the use of the PCI bus 14, and the arbiter (arbiter) in the master bridge 12 can send a grant signal (grant, GNT) to the master controller, agreeing It uses the PCI bus 14 .

Data transmission between PCI compliant devices (such as a host controller or a north bridge in a computer chipset) is mainly controlled by the following adapter control signals. A cycle frame (FRAME) is sent by an initiator (which can be a master controller or a north bridge) to indicate the start and duration of an access operation. When the FRAME signal is sent out, it means that the data transaction (transaction) through the PCI bus starts, and when the FRAME signal is maintained at a low level, it means that the data transaction continues. At this point, the address bus AD will send a valid address (valid address) during the address phase, and will send a valid bus command (to satisfy PCI specification) is used to point out the data transaction type required by the initiator to the target device, wherein the command/byte enable line is encoded into 16 different commands with 4 bits, which are defined in detail in the PCI specification. Immediately after the valid address is sent, the address bus AD sends the data to be sent. This period is called the data phase. At the same time, the byte enable signal of the encoded bus command is sent on the CBE line to transfer the data. When the FRAME signal stops sending, it means that the transaction status is the last data transmission, or the data transmission has been completed. The initiator ready signal (initiator ready, IRDY) and the target device ready signal (target ready, TRDY) are used together to indicate that the initiator device and the target device are ready for data transmission. When a read operation is in progress, the IRDY signal indicates that the initiator is ready to receive data; while in a write operation, the TRDY signal indicates that the target device is ready to receive data. A stop signal (stop, STOP) is used to instruct the target device to request the initiator to stop the current data transaction behavior.

Referring to FIG. 2 , it shows an operation timing diagram when a read operation is performed by a PCI bus adapter. The period during which data transfer is performed and completed by the PCI bus is called a bus transaction cycle (bustransaction) 20, which includes an address phase (address phase) 22 and multiple data phases (data phase), such as 24a, 24b and 24c. Each data phase 24a/b/c is further divided into a wait cycle (wait cycle) 26a/b/c and a data transfer cycle (data transfer cycle) 28a/b/c. Next, with the timing diagram of FIG. 2 , a read operation is used as a simple description of the operation of the PCI system and the functions of the PCI specification control signals mentioned above.

During the cycle T1, the initiator (main controller) sends a REQ signal to require the main control PCI bus. At this time, if there are no other higher priority devices requiring the use of the PCI bus, then during the cycle T2, the main bridge ( Arbiter) sends a GNT signal to allow the initiator to master the PCI bus. During the cycle T3, the initiator sends a FRAME signal, indicating that a data transfer will begin, and sends a start address (start address) on the AD bus. To specify a target device, send a read command on the CBE line at the same time. Immediately following the sent read command, the CBE line will send a byte enable signal (byte enable), which will continue to be sent during the entire data phase (including 24a, 24b and 24c). In the period T4, the initiator sends a ready signal IRDY, indicating that the data can be sent, but the target device is not ready at this time. This period is the waiting period 26a of the data stage 24a, and the initiator waits for the target device Get your data ready. During cycle T5, the target device is ready and sends the ready signal TRDY, so the initiator reads data from the target device during the data transfer cycle 28a when both the IRDY and TRDY signals are sent. The target device sends a TRDY signal at the end of the period T6 to indicate the end of the data transmission and starts to prepare the second data, which is the waiting period 26a of the data phase 24b. During cycle T7, TRDY is sent again, indicating that the data is ready, and during the data transfer cycle 28b when both IRDY and TRDY signals are sent, the initiator reads data from the target device. When the initiator has no time to read the data, the initiator sends the IRDY signal at the end of the period T8. At this time, because the TRDY signal is still sent, the waiting period 26c is initiated by the initiator. After the initiator is ready, the IRDY signal is sent out again in the period T9. At this time, the initiator reads data from the target device during the data transfer cycle 28c when both the IRDY and TRDY signals are sent out. Since the initiator already knows that it does not need to read data any more during the cycle T9, the initiator ends sending the FRAME signal and the REQ signal, and the arbiter ends sending the GNT signal during the cycle T10. So far, a read operation is completed.

As mentioned above, in order to complete the data transactions of the PCI specification in the PCI specification, complicated control signals, waiting states and arbitration procedures must be used, and the signals specified by the PCI have at least 45-50 signal pins. The structure in the current personal computer is very similar to the system shown in Figure 1, wherein the main bridge 12 is exactly the north bridge chip of the control chipset in the motherboard, and the south bridge chip just includes the expansion bus bridge 16b, in the personal computer system The south bridge is a primary and necessarily present master. As for the graphics adapter add-on in the personal computer system, it is not connected to the PCI bus, but is connected to the North Bridge chip through an accelerated graphics port (AGP) adapter.

However, it is often not necessary to use such a complex function program as a general multi-purpose bus to control the data transactions between chips in the general chipset. The bus is such a complex program, and such a complex program may sacrifice a lot of performance characteristics in order to ensure that it can be applied to a variety of application environments. And with the trend of high integration, any control chip may combine more functions, for example, the CPU and the north bridge chip are combined into one chip, or the control chipset itself is combined into one chip, so that the pins on the chip package become A very precious resource that must be minimized to reduce the cost of the control chip. Therefore, in order to speed up data transactions between control chipsets and save chip pin resources, a special bus specification that simplifies but still satisfies data transactions between control chips is needed. For example: between the north and south bridges, a bus specification that simplifies multiple signal lines and is fast is designed, and the internal processing of this bus specification must be as close as possible to the general PCI specification, so as to be compatible with other modules in the chip and avoid too many control chips. Revise.

Therefore, the present invention proposes a control chip set, a data transaction method between chips in the control chip set, and an arbitration method for controlling the bus between chips in the chip set, so as to improve the efficiency of data exchange in the control chip set and simplify the control of the chip set. The type and quantity of the signal lines inside.

The present invention proposes a control chip set and a data transaction method between chips in the control chip set, so that the internal control chips of the control chip set can transmit data between the chips, and multiple commands or data can be transmitted continuously without any waiting period or stop Or retry (retry) situation, can save the time of using the bus, improve transmission efficiency.

The present invention proposes a control chip set and a method for controlling data transactions between chips in the chip set, which can save signal lines related to waiting state in the bus, signal lines related to the cycle length of data transactions, and signal lines related to stop and retry communication protocols, etc. .

The invention proposes an arbitration method for controlling the buses between chipsets, which can shorten the arbitration time when the bus is required.

The invention proposes an arbitration method for controlling the bus between chipsets, which can save signal lines related to bus grant.

The present invention provides a control chip set, including: a first control chip, including: a first data transmitter and receiver, coupled to an inter-chip bus, for receiving and sending data signals through the inter-chip bus to Complete multiple write transactions; a read/write data queue, coupled to the first data transmitter, for temporarily storing the data of these read/write transactions; a read/write transaction queue, coupled to The first data transceiver is used to temporarily store the data length and the read/write address of the read/write transactions; and a target controller is coupled to the read/write data queue and the read/write Write transaction queue, the target controller according to the read/write address corresponding to the read/write transaction first stored in the read/write transaction queue and the corresponding data in the read/write data queue , after sending the data to be read/written to a target device, the first data transmitter sends a read/write confirmation signal, and the read/write first stored in the current read/write transaction queue The read/write address corresponding to the write transaction and the corresponding data in the read/write data queue are released; and a second control chip, coupled to the first control chip via the inter-chip bus, Including: a read/write buffer size register, used to store the total number of data that can be accommodated in the read/write data queue; a read/write buffer count register, used to store the read/write transaction queue that can be accommodated /the total number of write transactions; a second data transmitter, coupled to the inter-chip bus, for receiving and sending data signals through the inter-chip bus, to complete the read/write transactions, when the After the second data transmitter receives the read/write confirmation signal, it sends a read/write successful release buffer signal; a write transaction generator is coupled to the second data transmitter for Generate the data length of these read/write transactions, read/write address and data; a read/write transaction recording circuit and queue, coupled to the second data transmitter and the read/write transaction generator , used to temporarily store the data lengths of the read/write transactions, and calculate the current usage of the read/write data queue in the first control chip according to the read/write successful release buffer signal The number of read/write buffer data and the number of read/write transactions to be used in the read/write transaction queue; and a read/write comparator, coupled to the second data transmitter, the read/write The write buffer size register, the read/write buffer count register, and the read/write transaction record circuit and queue are used to use the read/write buffer data number and the read/write transaction number to be used number, the total number of read/write transactions that the read/write transaction queue can accommodate, and the total number of data that can be accommodated in the read/write data queue, to notify the second data transmitter to send a new read/write transaction related data signals.

In the present invention, the data buffers of the internal queues of each control chip in the control chip set have a fixed size and quantity, and the order of reading and writing confirmation commands issued between the chips responds completely in accordance with the order of issuing read and write commands, so that the control chips can completely grasp The use of buffers in the internal queue of another control chip, when each command sent by the control chip, its relevant data must be prepared first, that is, all transactions between the control chipsets are transparent, thus saving the relevant data in the bus. Signal lines for wait states, signal lines for data transaction cycle length, and signal lines for stop-retry protocol, etc. And it can transmit multiple commands or data continuously without any waiting period, and there will be no stop or retry, which can save the time of using the bus and improve the transmission efficiency.

The arbitration method of the bus between the control chipsets of the present invention sets a certain control chip to normally control the bus between the chips, but another control chip enjoys a higher priority of the bus. The bus specification does not require the GNT signal line, which can quickly and accurately arbitrate the right to use the bus, shorten the time for arbitrating, and because the transaction requirements of the second control chipset are always approved, the entire transmission efficiency is improved.

In order to make the above-mentioned purposes, features, and advantages of the present invention more comprehensible, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Fig. 1 depicts a kind of known structure schematic diagram using PCI bus system in computer structure;

FIG. 2 shows a timing diagram of a read operation performed by a master controller of a PCI system, which is used to briefly illustrate various control signals of the PCI system;

FIG. 3 shows a schematic block diagram of a control chip set according to a preferred embodiment of the present invention;

FIG. 4 shows a timing relationship diagram between the transmitted data bit time (bit time), the bus clock pulse signal and the trigger signal line according to an embodiment of the present invention;

FIG. 5A shows a control chip set according to a preferred embodiment of the present invention, wherein a schematic block diagram of an internal structure related to write transactions;

FIG. 5B shows a control chip set according to a preferred embodiment of the present invention, wherein a related timing diagram related to writing transactions;

FIG. 6A shows a control chip set according to a preferred embodiment of the present invention, wherein the internal structure block diagram related to the read transaction; and

FIG. 6B shows a control chip set according to a preferred embodiment of the present invention, wherein a related timing diagram related to read transactions;

In order to propose a control chipset, a method for controlling data transactions between chips in the chipset, and an arbitration method for controlling the bus between chips in the chipset, which can improve the efficiency of controlling the data transactions of the chipset and simplify the control of signal lines in the chipset The type and quantity, that is, simplify the bus between control chips. The present invention takes the control chipset composed of the south bridge and the north bridge in the mainboard of the computer as an example, and redefines multiple command signals, which are called High Through-put Memory Link (HTML for short) to simplify the original complexity. PCI bus signals. In this preferred embodiment, the original signal lines between the south bridge and the north bridge need 45 signal lines, and the present invention replaces the original PCI bus signal lines with 15 command signal lines.

Referring to FIG. 3 and Table 1, wherein FIG. 3 is a schematic block diagram of a control chip set according to a preferred embodiment of the present invention, and FIG. 3 also shows the signal lines between the south bridge and the north bridge in the control chip set; and Table 1 details the meanings of these signal lines. As can be seen from FIG. 3 and Table 1, the control chip set of the present invention includes two control chips, the South Bridge 30 and the North Bridge 32, and the original 45 signal pins between the South Bridge 30 and the North Bridge 32 Simplified to 15, the extra pins can be provided for other purposes to enhance the functions of the control chipset.

As shown in Figure 3 and Table 1, between the south bridge 30 and the north bridge 32, the address data bus (AD bus) specified in the original PCI bus agreement specification is retained, but it is reduced to only 8 bidirectional signal lines, and others such as CBE , FRAME, IRDY, TRDY, STOP, DEVSEL, REQ and GNT and other signal lines are simplified into a bidirectional bit enable BE signal line, and the uplink command (up link command) UPCMD and uplink command driven by the south bridge 30 Link trigger (up link strobe) UPSTB; There is also a down link command (down link command) DNCMD driven by the north bridge 32, a down link strobe (down link strobe) DNSTB signal line, etc. The south bridge 30 and the north bridge 32 each drive an independent command signal line, which means that this preferred embodiment has a full-duplex command transmission function, and can each send a bus command at any time. And when the bus command is issued, if the right to use the bus is obtained, the address can be issued on the address data bus, and the length information of the current command can be issued on the BE signal line, or the data can be sent on the address data bus and sent on the BE signal line. The byte enable signal for this amount of data.

Table I Signal driver illustrate CLK 66Mhz clock signal DNSTB north bridge Downlink trigger UPSTB south bridge uplink trigger DNCMD north bridge Download link command UPCMD south bridge uplink command BE North Bridge/South Bridge byte enable AD[7:0] North Bridge/South Bridge address/data bus VREF reference voltage COMP Impedance comparison

Referring to FIG. 4 , it defines the timing relationship between the data bit transmission time of any data line of the present invention, the bus clock pulse signal and the trigger signal line. It can be seen from the figure that a clock cycle includes two clock pulse signals that trigger the STB, that is, the operating frequency of the uplink trigger signal line and the downlink trigger signal line is twice that of the clock pulse signal. The clock pulse frequency on the line. A total of four bit times 0 to 3 can be defined by using the rising and falling edges of the trigger signal. Using these four bit times, a total of 4 bits of data can be obtained and the bus command can be encoded. Therefore, with 8 data lines, 32 bits of data can be obtained in each clock cycle, and its effect is equivalent to that in the PCI bus, 32 data lines are transmitting data at the same time. And if the BE signal line represents length information, 1-16 (4 bits) data length information can be obtained in one clock cycle.

The uplink command UPCMD and the downlink command DNCMD define various data transaction types. The uplink command UPCMD driven by the south bridge 30 includes: north bridge to south bridge read confirmation command C2PRA, north bridge to south bridge write confirmation command C2PWA, south bridge to north bridge read command P2CR, south bridge to north bridge write command P2CW etc. The encoding relationship between it and the bit time is shown in Table 2. Please note that the REQ bus request signal is issued at bit time 0, and does not overlap with commands of other data transaction types. Therefore, at any time, even when sending a data transaction The REQ signal can be issued at the same time as the same clock cycle of the type command. The downlink command DNCMD driven by North Bridge 3 includes: North Bridge to South Bridge I/O Read Command C2PIOR, North Bridge to South Bridge Memory Read Command C2PMR, North Bridge to South Bridge I/O Write Command C2PIOW, North Bridge to South Bridge The memory write command C2PMW, south bridge to north bridge read confirmation command P2CRA, south bridge to north bridge write confirmation command P2CWA, the encoding relationship with the bit time is shown in Table 3. Please note that there is no signal definition related to GNT in this embodiment.

In the above commands, the commands issued by the South Bridge and the North Bridge chips correspond. When the South Bridge sends out multiple P2CR and/or P2CW commands in sequence, the North Bridge must respond to the corresponding P2CRA and/or commands in the order in which the South Bridge issued the commands. P2CWA command. After the North Bridge sends multiple C2PIOR, C2PMR, C2PIOW and C2PMW commands in sequence, the South Bridge must respond to the corresponding C2PRA and C2PWA commands in sequence. And in this embodiment, when each control chip issues a command, its related data must be prepared first. For example: when the south bridge sends P2CW, the data to be written must be prepared properly; when the north bridge sends P2CRA, the read data to be sent back must be fully prepared to avoid data pauses during data transmission Unable to continue.

Table 2 (uplink command UPCMD) bit time 0REQ bit time 1PMSTR Bit time 2MIO Bit time 3WR illustrate - 0 - 0 C2PRA - 0 - 1 C2PWA - 1 0 0 P2CR - 1 0 1 P2CW - 1 1 1 NOP 0 - - - REQ

Table 3 (download link command DNCMD) bit time 0 bit time 1PMSTR Bit time 2MIO Bit time 3WR illustrate - 0 0 0 C2PIOR - 0 0 1 C2PIOW - 0 1 0 C2PMR - 0 1 1 C2PMW - 1 0 0 P2CRA - 1 0 1 P2CWA - 1 1 1 NOP

FIG. 5A shows a control chip set according to a preferred embodiment of the present invention, wherein the internal structure block diagram related to the write transaction, refer to FIG. 5A . The control chipset of this preferred embodiment includes a first control chip and a second control chip, for example: the first control chip is the north bridge chip 500 , and the second control chip is the south bridge chip 600 . They are connected together through a special inter-chip bus, which is the HTML defined in the present invention. The north bridge chip 500 includes: a data transceiver 510 , a target controller 520 (for example: a memory controller 520 ), a write data queue 525 , and a write transaction queue 530 . The south bridge chip 600 includes: a data transceiver 610 , a write buffer size register 535 , a write buffer count register 540 , a write transaction generator 545 , a write transaction recording circuit and queue 550 , and a write comparator 555 .

The data transceiver 510 is directly connected to the HTML, and is a data transceiver controller conforming to the HTML adapter specification, capable of receiving and sending data signals through the HTML to complete multiple write transactions. Here we refer to as a write transaction that each time the south bridge chip 600 sends a P2CW command and related data, and the north bridge chip 500 responds to the P2CWA command corresponding to the P2CW command. The write data queue 525 can temporarily store the data of write transactions sequentially. The write transaction queue 530 sequentially temporarily stores the data lengths and write addresses of all write transactions. The depth of the write transaction queue 530 determines the number of write transactions that the Northbridge chip can process simultaneously, and the depth of the write data queue 525 determines the total number of data that the Northbridge chip can process write transactions. The target controller 520 will be about to write the target device (such as : After the data of the external memory is sent, the first data transceiver 510 will send a write confirmation signal (P2CWA command), and the write address corresponding to the write transaction first stored in the write transaction queue 530 at present is the same as The data length and the corresponding data in the write data queue 525 will be released, that is, the storage locations temporarily storing these data in the queue can be filled with other data.

The write buffer count register 540 and the write buffer size register 535 in the south bridge chip 600 respectively store the total number of write transactions that can be accommodated by the write transaction queue 530 in the north bridge chip 500 and the total number of data that can be accommodated by the write data queue 525, In this embodiment, the total number of write transactions that can be accommodated by the write transaction queue 530 is 4, and the total number of data that can be accommodated by the write data queue 525 is 16. These two numbers can be set by the basic input and output system when starting up, and can also be fixed when designing the chip.

The data transmitter 610 is also coupled to the HTML, and can receive and send data signals through the HTML to complete all write transactions, and when the data transmitter 610 receives the P2CWA command, it will send a write success release buffer The register signal is sent to the write transaction recording circuit and the queue 550, which can be used to release the storage location in the queue that stores the data length corresponding to the write transaction. When the write transaction generator 545 generates the data length of a new write transaction, and writes the address and data, the data length will also be sent to the write transaction recording circuit and the queue 550 .

The write transaction recording circuit and queue 550 can calculate the number of all write buffer data to be used in the write data queue 530 and the number of all write transactions to be used in the write transaction queue 525 in the current north bridge chip 500 . This is because the data lengths of all write transactions are temporarily stored sequentially in the write transaction recording circuit and the queue 550, and because the Northbridge chip 500 sends out the P2CWA command to respond completely in accordance with the order in which the Southbridge chip 600 sends out the P2CW command, the Southbridge The chip 600 can fully grasp the usage of the buffers in the internal queue of the north bridge chip 500 .

The write transaction recording circuit and the queue 550 will send all the data numbers of the write buffer data about the write data queue 530 and the write transaction numbers of the write transaction queue 525 to the write comparator 555, and the write comparator 555 compares the above-mentioned information with the total amount of data that can be accommodated in the write data queue 525 stored in the write buffer size register 535, and the total number of write transactions that can be accommodated in the write transaction queue 530 stored in the write buffer count register 540, if both If neither of them exceeds the total number that can be accommodated, the data transmitter 610 can be notified to send a data signal related to a new write transaction.

Referring to FIG. 5B , it is assumed that at clock pulse T1, the south bridge chip obtains the right to use the address data bus and starts the first write transaction. The south bridge chip sends the write command P2CW in the uplink command UPCMD, sends the address ADDR written in on the address data bus AD, and sends the length LEN=2 to be written on the byte enable BE, and at the time of the clock pulse T2 , the south bridge chip sends the first data to be written on the AD, and sends the byte enable of the first data on the BE, and then sends the second write data at the clock pulse T3. At this time, there is an unfinished write transaction in the north bridge chip. Because the south bridge chip knows the number of write transactions that the north bridge chip can accept at the same time and the size of the write data queue, it can judge whether the north bridge chip can accept new write transactions. If the north bridge chip still has empty write transaction queue 530 and write data queue 525 available, the south bridge chip can start the second write transaction again at clock pulse T4, and there are two unfinished writes in this moment in the north bridge chip affairs. The south bridge chip judges whether the third write transaction can be started at T9. When the south bridge chip finds that the write transaction for the third time will cause the write transaction queue 530 or the write data queue 525 of the north bridge chip to overflow without the write transaction queue 530 of the north bridge chip or the write data queue 525 overflowing and cannot processing, the south bridge chip cannot initiate the third write transaction at the clock pulse T9. After the Northbridge chip completely writes the data of the first write transaction into the memory via the memory controller, it sends a write confirmation command in the downlink command DNCMD at the clock pulse T9, telling the Southbridge chip to write the transaction for the first time (length LEN=2) Completed. The south bridge chip knows that the available write transaction queue 530 in the north bridge chip increases by one, and the available write data queue 525 increases by two. The south bridge chip receives the leakage confirmation command from the north bridge chip and knows that the first write transaction has been completed. The related write transaction queue 530 and the write data queue 525 have been released, and it is judged that the north bridge chip can receive the third write transaction, and the third write transaction starts at the clock pulse T12.

FIG. 6A is a schematic block diagram of the internal structure of a read transaction in a control chip set according to a preferred embodiment of the present invention. Refer to Figure 6A. The control chip set of this preferred embodiment includes a north bridge chip 500 and a south bridge chip 600 . They are connected together through a special inter-chip bus, which is the HTML defined in the present invention. The north bridge chip 500 includes: a data transceiver 510 , a target controller 520 (for example: a memory controller 520 ), a read data queue 625 , and a read transaction queue 630 . The south bridge chip 600 includes: a data transceiver 610 , a read buffer size register 635 , a read buffer count register 640 , a read transaction generator 645 , a read transaction recording circuit and queue 650 , and a read comparator 655 .

The data transceiver 510 is directly connected to the HTML, and is a data transceiver controller conforming to the HTML adapter specification, capable of receiving and sending data signals through the HTML to complete multiple read transactions. Here we refer to as a readout transaction every time the south bridge chip 600 sends a P2CR command and the north bridge chip 500 responds to the P2CRA command and related data corresponding to the P2CR command. The read data queue 625 can temporarily store the data of read transactions sequentially. The read transaction queue 630 sequentially temporarily stores the data lengths and read addresses of all read transactions. The depth of the read transaction queue 630 determines the number of read transactions that the Northbridge chip can process simultaneously, and the depth of the read data queue 625 determines the number of data that the Northbridge chip can process for read transactions. The target controller 520 reads the data from the target device (such as external memory) according to the read address and data length corresponding to the read transaction first stored in the read transaction queue 630, and stores it in the read data queue 625 middle. Then, the first data transceiver 510 will send out the read confirmation signal (P2CRA command) and the data in the read data queue 625 corresponding to the read transaction first stored in the read transaction queue 630, and is currently in the read transaction queue 630 The corresponding read-out address and data length of the read-out transaction first stored in the read-out transaction, as well as the corresponding data in the read-data queue 625, will be released, that is, the buffers temporarily storing these data in the queue can be filled with other buffers. data.

The read buffer count register 640 and the read buffer size register 635 in the south bridge chip 600 respectively store the total number of read transactions that can be accommodated by the read transaction queue 630 in the north bridge chip 500 and the total number of data that can be accommodated by the read data queue 625, In this embodiment, the total number of read transactions that can be accommodated by the read transaction queue 630 is 4, and the total number of data that can be accommodated by the read data queue 625 is 16. These two numbers can be set by the basic input and output system when starting up, and can also be fixed when designing the chip.

The data transceiver 610 is also coupled to the HTML, and can receive and send data signals through the HTML to complete all read transactions, and when the data transceiver 610 receives the P2CRA command, in addition to corresponding to the P2CRA command The data of the read transaction is sent to the read transaction generator 645, which also sends a read successful release buffer signal to the read transaction record circuit and the queue 650, which can be used to release the storage corresponding to the data length of the read transaction in the queue. Location. When the read transaction generator 645 generates the data length and read address of a new read transaction, it will also send the data length to the read transaction recording circuit and the queue 650 .

The read transaction recording circuit and the queue 650 can calculate the number of all read buffer data to be used in the read data queue 630 and the number of all read transactions to be used in the read transaction queue 625 in the current north bridge chip 500 . This is because the data lengths of all read transactions are temporarily stored sequentially in the read transaction recording circuit and the queue 650, and because the North Bridge chip 500 sends the P2CRA command to respond in the order in which the South Bridge chip 600 sends the P2CR command, the South Bridge The chip 600 can fully grasp the usage of the buffers in the internal queue of the north bridge chip 500 .

The read transaction recording circuit and queue 650 will send all the data numbers of the read buffers to be used in the read data queue 630 and the number of all read transactions to be used in the read transaction queue 625 to the read comparator 655 . The read comparator 655 compares the above information with the total amount of data that can be accommodated in the read data queue 625 stored in the read buffer size register 635 and the total number of read transactions that can be accommodated in the read transaction queue 630 stored in the read buffer count register 640 , if both do not exceed the accommodated total, the data transmitter 610 may be notified to send a new read transaction-related data signal.

Referring to FIG. 6B , it is assumed that at clock pulse T1, the south bridge chip obtains the right to use the address data bus and starts the first read transaction. The south bridge chip sends the read command P2CR in the uplink command UPCMD, sends the read address ADDR on the address data bus AD, and sends the length LEN=2 to be read on the byte enable BE. At this time, there is an unfinished read transaction in the north bridge chip, because the south bridge chip knows the number of read transactions that the north bridge chip can accept at the same time and determines the size of the data queue, so it can judge whether the north bridge chip can accept new read transactions affairs. If the north bridge still has empty read transaction queue 630 and read data queue 625 available, the south bridge chip can start the second read transaction (length LEN=3) again at clock pulse T2, now there are two in the north bridge chip For an unfinished read transaction, the south bridge chip judges that the third read transaction will be launched when the clock pulse T3 will make the read transaction queue 630 or the read data queue 625 of the north bridge chip overflow and cannot be processed, so the south bridge The chip cannot start the third read transaction at clock pulse T3. After the north bridge chip obtains the data of the first read transaction through the memory controller and stores it in the read data queue 625, it initiates a read confirmation command to send the read data back to the south bridge. At clock pulse T7, the north bridge chip obtains the right to use the address data bus, sends the read confirmation command P2CRA in the downlink link command DNCMD, and sends the first data of the first read transaction on the address data bus. The second data is sent at clock pulse T8. At this time, the south bridge chip knows that the read transaction queue 630 and the read data queue 625 related to the first read transaction have been released, and re-determines whether the third read can be initiated. Order. Before launching the third read command, the south bridge chip must obtain the right to use the address data bus, so the uplink command UPCMD is used to send REQ at the clock pulse T10 to request the use of the bus to the north bridge chip. The north bridge chip sends out the data of the second read command through the read confirmation command during the clock pulse T9-T10-T11. The south bridge chip obtains the right to use the bus at the time of the clock pulse T13, and initiates the second read command.

The embodiments of the present invention described in above-mentioned Fig. 5A, 5B and Fig. 6A, 6B are all examples that the first control chip is a north bridge chip, and the second control chip is a south bridge chip, and the south bridge chip actively issues commands to control the north bridge chip to read and write data. As those skilled in the art can easily know, as long as there is a corresponding structure in the north and south bridges, the south bridge chip is not limited to actively issue commands, that is, the first control chip can be the south bridge chip, and the second control chip can be the north bridge chip chip.

5A, 5B and 6A, 6B are just an embodiment, and should not be used to limit the present invention. The spirit of the present invention is:

1. When starting a write or read transaction, in addition to sending the address and command, it also sends the length of the data to be written or read, so you can know when the transaction ends without FRAME.

2. When there are multiple write or read transactions waiting to be completed, the write or read confirmation commands correspond to the previous write or read commands in sequence, so you can know the usage of the internal queue of the other chip, and then judge the restart A new write or read command, that is to say, flow control is done by the chip that initiates the write or read command, and the chip that receives the write or read command never receives it will overflow the internal queue command, so there is no need to do flow control.

3. The scope of application should not be limited to the north and south bridge chips, but should be applicable to data transmission between any two chips.

In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined in the claims.

Claims (9)

1. control chip group comprises:

One first control chip comprises:

One first data are sent the receipts device, are coupled to a chip chamber bus, in order to by this chip chamber bus, receive and the transmission data-signal, finish a plurality of affairs that write;

One read/write data formation is coupled to these first data and send the receipts device, reads/write the data of affairs in order to temporary those;

One read/write transaction formation is coupled to these first data and send the receipts device, reads/writes the data length of affairs and read/write the address in order to temporary those; And

One target controller, be coupled to this read/write data formation and this read/write transaction formation, this target controller reads/write according to what deposits at first in this read/write transaction formation at present that affairs are pairing reads/write the address and pairing data in this read/write data formation, after the data of reading/writing a destination apparatus with being about to are sent, these first data are sent and are received device and send one and read/write entry confirmation signal, and deposit at first in this read/write transaction formation at present read/write affairs are pairing read/write the address and in this read/write data formation pairing data all be released; And

One second control chip is coupled to this first control chip via this chip chamber bus, comprising:

One read/write buffers sized registers, in order to store this read/write data formation can hold the sum of data;

One read/write buffers counter register, in order to store this read/write transaction formation can hold the sum of reading/write affairs;

One second data are sent the receipts device, are coupled to this chip chamber bus, in order to pass through this chip chamber bus, receive and the transmission data-signal, finish those and read/write affairs, when these second data send receive device receive this read/write entry confirmation signal after, send one and read/write successfully buffer release device signal;

One writes the affairs generator, is coupled to these second data and send the receipts device, reads/write the data length of affairs in order to produce those, reads/write address and data;

One read/write transaction writing circuit and formation, be coupled to these second data and send receipts device and this read/write transaction generator, read/write the data length of affairs in order to temporary those, and read/write successfully buffer release device signal according to this, calculating one of this read/write data formation in this first control chip at present will will be with reading/write the affairs number with one of read/write buffers data number and this read/write transaction formation; And

One read/write comparer, be coupled to these second data and send receipts device, this read/write buffers sized registers, this read/write buffers counter register and this read/write transaction writing circuit and formation, in order to according to this will with read/write buffers data number, this will with read/write affairs number, this read/write transaction formation can hold the sum that the sum of reading/write affairs and this read/write data formation institute can hold data, notify these second data to send to receive device to send new read/write and go into the data-signal that affairs are correlated with.

2. control chip group as claimed in claim 1, wherein this chip chamber bus comprises: an address data bus, one length/byte enable signal line, a up-link command signal line, a up-link line trigger signal, once pass the link command signal wire, pass a link line trigger signal and a time clock signal wire once.

3. control chip group as claimed in claim 2, the operation frequency when wherein this up-link line trigger signal and this time pass the actuating of link line trigger signal is 2 times of clock frequencies on this clock pulse signal line.

4. control chip group as claimed in claim 1, wherein this first is respectively the north bridge control chip and the south bridge control chip of computer main frame panel with this second control chip, and this target controller is a Memory Controller, and this destination apparatus is an external memory storage.

5. control chip group as claimed in claim 4, wherein this read/write transaction formation can hold read/write affairs add up to 4, this read/write data formation can hold data add up to 16.

6. the data transactions method between the control chip group, in order to finish a plurality of reading/write affairs, this control chip group comprises one first control chip and one second control chip, and this first control chip comprises a read/write data formation, reads/write the data of affairs in order to temporary those; An and read/write transaction formation, read/write the data length of affairs and read/write the address in order to temporary those, this second control chip comprises that keeping in those reads/write a read/write transaction writing circuit and the formation and a read/write comparer of the data length of affairs, and this data transactions method comprises the following steps:

By the chip chamber bus provide this read/write transaction formation can hold read/write go into affairs the sum and this read/write data formation can hold the sum of data to second control chip;

This first control chip according to deposit at first in this read/write transaction formation at present read/write affairs are pairing read/write the address and in this read/write data formation pairing data, the data of reading/writing a destination apparatus with being about to are read/are write out;

This first control chip is sent one and is read/write entry confirmation signal;

This first control chip discharges reading/writing of depositing at first in this read/write transaction formation at present, and affairs are pairing reads/write the address and pairing data in this read/write data formation;

This second control chip produces corresponding one and newly reads/write the data length of affairs, reads/write address and data;

Entry confirmation signal is read/write to this second control chip according to this, make this read/write transaction writing circuit and formation, calculating one of this read/write data formation in present this first control chip will will be with reading/write the affairs number with one of read/write buffers data number and this read/write data formation; And

This read/write comparer according to this will with read/write buffers data number, this will with read/write affairs number, this read/write transaction formation can hold the sum that the sum of reading/write affairs and this read/write data formation institute can hold data, decide and make this second control chip to send this new reading/write the relevant data length of affairs and read/write address and data.

7. the data transactions method between the control chip group as claimed in claim 6, wherein this first with this second control chip be to couple by a chip chamber bus, this first is respectively the north bridge control chip and the south bridge control chip of computer main frame panel with this second control chip, and this chip chamber bus comprises: an address data bus, one length/byte enable signal line, a up-link command signal line, a up-link line trigger signal, once pass the link command signal wire, pass a link line trigger signal and a time clock signal wire once.

8. the data transactions method between the control chip group as claimed in claim 7, the operation frequency when wherein this up-link line trigger signal and this time pass the actuating of link line trigger signal is 2 times of clock frequencies on this clock pulse signal line.

9. the data transactions method between the control chip group as claimed in claim 7, wherein this destination apparatus is an external memory storage.

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