CN117075703A - Power supply control system and control method - Google Patents
Power supply control system and control method Download PDFInfo
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- CN117075703A CN117075703A CN202210499784.1A CN202210499784A CN117075703A CN 117075703 A CN117075703 A CN 117075703A CN 202210499784 A CN202210499784 A CN 202210499784A CN 117075703 A CN117075703 A CN 117075703A
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Abstract
The application discloses a power supply control system and a control method. The system comprises: the system comprises a central processing unit CPU, an integrated south bridge PCH module, a micro control unit MCU module and a plurality of power supply modules; the PCH module is respectively connected with the CPU module and the MCU module; the power supply module is used for supplying power to at least one of the CPU, the PCH module and the MCU module; the CPU is used for providing first power supply time sequence information for the MCU module, and the first power supply time sequence information is used for representing candidate power supply time sequences of the power supply modules provided by the CPU; the PCH module is used for providing second power supply time sequence information for the MCU module, and the second power supply time sequence information is used for representing candidate power supply time sequences of the power supply modules provided by the PCH module; the MCU module is used for determining a first power supply time sequence of at least one power supply module of the plurality of power supply modules according to at least one of the acquired first power supply time sequence information and second power supply time sequence information and controlling the at least one power supply module to supply power according to the first power supply time sequence. The application solves the technical problem of fixed power supply time of the power supply caused by the fact that the power supply enabling signal is based on the logic fixed delay output in the Super IO chip.
Description
Technical Field
The application relates to the field of power supply control, in particular to a power supply control system and a control method.
Background
In the related art, the computer module architecture of commercial display mainly includes a CPU (center processing unit, central processing unit), a PCH (platform controller Hub, integrated south bridge) and a Super IO chip. The three parts commonly control a plurality of power supply modules (the power supply modules are used for supplying power to at least a CPU, a PCH module and a Super IO chip) so as to meet the time sequence requirements of the CPU and the PCH on each power supply module. The specific control flow process is as follows: after the Super IO chip acquires the CPU power state signal, the Super IO chip sends out a power enabling signal through a logic pin in the Super IO chip so as to open a corresponding power supply module. However, since the power enable signal is output based on the fixed delay of the logic pin in the Super IO chip, the power supply module has fixed on-time and low accuracy. In addition, the computer module of the commercial display also comprises an MCU (microcontroller unit, micro control unit). However, the MCU is only used for interacting with the whole large-screen display and is not used for controlling the opening and closing time of the power supply module.
In view of the above problems, no effective solution has been proposed at present.
Disclosure of Invention
The embodiment of the application provides a power supply control system and a control method, which at least solve the technical problem of fixed power supply time caused by the fact that a power supply enabling signal is based on the fixed delay output of a logic pin in a Super IO chip.
According to an aspect of an embodiment of the present application, there is provided a power supply control system including: the system comprises a central processing unit CPU, an integrated south bridge PCH module, a micro control unit MCU module and a plurality of power supply modules; the PCH module is respectively connected with the CPU module and the MCU module; the power supply module is used for supplying power to at least one of the CPU, the PCH module and the MCU module; the CPU is used for providing first power supply time sequence information for the MCU module, and the first power supply time sequence information is used for representing candidate power supply time sequences of the power supply modules provided by the CPU; the PCH module is used for providing second power supply time sequence information for the MCU module, and the second power supply time sequence information is used for representing candidate power supply time sequences of the power supply modules provided by the PCH module; the MCU module is used for determining a first power supply time sequence of at least one power supply module of the plurality of power supply modules according to at least one of the acquired first power supply time sequence information and second power supply time sequence information and controlling the at least one power supply module to supply power according to the first power supply time sequence.
Optionally, the MCU module includes: a processor, a memory and a general purpose input/output GPIO interface; the memory and the GPIO interface are connected with the processor; a processor for calling a program stored in the memory to perform the steps of: determining a first power supply timing according to at least one of the first power supply timing information and the second power supply timing information; and the GPIO interface is used for outputting an enabling signal to the at least one power supply module so as to control the at least one power supply module to supply power according to the first power supply time sequence.
Optionally, the MCU module further includes a timer connected to the processor for providing timing information to the processor; the processor is further used for determining the output time of the enabling signal according to the first power supply time sequence and timing information provided by the timer, and outputting the enabling signal at the output time to control the at least one power supply module to supply power according to the first power supply time sequence.
Optionally, the MCU module is further configured to receive power supply timing adjustment information after determining the first power supply timing, adjust the first power supply timing according to the power supply timing adjustment information, and control at least one power supply module to supply power according to the adjusted first power supply timing.
Optionally, the MCU module is further configured to obtain power supply states of the multiple power supply modules through GPIO interfaces of the MCU module; wherein, the power supply state includes: whether the power supply module supplies power or not; the power control system further includes: and the display equipment is connected with the MCU module and used for displaying the power supply states of the power supply modules.
Optionally, the MCU module is further configured to receive a power control instruction sent by an external device through a communication interface in the MCU module, where the remote power control instruction is configured to control a power supply state of the multiple power supply modules; and under the condition that the power control instruction is received, controlling the power supply modules to supply power according to the power control instruction, wherein the priority of the MCU module responding to the power control instruction is higher than that of the MCU module responding to the first power supply time sequence.
Optionally, the MCU module determines an output time of the enable signal according to the first power supply timing sequence and timing information provided by a timer in the MCU module, and outputs the enable signal at the output time to control at least one power supply module to supply power according to the first power supply timing sequence. According to another aspect of the embodiment of the present application, there is also provided a control method applied to a power control system, the control system including: the control system comprises: the system comprises a central processing unit CPU, an integrated south bridge PCH module, a micro control unit MCU module and a plurality of power supply modules; the PCH module is respectively connected with the CPU module and the MCU module; the power supply module is used for supplying power to at least one of the CPU, the PCH module and the MCU module; the control method comprises the following steps: the MCU module acquires first power supply time sequence information provided by the CPU and second power supply time sequence information provided by the PCH module, wherein the first power supply time sequence information is used for representing candidate power supply time sequences of a plurality of power supply modules provided by the CPU, and the second power supply time sequence information is used for representing candidate power supply time sequences of a plurality of power supply modules provided by the PCH module; the MCU module determines a first power supply time sequence of at least one power supply module of the plurality of power supply modules according to at least one of the first power supply time sequence information and the second power supply time sequence information; the MCU module controls at least one power supply module to supply power according to the first power supply time sequence.
Optionally, the method further comprises: after the first power supply time sequence is determined, the MCU module receives power supply time sequence adjustment information and modifies the first power supply time sequence according to the power supply time sequence adjustment information.
Optionally, the method further comprises: the MCU module controls the power supply modules to supply power according to the power supply control instruction according to the received power supply control instruction, and the priority of the MCU module responding to the power supply control instruction is higher than that of the MCU module responding to the first power supply time sequence.
In the embodiment of the application, a Central Processing Unit (CPU), an integrated south bridge PCH module, a Micro Control Unit (MCU) module and a plurality of power supply modules are adopted; the PCH module is respectively connected with the CPU module and the MCU module; the power supply module is used for supplying power to at least one of the CPU, the PCH module and the MCU module; the CPU is used for providing first power supply time sequence information for the MCU module, and the first power supply time sequence information is used for representing candidate power supply time sequences of the power supply modules provided by the CPU; the PCH module is used for providing second power supply time sequence information for the MCU module, and the second power supply time sequence information is used for representing candidate power supply time sequences of the power supply modules provided by the PCH module; the MCU module is used for determining the first power supply time sequence of at least one power supply module in the plurality of power supply modules according to at least one of the acquired first power supply time sequence information and second power supply time sequence information, controlling the at least one power supply module to supply power according to the first power supply time sequence, and setting the power supply time sequence of the power supply module by directly utilizing the MCU module according to the first power supply time sequence information provided by the CPU and the second power supply time sequence information provided by the PCH module, so that the purpose of flexibly setting the power supply time sequence is achieved, the technical effect of accurately controlling the power supply time sequence is achieved, and the technical problem of power supply time fixation caused by the fact that a power supply enabling signal is output based on the fixed delay of logic pins in the Super IO chip is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a schematic diagram of an alternative power control system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another alternative computer power control system according to an embodiment of the application;
FIG. 3 is a control system schematic diagram of an alternative computer power control system in the related art;
FIG. 4 is a control flow diagram of an alternative power control system of the related art;
FIG. 5 is a schematic diagram of yet another alternative computer power control system in accordance with an embodiment of the application;
FIG. 6 is a control flow diagram of an alternative computer power control system according to an embodiment of the application;
fig. 7 is a schematic diagram of a control method of an alternative power control system according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a power control system according to an embodiment of the present application, as shown in fig. 1, the system includes: a Central Processing Unit (CPU) 10, an integrated south bridge PCH module 12, a Micro Control Unit (MCU) module 14 and a plurality of power supply modules 16; the power supply module 16 is configured to supply power to at least one of the CPU10, the PCH module 12, and the MCU module 14; a CPU10 for providing MCU module 14 with first power supply timing information for characterizing candidate power supply timings of a plurality of power supply modules 16 provided by CPU 10; the PCH module 12 is configured to provide second power timing information, where the second power timing information is configured to characterize candidate power supply timings of the plurality of power supply modules 16 provided by the PCH module 12; the MCU module 14 is configured to determine a first power supply timing of at least one power supply module 16 of the plurality of power supply modules 16 according to at least one of the first power supply timing information and the second power supply timing information, and control at least one power supply module 16 of the plurality of power supply modules 16 to supply power according to the first power supply timing; at least one power module 16 of the plurality of power modules 16 is configured to power at least one of the CPU10, PCH module 12, and MCU module 14.
Through the system, the power supply time sequence of the power supply module 16 can be determined by directly utilizing the MCU module 14 according to the first power supply time sequence information provided by the CPU10 and the second power supply time sequence information provided by the PCH module 12, so that the purpose of flexibly setting the power supply time sequence is achieved, the technical effect of accurately controlling the power supply time sequence is achieved, and the technical problems of power supply sequence and time fixation caused by the fact that a power supply enabling signal is output based on internal logic fixed delay are solved.
It should be noted that, the first power timing information may be a requirement of the CPU10 on a power supply timing, or may be a power timing signal sent by the CPU10 to the outside, for example, a range of the requirement of the CPU10 on the power supply timing is that a time interval from the start of power supply of the first power supply module 16 to the start of power supply of the second power supply module 16 after receiving the power-on signal is within 0us-100 us; the time interval between the start of power supply by the second power supply module 16 and the start of power supply by the third power supply module 16 is 0ms-1 ms. The second power timing information may be a requirement of the PCH module 12 on the power supply timing, or may be that the PCH module 12 sends a power supply timing signal to the outside, similar to the CPU10, which is not described herein again.
It will be appreciated that in some alternative embodiments the CPU10 and PCH module 12 may be directly connected to the MCU module 14 via either the first interface or the second interface.
In some embodiments of the present application, as shown in FIG. 2, MCU module 14 includes: a processor 201, a memory 202, and a general purpose input output GPIO interface 204; wherein the memory 202 is connected to the processor 201; GPIO interface 204 is coupled to processor 201; a processor 201, configured to call a program stored in the memory 202 to perform the following steps: determining a first power supply timing of the plurality of power supply modules 16 according to at least one of the first power supply timing information and the second power supply timing information; a timer 203 for providing a timing function for the processor; the GPIO interface 204 is configured to output an enable signal to the plurality of power supply modules 16 according to a first power supply timing sequence of the plurality of power supply modules 16 to control at least one power supply module 16 of the plurality of power supply modules 16 to supply power according to the first power supply timing sequence.
In the related art, a logic pin in the Super IO chip is used to fix and output a power enable signal to control a power supply time sequence, and when the power supply time sequence is adjusted, the hardware connection is changed to adjust the power supply time sequence, which involves the change of hardware equipment. In the embodiment of the application, the MCU module 14 is utilized to adjust the power supply time sequence, and the power supply time sequence can be directly adjusted by changing the setting of software, so that the setting and changing of the power supply time sequence are more convenient and accurate.
In some embodiments of the application, the MCU module further comprises: a timer 203 coupled to the processor 201; a timer 203 for providing the processor 201 with the timing information; the processor 201 is further configured to determine a time when the enable signal is output to the power supply modules 16 according to the first power supply timing and the timing information provided by the timer 203, and output the enable signal according to the time when the enable signal is output by the power supply modules 16 to control the power supply of the power supply modules 16.
In an alternative manner, the time interval from when the first power supply module 16 starts to supply power to the second power supply module 16 is 0us-100us, the timer 203 provides timing information to the processor 201, and the processor 201 determines that the interval 100us is within using the received timing information, for example, after outputting the enable signal 80us to the first power supply module 16, outputs the enable signal to the second power supply module 16 to control the second power supply module 16 to supply power.
In some embodiments of the present application, the MCU module 14 is further configured to receive power supply timing adjustment information after determining the first power supply timing; and modifies the first power supply timing according to the power supply timing adjustment information and controls the at least one power supply module 16 to supply power according to the adjusted first power supply timing.
It should be noted that, the power supply timing adjustment information may be written into the software program at any time according to actual requirements and stored in the memory 202.
In some optional manners, the first power supply time sequence is determined according to the requirements of the CPU and the PCH on the power supply time sequences, the first power supply time sequence can be stored in the memory 202 in a pre-written program manner, and the processor 201 controls the corresponding power supply module 16 to supply power according to the pre-stored power supply time sequence.
In some embodiments of the present application, the GPIO interface 204 is further configured to output an enable signal to at least one power supply module 16 of the plurality of power supply modules 16 according to the adjusted first power supply timing sequence to control the at least one power supply module 16 to supply power according to the second power supply timing sequence.
In some embodiments of the present application, the MCU module 14 is further configured to obtain power states of the plurality of power supply modules 16 through the GPIO interface 204; wherein, the power supply state includes: the power module 16 is powered. And transmits the power supply status of the plurality of power supply modules 16 to a display device in the power control system for presentation.
In some alternatives, the current state of the computer may be determined by the power states of the plurality of power modules 16, such as power on and power off.
In some embodiments of the present application, the MCU module 14 is further configured to receive a power control instruction sent by an external device through the communication interface 205 in the MCU module 14, where the remote power control instruction is used to control a power supply state of a plurality of power supply modules; upon receiving the power control instruction, the plurality of power supply modules 16 are controlled to stop supplying power according to the first power supply timing, and the plurality of power supply modules 16 are controlled to supply power according to the power control instruction.
It should be noted that, the control priority of the remote power control command is higher than the control priority of the first power supply timing, for example: the remote power control command may turn the power module 16 off or on directly.
The communication interface 205 may be used to connect a network card, and the power control instructions include, but are not limited to, power supply timing different from the first power supply timing, power off, and power on.
The computer is turned off or awakened through remote control, so that the effect of convenient power saving is achieved.
In some embodiments of the application, the first interface comprises a direct media interface; the second interface includes a universal asynchronous receiver/transmitter interface.
Specifically, taking a commercial display computer as an example, in the related art, a power control system is shown in fig. 3, a CPU10 is connected to a PCH module 12, the PCH module 12 is connected to a Super IO chip 22, the Super IO chip 22 controls a plurality of power supply modules 16 to supply power to meet the timing requirements of power supply of the CPU10 and the PCH module 12, besides, the commercial display computer module further includes one MCU module 14 for interacting with the commercial display large screen complete machine, the Super IO chip 22 controls a mode as shown in fig. 4, and after a power-on signal or a power status signal of the CPU10 is given to the Super IO chip 22, a logic pin in the Super IO chip 22 inputs a signal to turn on the power supply module 16 corresponding to the timing sequence in the plurality of power supply modules 16. This control has the disadvantage: the enable signal is based on an internal logic fixed delay output and cannot be adjusted, thus failing to control the turn-on time and sequence of the power module 16 more flexibly. In fig. 3, LPC (Low pin count, an interface), ESPI (Serial Peripheral Interface, an interface) are shown.
In some embodiments of the present application, taking a commercial display computer as an example, as shown in fig. 5, the power control system directly reduces the Super IO chip 22, and controls the power timing to be executed by the MCU module 14, and controls the power supply module 16 by configuring the GPIO interface 204 of the MCU module 14, so as to turn on the power sequentially according to the requirements of the CPU10 and the PCH module 12. The execution steps are as follows: detecting input-setting timer 203 timing-configuring GPIO interface 204 to control multiple power supply modules 16.
The control manner of the MCU module 14 is shown in fig. 6, after the power status signal of the CPU10 is given to the MCU module 14, the MCU module 14 is utilized to have the function of the timer 203, so that the GPIO can be controlled to enable the power supply at any time, and the time difference required by programming can be flexibly according to the time sequence requirement.
In the application scenario of commercial display computers, the functions of the calculator module are not reduced, but the cost saving effect can be achieved. The MCU module 14, as a programmable device, can perform other customization functions according to application scenarios more flexibly, which is a capability not provided by the Super IO chip 22. The MCU module 14 can be connected with the external interface 20 for connection with an external device, and meanwhile, the use of one key chip of the Super IO chip 22 is reduced, so that the cost can be reduced, the MCU module 14 is already used in the current application scenario, the cost is not additionally increased only by configuring the GPIO interface 204 through software, the MCU module 14 can be programmed, any time sequence configuration can be performed according to the requirement, the delay of peripheral hardware circuits is reduced, various customization requirements can be realized, and the flexibility of the product is increased.
According to an embodiment of the present application, there is provided a control method embodiment of a power supply control system, it being noted that the steps shown in the flowcharts of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.
The embodiment of the application also provides a control method of the power supply control system, as shown in fig. 7, comprising the following steps:
step S702, the MCU module 14 obtains first power supply timing information provided by the CPU10 and second power supply timing information provided by the PCH module 12, the first power supply timing information being used for representing candidate power supply timings of the plurality of power supply modules 16 provided by the CPU10, and the second power supply timing information being used for representing candidate power supply timings of the plurality of power supply modules 16 provided by the PCH module 12;
step S704, the MCU module 14 determines the first power supply timing of the plurality of power supply modules 16 according to at least one of the first power supply timing information and the second power supply timing information;
in step S706, the MCU module 14 controls at least one power supply module 16 of the plurality of power supply modules 16 to supply power according to the first power supply timing sequence of the at least one power supply module 16 of the plurality of power supply modules 16.
Through the steps, the MCU module 14 is directly utilized to set the power supply time sequence of the power supply module according to the first power supply time sequence information provided by the CPU10 and the second power supply time sequence information provided by the PCH module 12, the purpose of flexibly setting the power supply time sequence is achieved, the technical effect of accurately controlling the power supply time sequence is achieved, and the technical problems of power supply sequence and time fixation caused by the fact that the power supply enable signal is based on the internal logic fixed delay output of the Super IO chip 22 are solved.
It will be appreciated that the MCU module 14 is configured to determine the output time of the enable signal according to the first power supply timing and timing information provided by a timer in the MCU module, and output the enable signal at the output time to control at least one power supply module to supply power according to the first power supply timing.
In some embodiments of the present application, the MCU module 14 receives power supply timing adjustment information; the power supply timing adjustment information is used to modify the first power supply timing.
In some embodiments of the present application, the MCU module 14 may further control the plurality of power modules 16 to stop supplying power according to the first power supply timing according to the received remote power control command, and control the plurality of power modules 16 to supply power according to the power control command. Wherein, the priority of the power control instruction is higher than the priority of the first power supply time sequence, for example: the computer is turned off or turned on through remote control, so that the effect of convenient power saving is achieved.
The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed technology may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of units may be a logic function division, and there may be another division manner in actual implementation, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method of the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.
Claims (10)
1. A power control system, comprising: the system comprises a central processing unit CPU, an integrated south bridge PCH module, a micro control unit MCU module and a plurality of power supply modules; the PCH module is respectively connected with the CPU module and the MCU module; the power supply module is used for supplying power to at least one of the CPU, the PCH module and the MCU module;
the CPU is used for providing first power supply time sequence information for the MCU module, and the first power supply time sequence information is used for representing candidate power supply time sequences of the power supply modules provided by the CPU;
the PCH module is used for providing second power supply time sequence information for the MCU module, and the second power supply time sequence information is used for representing candidate power supply time sequences of the power supply modules provided by the PCH module;
the MCU module is used for determining a first power supply time sequence of at least one power supply module of the power supply modules according to at least one of the acquired first power supply time sequence information and the second power supply time sequence information, and controlling the at least one power supply module to supply power according to the first power supply time sequence.
2. The system of claim 1, wherein the MCU module comprises: a processor, a memory and a general purpose input/output GPIO interface; wherein, the memory and the GPIO interface are both connected with the processor;
the processor is configured to call a program stored in the memory to perform the following steps: determining the first power supply timing according to at least one of the first power supply timing information and the second power supply timing information; the GPIO interface is used for outputting an enabling signal to the at least one power supply module to control the at least one power supply module to supply power according to the first power supply time sequence.
3. The system of claim 2, wherein the system further comprises a controller configured to control the controller,
the MCU module also comprises a timer connected with the processor and used for providing timing information for the processor;
the processor is further configured to determine an output time of the enable signal according to the first power supply time sequence and timing information provided by the timer, and output the enable signal at the output time to control the at least one power supply module to supply power according to the first power supply time sequence.
4. The system of claim 1, wherein the MCU module is further configured to receive power supply timing adjustment information after determining the first power supply timing, adjust the first power supply timing according to the power supply timing adjustment information, and control the at least one power supply module to supply power according to the adjusted first power supply timing.
5. The system of claim 4, wherein the system further comprises a controller configured to control the controller,
the MCU module is further used for acquiring power supply states of the power supply modules through GPIO interfaces of the MCU module; wherein the power supply state includes: whether the power supply module supplies power or not;
the power control system further includes: and the display equipment is connected with the MCU module and used for displaying the power supply states of the power supply modules.
6. The system of claim 5, wherein the system further comprises a controller configured to control the controller,
the MCU module is further used for receiving a power control instruction sent by external equipment through a communication interface in the MCU module, wherein the power control instruction is used for controlling the power supply states of the power supply modules; and under the condition that the power control instruction is received, controlling the power supply modules to supply power according to the power control instruction, wherein the priority of the MCU module responding to the power control instruction is higher than the priority of the MCU module responding to the first power supply time sequence.
7. A control method, characterized by being applied to a power supply control system, the control system comprising: the system comprises a central processing unit CPU, an integrated south bridge PCH module, a micro control unit MCU module and a plurality of power supply modules; the PCH module is respectively connected with the CPU module and the MCU module; the power supply module is used for supplying power to at least one of the CPU, the PCH module and the MCU module; the control method comprises the following steps:
the MCU module acquires first power supply time sequence information provided by the CPU and second power supply time sequence information provided by the PCH module, wherein the first power supply time sequence information is used for representing candidate power supply time sequences of the power supply modules provided by the CPU, and the second power supply time sequence information is used for representing candidate power supply time sequences of the power supply modules provided by the PCH module;
the MCU module determines a first power supply time sequence of at least one power supply module of the plurality of power supply modules according to at least one of the first power supply time sequence information and the second power supply time sequence information;
the MCU module controls the at least one power supply module to supply power according to the first power supply time sequence.
8. The method of claim 7, wherein the method further comprises:
after the first power supply time sequence is determined, the MCU module receives power supply time sequence adjustment information and modifies the first power supply time sequence according to the power supply time sequence adjustment information.
9. The method of claim 7, wherein the method further comprises:
the MCU module controls the power supply modules to supply power according to the power control instruction according to the received power control instruction, and the priority of the MCU module responding to the power control instruction is higher than the priority of the MCU module responding to the first power supply time sequence.
10. The method of claim 7, wherein the method further comprises:
the MCU module determines the output time of the enabling signal according to the first power supply time sequence and timing information provided by a timer in the MCU module, and outputs the enabling signal at the output time so as to control the at least one power supply module to supply power according to the first power supply time sequence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210499784.1A CN117075703A (en) | 2022-05-09 | 2022-05-09 | Power supply control system and control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119336668A (en) * | 2024-12-19 | 2025-01-21 | 苏州元脑智能科技有限公司 | Network card management method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119336668A (en) * | 2024-12-19 | 2025-01-21 | 苏州元脑智能科技有限公司 | Network card management method and device |
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