CN117060918A - Clock adjustment circuit and method - Google Patents

Abstract

A clock adjustment circuit and related clock adjustment method are provided. The clock adjustment circuit includes a pattern filter circuit, a phase error detector (PED) circuit, and a phase error calculation circuit. The pattern screening circuit is configured to select a first predetermined data pattern from a plurality of consecutive data samples originating from an output of the first sampler circuit in an acquisition mode of the clock adjustment circuit. The PED circuit is used to detect the phase error based on the output of the pattern filter circuit and the error samples derived from the output of the second sampler circuit. A phase error calculation circuit is used to determine the timing compensation of a sampling clock used by the first sampler circuit and the second sampler circuit based on the output of the PED circuit.

Description

Clock adjustment circuit and method

Technical field

The present invention relates to adjusting a clock signal, and more particularly to using a pattern filter circuit in acquisition mode and tracking mode to select a predetermined data pattern for phase error. Detected clock adjustment circuits and related clock adjustment methods.

Background technique

A serializer/deserializer (SerDes) is a pair of functional blocks commonly used in high-speed communications to compensate for limited input/output (I/O). These blocks convert data between serial data and parallel interfaces in each direction. The term "SerDes" generally refers to the interface used in a variety of technologies and applications. The primary purpose of SerDes is to provide data transfer over a single line or differential line pair, minimizing the number of I/O pins and interconnects. Clock and data recovery (CDR) circuits are responsible for sampling the analog waveforms of high-speed SerDes systems at the appropriate time. For example, high-speed SerDes receivers can use Bang-bang CDR or Baud-rate CDR. Bang-bang CDR has good performance, but consumes higher power because additional clock phases are required to sample symbol edge information. Therefore, Bang-bang CDR is not a good choice for low power applications. Compared to Bang-bang CDR, baud rate CDR has poorer performance but consumes less power since each symbol is only sampled once. Therefore, baud rate CDR is a good choice for low power applications. However, baud rate CDR may encounter multiple lock phase problems. That is to say, the baud rate CDR will lock different locking phases for different initial phases, and only one of the different locking phases is suitable, while other locking phases may lead to wrong decisions.

Therefore, there is a need for a novel solution that can solve the multiple locked phase problem of the baud rate CDR and can work well with the clock generator circuit using one of the many possible I/O architectures. The architecture includes common clock architecture, forward clock architecture and embedded clock architecture.

Contents of the invention

One object of the present invention is to provide a clock adjustment circuit and a related clock adjustment method, which use a pattern screening circuit to select a predetermined data pattern for phase error detection in acquisition mode and tracking mode.

According to a first aspect of the invention, an exemplary clock adjustment circuit is disclosed. Exemplary clock adjustment circuits include pattern screening circuits, phase error detector (PED) circuits, and phase error calculation circuits. The pattern screening circuit is configured to select a first predetermined data pattern from a plurality of consecutive data samples originating from an output of the first sampler circuit in an acquisition mode of the clock adjustment circuit. The PED circuit is used to detect the phase error based on the output of the pattern filter circuit and the error samples derived from the output of the second sampler circuit. A phase error calculation circuit is used to determine the timing compensation of a sampling clock used by the first sampler circuit and the second sampler circuit based on the output of the PED circuit.

According to a second aspect of the invention, an exemplary clock adjustment method is disclosed. An exemplary clock adjustment method includes performing a pattern filtering operation in an acquisition mode of the clock adjustment method to select a first predetermined data pattern from a plurality of consecutive data samples, wherein the plurality of consecutive data samples originate from a first sample the output of the operation; performing a phase error detection based on the output of the pattern filtering operation and error samples derived from the output of the second sampling operation; and based on the output of the phase error detection, performing a phase error calculation operation to determine a timing offset for a sampling clock used by the first sampling operation and the second sampling operation.

The present invention can solve the problem of multiple locked phases of baud rate CDR and can work well with clock generator circuits using one of many possible I/O architectures.

These and other objects of the present invention will undoubtedly become apparent to those skilled in the art upon reading the following figures and the detailed description of the preferred embodiments shown in the accompanying drawings.

Description of the drawings

1 is a schematic diagram of a first application using a clock adjustment circuit with acquisition (ACQ) pattern selection (pattern selection) and tracking (tracking, TRK) pattern selection according to an embodiment of the present invention.

Figure 2 is a schematic diagram illustrating an example of a root cause of multiple locked phases.

Figure 3 is a schematic diagram illustrating an S-curve of a PED function having multiple locked phases for a baud rate CDR in the case where the data pattern used by the PED function has decision errors caused by ISI.

4 is a schematic diagram illustrating an S-curve of a PED function selected as an ACQ pattern used by the PED circuit 104 in the data pattern D[n-1:n+1]=[-3-3 1]. Conditionally the CDR has only a single locked phase for the baud rate.

5 is a schematic diagram illustrating an S-curve of the PED function, where the S-curve is an ACQ pattern selected as the PED circuit 104 when the data pattern D[n-1:n+1]=[-3-3-1] The CDR has only a single locked phase for the baud rate.

FIG. 6 is a schematic diagram illustrating an S-curve of the PED function for an ACQ pattern used by the PED circuit 104 under the condition that the data pattern D[n-1:n+1]=[33 1] is selected. Baud rate CDR only has a single locked phase.

7 is a schematic diagram illustrating an S-curve of the PED function under the condition that the data pattern D[n-1:n+1]=[33-1] is selected as an ACQ pattern used by the PED circuit 104. CDR only has a single locked phase for baud rate.

8 is a schematic diagram illustrating an S-curve of a PED function selected as an ACQ pattern used by the PED circuit 104 in the data pattern D[n-1:n+1]=[1-3-3]. Conditional CDR has only a single locked phase for the baud rate.

9 is a schematic diagram illustrating an S-curve of the PED function, where the S-curve is an ACQ pattern selected as the PED circuit 104 when the data pattern D[n-1:n+1]=[-1-3-3] The CDR has only a single locked phase for the baud rate.

FIG. 10 is a schematic diagram illustrating an S-curve of the PED function under the condition that the data pattern D[n-1:n+1]=[1 3 3] is selected as an ACQ pattern used by the PED circuit 104. CDR only has a single locked phase for baud rate.

FIG. 11 is a schematic diagram illustrating an S-curve of the PED function under a condition that the data pattern D[n-1:n+1]=[-1 3 3] is selected as an ACQ pattern used by the PED circuit 104 The CDR only has a single locked phase for the baud rate.

FIG. 12 is a schematic diagram illustrating the concept of CDR pattern switching according to an embodiment of the present invention.

13 is a schematic diagram illustrating a second application using a clock adjustment circuit with ACQ pattern selection and TRK pattern selection according to an embodiment of the present invention.

Detailed ways

Certain terms are used throughout the following description and claims to refer to specific components. As will be apparent to those skilled in the art, electronic device manufacturers may refer to components by different names. This document is not intended to differentiate between components that have different names rather than different functions. In the following description and claims, the terms "including" and "including" are used in an open-ended fashion, and therefore should be interpreted to mean "including, but not limited to...". Furthermore, the term "couple" is intended to mean either an indirect electrical connection or a direct electrical connection. Thus, if one device is coupled to another device, the connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

1 is a schematic diagram of a first application using a clock adjustment circuit with acquisition (ACQ) pattern selection (pattern selection) and tracking (tracking, TRK) pattern selection according to an embodiment of the present invention. For example, but not limited to, the clock adjustment circuit 100 may be part of a baud-rate clock and data recovery (clock and data recovery, CDR) circuit. For example, high-speed SerDes receiver 10 may employ baud rate CDR circuitry. In this embodiment, high-speed SerDes receiver 10 includes multiple sampler circuits 12 and 14, clock generator circuit 16, receiver subsystem 18, and clock adjustment circuit 100. The clock adjustment circuit 100 includes a pattern screening circuit 102, a phase error detector (PED) circuit 104, a phase error calculation circuit 106 and a pattern switching control circuit 108. The high-speed SerDes receiver 10 is used to receive a data input signal (analog signal) S_IN, and derive transmission data from the analog input signal S_IN to generate a data output signal (digital signal) D_OUT. For example, the data input signal S_IN is an n-level pulse amplitude modulation (PAMn) signal transmitted from a high-speed SerDes transmitter (not shown), and the data output signal D_OUT includes the PAMn extracted from the data input signal S_IN Encode data.

The sampler circuit 12 may be implemented by a slicer or an analog-to-digital converter. The sampler circuit 12 is used to sample the analog input signal S_IN according to the sampling clock CLK_S generated from the clock generator circuit 16, and generate and output a plurality of continuous data samples d[k]. The sampler circuit 14 may be implemented by a limiter or an analog-to-digital converter. The sampler circuit 14 is used to sample the analog input signal S_IN according to the sampling clock CLK_S generated by the clock generator circuit 16, and generate and output a plurality of error samples e[k] respectively corresponding to the continuous data samples d[k]. Taking the PAM4 signal as an example, the analog input signal S_IN (two-bit data) is encoded into four-level symbols sent at every clock unit interval (unit interval, UI), so that the data samples obtained by the sampler circuit 12 can It is a fourth-level symbol selected from {+3,+1,-1,-3}. Specifically, when the sampling voltage of the data sample is higher than the top threshold, the data sample is determined to be +3; when the sampling voltage of the data sample is between the top threshold and the middle threshold, the data sample is determined to be +3. The judgment is +1. When the sampling voltage of the data sample is between the middle threshold and the bottom threshold, the data sample is determined to be -1. When the sampling voltage of the data sample is lower than the minimum threshold, the data sample is judged to be -3. The error samples in each UI can be derived by comparing the actual sampled voltage to the target reference voltage. Receiver subsystem 18 may contain equalizer and/or other signal processing functions.

Since the clock adjustment circuit 100 is part of a baud rate CDR circuit, the clock adjustment circuit 100 is arranged to handle timing recovery. The pattern screening circuit 102 is arranged to select a first predetermined data pattern from consecutive data samples derived from the output of the sampler circuit 12 in the ACQ mode of the clock adjustment circuit 100 . In this embodiment, consecutive data samples d[k] are received by pattern filtering circuit 102 after passing through receiver subsystem 18 . Specifically, the pattern screening circuit 102 performs ACQ pattern selection on consecutive data samples such that the first predetermined data pattern serves as the ACQ pattern used by the PED circuit 104 in the ACQ mode, and the remaining data patterns included in the consecutive data samples are prevented from reaching PED circuit 104. The PED circuit 104 is arranged to detect phase errors based on the output of the pattern filter circuit 102 and the error samples derived from the output of the sampler circuit 14 . Specifically, the PED circuit 104 uses a PED function for phase error detection, where the output of the PED function depends on the data samples and the error samples. As mentioned above, typical baud rate CDR has multiple lock-phase problems, where the root cause of multiple lock-phases is a decision error that provides wrong timing information.

Figure 2 is a schematic diagram illustrating an example of a root cause of multiple locked phases. Assume that three consecutive PAM4 symbols D[n-1:n+1] are [-3 -1 3]. Characteristic curve 202 illustrates the ideal transition of consecutive PAM4 symbols [-3 -1 3]. Intersymbol interference (ISI) is a form of signal distortion in which one symbol interferes with subsequent symbols. Therefore, the actual simulated waveform of consecutive PAM4 symbols [-3 -1 3] deviates from the ideal simulated waveform of consecutive PAM4 symbols [-3 -1 3] due to ISI. The actual transition of the consecutive PAM4 symbols [-3 -1 3] is illustrated by characteristic curve 204 . E represents the possible sampling range of D[n] during CDR initialization. C represents a good sampling point with no decision errors. In the case of sampling within the "A" range, the sampling time is too late. Because the CDR is locked too late, the D[n] decision is wrong, and the sampling result of the consecutive PAM4 symbols [-3 -13] becomes [-3 1 3]. Furthermore, since the sample voltage of D[n] is lower than the reference voltage level +1 (which is the ideal voltage level for the PAM4 symbol "1"), the associated error samples are negative, indicating that the CDR locked too early, which is consistent with The actual situation is different when the sampling time is later and thus provides erroneous timing information. In the other case, sampling is performed within range "B", the sampling time is advanced. Because the CDR is locked too early, the D[n] decision is wrong, and the sampling result of the consecutive PAM4 symbols [-3 -1 3] becomes [-3 -3 1]. Furthermore, since the sample voltage of D[n] is higher than the reference voltage level -3 (which is the ideal voltage level for the PAM4 symbol "-3"), the associated error samples are positive, indicating that the CDR locked too late, which This differs from the actual case where the sampling time is early and thus provides erroneous timing information. In short, when an analog waveform of a data pattern consisting of consecutive data samples (such as PAM4 symbols) suffers severe ISI, the output of the PED function can indicate an incorrect phase error and can cause the baud rate CDR to approach a deviation Locked phase for correct phase.

3 is a schematic diagram illustrating an S-curve of a PED function having multiple locked phases for a baud rate CDR in the case where the PED function uses a data pattern that has decision errors caused by ISI. The output of the PED function is represented by s-curve(τ), which is a function of the CDR locking point τ. The negative-slope zero-crossing point of the S-curve of the PED function represents a possible CDR locking phase. When the CDR initial phase is within the capture range R0, the output of the PED function (ie S-curve(τ)) represents the distance between the current CDR lock point and the CDR lock phase τ ₀ (which is the correct lock phase) The phase difference can be referenced to adjust the current CDR locking point so that it is close to the CDR locking phase τ ₀ , where S-curve(τ ₀ )=0. When the CDR initial phase is within the capture range R1, the output of the PED function (i.e., S-curve(τ)) represents the phase difference between the current CDR lock point and the CDR lock phase τ ₁ (which is the wrong lock phase), and It can be used as a reference to adjust the current CDR locking point to make it close to the CDR locking phase τ ₁ , where S-curve(τ ₁ )=0. When the CDR initial phase is within the capture range R2, the output of the PED function (i.e., S-curve(τ)) represents the phase difference between the current CDR lock point and the CDR lock phase τ ₂ (which is the wrong lock phase), and It can be used as a reference to adjust the current CDR locking point to make it close to the CDR locking phase τ ₂ , where S-curve(τ ₂ )=0.

As mentioned above, when an analog waveform of a data pattern consisting of consecutive data samples (e.g., PAM4 symbols) suffers severe ISI, the output of the PED function can indicate incorrect phase error and can cause the baud rate CDR to approach the error by the correct The phase error derives the locked phase. In order to solve this multiple locked phase problem encountered in the ACQ mode, the present invention proposes ACQ pattern selection to select a first predetermined data pattern S1 from consecutive data samples in the ACQ mode of the clock adjustment circuit 100, wherein the first Each of the predetermined data patterns S1 ensures that the PED function does not have multiple locking phases. For example, each of the first predetermined data patterns (i.e., ACQ patterns) S1 includes a plurality of data samples, and the signal level difference between any two of the data samples is limited to a preset range Inside.

Taking the PAM4 signal as an example of the analog input signal S_IN, the two-bit data is encoded into a four-level symbol transmitted in each UI, so that the data samples obtained by the sampler circuit 12 can be selected from {+3, +1,-1,-3} four-level symbols. Assume that each of the first predetermined data patterns (ie, ACQ patterns) S1 includes D[n-1], D[n], and D[n+1] sequences. Since D[n-1], D[n], and D[n+1] are all four-level symbols selected from {+3, +1, -1, -3}, D[n-1], There are 64 possible combinations of D[n] and D[n+1] sequences. Satisfy D[n-1]≤D[n]＜D[n+1], D[n-1]＜D[n]≤D[n+1], D[n-1]≥D[n] Any data pattern that is one of >D[n+1], and D[n-1]>D[n]≥D[n+1] may have timing information. Therefore, out of 64 data patterns, 32 data patterns may have timing information. However, some of these data patterns with timing information may have multiple locked phases. The pattern screening circuit 102 is designed to select data patterns in which the timing information does not have multiple locking phases.

When the signal level difference between D[n-1:n+1] is smaller, the error probability of D[n] decision error is lower. The first predetermined data pattern (ie, ACQ pattern) S1 may be selected using one or more of the following ACQ pattern selection rules. According to the first ACQ pattern selection rule, D[n] is equal to +3 or -3. The reason is that the largest symbols (e.g., ±3 for PAM4) are more resistant to ISI. According to the second ACQ pattern selection rule, D[n] is equal to D[n-1], and D[n+1] is equal to +1 or -1. According to the third ACQ style selection rule, D[n] is equal to D[n+1], and D[n-1] is equal to +1 or -1. Therefore, the first predetermined data pattern (ie, ACQ pattern) S1 that conforms to the ACQ pattern selection rule is as shown in the following table.

D[n-1] D[n] D[n+1] -3 -3 1 -3 -3 -1 3 3 1 3 3 -1 1 -3 -3 -1 -3 -3 1 3 3 -1 3 3

According to the design of the PED function used in the PED circuit 104, the negative slope zero crossing point of the S-curve of the PED function represents a possible CDR locking phase. 4 is a schematic diagram illustrating an S-curve of a PED function selected as an ACQ pattern used by the PED circuit 104 in the data pattern D[n-1:n+1]=[-3-3 1]. Conditionally the CDR has only a single locked phase for the baud rate. 5 is a schematic diagram illustrating an S-curve of the PED function, where the S-curve is an ACQ pattern selected as the PED circuit 104 when the data pattern D[n-1:n+1]=[-3-3-1] The CDR has only a single locked phase for the baud rate. 6 is a schematic diagram illustrating an S-curve of the PED function under the condition that the data pattern D[n-1:n+1]=[3 3 1] is selected as an ACQ pattern used by the PED circuit 104. CDR only has a single locked phase for baud rate. 7 is a schematic diagram illustrating an S-curve of a PED function under a condition that the data pattern D[n-1:n+1]=[3 3 -1] is selected as an ACQ pattern used by the PED circuit 104 The CDR only has a single locked phase for the baud rate. 8 is a schematic diagram illustrating an S-curve of a PED function selected as an ACQ pattern used by the PED circuit 104 in the data pattern D[n-1:n+1]=[1-3-3]. Conditional CDR has only a single locked phase for the baud rate. 9 is a schematic diagram illustrating an S-curve of the PED function, where the S-curve is an ACQ pattern selected as the PED circuit 104 when the data pattern D[n-1:n+1]=[-1-3-3] The CDR has only a single locked phase for the baud rate. FIG. 10 is a schematic diagram illustrating an S-curve of the PED function under the condition that the data pattern D[n-1:n+1]=[1 3 3] is selected as an ACQ pattern used by the PED circuit 104. CDR only has a single locked phase for baud rate. FIG. 11 is a schematic diagram illustrating an S-curve of the PED function under a condition that the data pattern D[n-1:n+1]=[-1 3 3] is selected as an ACQ pattern used by the PED circuit 104 The CDR only has a single locked phase for the baud rate.

Since the pattern filtering circuit 102 can filter out some data patterns that have multiple locking phases to the baud rate CDR, there is no need to control the CDR initial phase. Furthermore, since the S-curve of the PED function has only a single locked phase for the baud rate CDR at each first predetermined data pattern (i.e., ACQ pattern) S1, a wide capture range of SerDes timing recovery can be achieved, as shown in Figure 4 to Figure Shown in 11.

The output of PED circuit 104 (eg, S-curve(τ)) indicates the phase error between the current CDR lock point and the desired CDR lock phase. The phase error calculation circuit 106 is arranged to determine the timing compensation of the sampling clock CLK_S from the output of the PED circuit 104 and instruct the clock generator circuit 16 to apply the timing compensation to the sampler circuit (eg data slicer) 12 and the sampler The sampling clock CLK_S used by circuit (eg, CDR limiter) 14. For example, phase error calculation circuit 106 may collect timing errors for different received PAMn symbols (eg, PAM4 symbols) provided by PED circuit 104 and accumulate the collected timing errors to provide timing compensation to clock generator circuit 16 . However, this is for illustrative purposes only and is not intended to limit the invention.

The clock adjustment circuit 100 causes the CDR circuit (especially the baud rate CDR circuit) to be locked at the negative slope zero crossing point of the S-curve. For each first predetermined data pattern (ie, ACQ pattern) S1 described above, it may have a small slope near the desired locking phase. Therefore, each of the first predetermined data patterns (i.e., ACQ patterns) S1 is specifically selected to have a wide acquisition range but to be less sensitive to sampling time variations around the desired locking phase. To solve this problem, in the present invention, the ACQ pattern is selected to have D[n] with lower decision error probability to prevent multiple locked phases, and the TRK pattern is selected to have a large S-curve slope around D[n] to achieve more Good CDR performance. As shown in FIG. 1 , the pattern switching control circuit 108 is included in the clock adjustment circuit 100 . When the clock adjustment circuit 100 switches from the ACQ mode to the TRK mode because the CDR locking point is close to the desired locking phase, the pattern switching control circuit 108 is used to instruct the pattern screening circuit 102 to select from consecutive data samples in the TRK mode of the clock adjustment circuit 100 Second predetermined data patterns (ie, TRK patterns) S2 are selected, wherein each of the second predetermined data patterns (ie, TRK patterns) S2 is different from any of the first predetermined data patterns (ie, ACQ patterns) S1.

Taking the PAM4 signal as an example of the analog input signal S_IN, the two-bit data is encoded into a four-level symbol transmitted in each UI, so that the data samples obtained by the sampler circuit 12 can be selected from {+3, +1,-1,-3} four-level symbols. Assume that each of the second predetermined data patterns (ie, TRK patterns) S2 includes D[n-1], D[n], and D[n+1] sequences. Each of the second predetermined data patterns (ie, TRK patterns) S2 requires a large S-curve slope around the desired locking phase. For example, the second predetermined data pattern (ie, TRK pattern) S2 that conforms to the TRK pattern selection rule is shown in the following table.

FIG. 12 is a schematic diagram illustrating the concept of CDR pattern switching according to an embodiment of the present invention. An S-curve with a larger slope at the locked phase (i.e., the negative slope zero crossing point) will have better CDR quality. Therefore, the baud rate CDR circuit using TRK style 1204 for phase error detection in TRK mode can have better performance. However, the baud rate CDR circuit using TRK style 1204 for phase error detection in ACQ mode has multiple locked phase issues. In this embodiment, the baud rate CDR circuit using ACQ pattern 1202 for phase error detection in ACQ mode can avoid multiple locking phase problems caused by TRK pattern 1204. Simply put, ACQ mode and TRK mode can use different CDR methods to solve different problems. In addition, the ACQ mode CDR and the TRK mode CDR share most of the hardware and only require the pattern filtering circuit 102 to change the data pattern selected for subsequent phase error detection.

In the above embodiment, the proposed clock adjustment circuit 100 is applied to a high-speed SerDes receiver using a baud rate CDR circuit for timing recovery. However, this is for illustrative purposes only and is not meant to be a limitation of the invention. In fact, any application using the proposed clock adjustment circuit 100 falls within the scope of the present invention.

13 is a schematic diagram illustrating a second application using a clock adjustment circuit with ACQ pattern selection and TRK pattern selection according to an embodiment of the present invention. For example, but not limited to, the clock adjustment circuit 100 may be part of an application using a Bang-bangCDR circuit. For example, the high-speed SerDes receiver 1300 may employ Bang-bang CDR circuitry. High-speed SerDes receiver 1300 includes multiple sampler circuits 1302, 1304, and 1306, receiver subsystem 1308, CDR clock generator circuit 1310, data clock generator circuit 1312, Bang-bang CDR circuit 1314, combining circuit 1316, and the clocks described above Adjust circuit 100.

The high speed SerDes receiver 1300 is arranged to receive a data input signal (analog signal) S_IN and to derive the data to be transmitted from the analog input signal S_IN to generate a data output signal (digital signal) D_OUT. For example, the data input signal S_IN is an n-level pulse amplitude modulation (PAMn) signal transmitted from a high-speed SerDes transmitter (not shown), and the data output signal D_OUT includes PAMn encoded data. Sampler circuit 1302 may be implemented by a limiter or an analog-to-digital converter. Similar to the sampler circuit 12 shown in FIG. 1 , the sampler circuit (eg, data slicer) 1302 is used to sample the analog input signal S_IN according to the sampling clock CLK_S generated by the data clock generator circuit 1312 to generate and output a plurality of signals. consecutive data samples d[k]. Sampler circuit 1304 may be implemented by a limiter or an analog-to-digital converter. Similar to the sampler circuit 14 shown in FIG. 1 , the sampler circuit (such as a skew slicer) 1304 is used to perform sampling on the analog input signal S_IN according to the sampling clock CLK_S generated by the data clock generator circuit 1312 . Sampling, generating and outputting multiple error samples e[k] corresponding to multiple consecutive data samples d[k]. Sampler circuit 1306 may be implemented by a limiter or an analog-to-digital converter. The sampler circuit (such as a CDR limiter) 1306 is used to sample the analog input signal S_IN according to another sampling clock CLK_S' generated by the CDR clock generator circuit 1310 to generate and output the symbol edges required by the Bang-bang CDR circuit 1314 information. Similar to receiver subsystem 18 shown in Figure 1, receiver subsystem 1308 may contain an equalizer and/or other signal processing functionality.

To meet high-performance requirements, the high-speed SerDes receiver 1300 may employ a Bang-bang CDR circuit 1314. To prevent dual clock frequency requirements, the high-speed SerDes receiver 1300 uses two clock generator circuits, including a data clock generator circuit 1312 and a CDR clock generator circuit 1310, to support half UI phase difference. Specifically, the expected sampling phase of the sampling clock CLK_S is located in the middle of one symbol transmitted in each UI, and the expected sampling phase of the sampling clock CLK_S' is located at the edge of one symbol transmitted in each UI. The offset between the two clock generator circuits including the data clock generator circuit 1312 and the CDR clock generator circuit 1310 is not negligible.

In this embodiment, the clock adjustment circuit 100 is configured to handle data skew calibration. Pattern screening circuit 102 is configured to select a first predetermined data pattern (ie, ACQ pattern) S1 from consecutive data samples originating from the output of sampler circuit 1302 in a skew-calibrated ACQ mode. In this embodiment, consecutive data samples d[k] are received by the pattern filtering circuit 102 after passing through the receiving subsystem 1318 . Specifically, the pattern screening circuit 102 performs ACQ pattern selection on consecutive data samples such that the first predetermined data pattern is used as the ACQ pattern by the PED circuit 104 in the skew-calibrated ACQ mode, and the remaining data patterns in the consecutive data samples are Reaching the PED circuit 104 is blocked. The PED circuit 104 is arranged to detect phase errors based on the output of the pattern filter circuit 102 and error samples derived from the output of the sampler circuit 1314 . Specifically, the PED circuit 104 uses a PED function for phase error detection, where the output of the PED function depends on the data samples and the error samples.

The phase error calculation circuit 106 is arranged to determine the timing compensation of the sampling clock CLK_S from the output of the PED circuit 104 . For example, the phase error calculation circuit 106 may collect the timing errors (timing errors) of different received PAMn symbols (eg, PAM4 symbols) provided by the PED circuit 104, and accumulate the collected timing errors to provide timing compensation to the data clock generator. Circuit 1312. In this embodiment, the combining circuit 1316 may be implemented by an adder, such that the output of the phase error calculation circuit 106 and the output of the Bang-bang CDR circuit 1314 are combined to jointly control the data clock generator circuit 1312 for the sampler circuit ( Timing compensation 1312 for the sampling clock CLK_S used by, for example, a data slicer) and sampler circuit (eg, a skew slicer) 1314.

When the clock adjustment circuit 100 switches from the ACQ mode to the TRK mode due to the offset calibrated locking point approaching the desired locking phase, the pattern switching control circuit 108 is operable to instruct the pattern screening circuit 102 to switch from continuous to TRK mode in the offset calibrated TRK mode. Second predetermined data patterns (ie, TRK patterns) S2 are selected from the data samples, wherein each second predetermined data pattern (ie, TRK pattern) S2 is different from any first predetermined data pattern (ie, ACQ pattern) S1. As such, the high-speed SerDes receiver 1300 benefits from the clock adjustment circuit 100 to have a wide skew calibration range in the skew-calibrated ACQ mode and high performance in the skew-calibrated TRK mode.

Since those skilled in the relevant art can easily understand the details of the clock adjustment circuit 100 used in the embodiment shown in FIG. 13 after reading the above paragraphs for the clock adjustment circuit 100 used in the embodiment shown in FIG. 1, hereby No need to go into details.

It should be noted that in some embodiments of the present invention, both the clock generator circuit 16 and the data clock generator circuit 1312 with timing compensation provided by the clock adjustment circuit 100 can support any I/O architecture, such as a common clock architecture, Forward clock architecture or embedded clock architecture.

Those skilled in the art will readily observe that many modifications and variations can be made in the apparatus and methods while retaining the teachings of the present invention. Accordingly, the foregoing disclosure should be construed as limited only by the appended claims.

Claims (20)

1. A clock adjustment circuit, including: Pattern screening circuitry for selecting a first predetermined data pattern from a plurality of consecutive data samples derived from an output of the first sampler circuit in an acquisition mode of the clock adjustment circuit; a phase error detector PED circuit for detecting a phase error based on the output of the pattern screening circuit and error samples derived from the output of the second sampler circuit; and Phase error calculation circuit for determining timing compensation of a sampling clock used by the first sampler circuit and the second sampler circuit based on the output of the PED circuit. 2. The clock adjustment circuit of claim 1, wherein each of the first predetermined data patterns includes a plurality of data samples, and any two data samples of the plurality of data samples The signal level difference between them is limited to a predetermined range. 3. The clock adjustment circuit of claim 2, wherein the plurality of continuous data samples are obtained by sampling a four-level pulse amplitude modulation (PAM4) signal according to the sampling clock, and the plurality of continuous data samples are obtained by sampling a four-level pulse amplitude modulation (PAM4) signal according to the sampling clock. The data samples include the sequence D[n-1], D[n], D[n+1], and D[n] is equal to +3 or -3. 4. The clock adjustment circuit of claim 2, wherein the plurality of continuous data samples are obtained by sampling the PAM4 signal according to the sampling clock, and the plurality of data samples include the sequence D[n- 1], D[n], D[n+1], D[n] is equal to D[n-1], and D[n+1] is equal to +1 or -1. 5. The clock adjustment circuit of claim 4, wherein D[n] is equal to +3 or -3. 6. The clock adjustment circuit of claim 2, wherein the plurality of continuous data samples are obtained by sampling the PAM4 signal according to the sampling clock, and the plurality of data samples include the sequence D[n- 1], D[n], D[n+1], D[n] is equal to D[n+1], and D[n-1] is equal to +1 or -1. 7. The clock adjustment circuit of claim 6, wherein D[n] is equal to +3 or -3. 8. The clock adjustment circuit of claim 1, further comprising: Pattern switching control circuit, wherein in response to the clock adjustment circuit switching from the acquisition mode to the tracking mode, the pattern switching control circuit is arranged to instruct the pattern screening circuit to be in the tracking mode of the clock adjustment circuit A second predetermined data pattern is selected from the plurality of consecutive data samples; each of the second predetermined data patterns is different from any of the first predetermined data patterns. 9. The clock adjustment circuit of claim 1, wherein the clock adjustment circuit is part of a baud rate clock and data recovery circuit for timing recovery. 10. The clock adjustment circuit of claim 1, wherein the clock adjustment circuit is part of an application using a Bang-bang clock and data recovery circuit and is used for data offset calibration. 11. A clock adjustment method, comprising: performing a pattern filtering operation in an acquisition mode of the clock adjustment method to select a first predetermined data pattern from a plurality of consecutive data samples, wherein the plurality of consecutive data samples originate from an output of a first sampling operation; performing phase error detection based on the output of the pattern filtering operation and error samples derived from the output of the second sampling operation; and Based on the output of the phase error detection, a phase error calculation operation is performed to determine a timing compensation of a sampling clock used by the first sampling operation and the second sampling operation. 12. The clock adjustment method of claim 11, wherein each of the first predetermined data patterns includes a plurality of data samples, and any two data samples of the plurality of data samples The signal level difference between them is limited to a predetermined range. 13. The clock adjustment method of claim 12, wherein the plurality of continuous data samples are obtained by sampling a four-level pulse amplitude modulated PAM4 signal according to the sampling clock, and the plurality of data samples Including the sequence D[n-1], D[n], D[n+1], D[n] is equal to +3 or -3. 14. The clock adjustment method according to claim 12, wherein the plurality of continuous data samples are obtained by sampling the PAM4 signal according to the sampling clock, and the plurality of data samples include the sequence D[n- 1], D[n], D[n+1], D[n] is equal to D[n-1], and D[n+1] is equal to +1 or -1. 15. The clock adjustment method according to claim 14, wherein D[n] is equal to +3 or -3. 16. The clock adjustment method of claim 12, wherein the plurality of continuous data samples are obtained by sampling the PAM4 signal according to the sampling clock, and the plurality of data samples include the sequence D[n- 1], D[n], D[n+1], D[n] is equal to D[n+1], and D[n-1] is equal to +1 or -1. 17. The clock adjustment method according to claim 16, wherein D[n] is equal to +3 or -3. 18. The clock adjustment method according to claim 11, further comprising: Instructing the pattern filtering operation to select a second predetermined data pattern from the plurality of consecutive data samples in the tracking mode of the clock adjustment circuit in response to the clock adjustment circuit switching from the acquisition mode to the tracking mode. ; wherein each of said second predetermined data patterns is different from any of said first predetermined data patterns. 19. The clock adjustment method of claim 11, wherein the clock adjustment method is part of a baud rate clock and data recovery circuit and is used for timing recovery. 20. The clock adjustment method of claim 11, wherein the clock adjustment method is part of an application using a Bang-bang clock and data recovery circuit and is used for data offset calibration.