CN117056986A - A SRAM PUF security chip - Google Patents

Abstract

The invention discloses an SRAM PUF security chip, which relates to the field of integrated circuits. The SRAM PUF security chip includes: an SRAM unit, a first three-state gate, a second three-state gate, a third three-state gate and a first NOT gate; The input terminals of the first three-state gate, the second three-state gate and the third three-state gate are all connected to the power supply of the security chip; the control terminals of the first three-state gate and the second three-state gate are all connected to the precharge enable signal. ; The input terminal of the first NOT gate is connected to the precharge enable signal; the output terminal of the first NOT gate is connected to the control terminal of the third three-state gate; the output terminal of the first three-state gate is connected to the bit line of the SRAM unit; The output terminal of the second tri-state gate is connected to the inverted bit line of the SRAM cell; the output terminal of the third tri-state gate is connected to the power supply of the SRAM cell. The present invention can generate twice the number of stimulus-response relationships under the same hardware resources, expanding the application scenarios of SRAM PUF.

Description

SRAM PUF safety chip

Technical Field

The application relates to the field of integrated circuits, in particular to an SRAM PUF safety chip.

Background

The password is a basic support for guaranteeing information security. Traditional cryptography uses non-volatile memory to hold keys, which are vulnerable to security. There are many possible physical attack means, such as microprobe, side channel attack, etc., that risk theft, tampering of the stored keys.

In view of the above, a physically unclonable function (Physical Unclonable Function, PUF) is considered to be an effective means of improving the security of computer systems against physical attacks. PUF security chips use the random process variations that are unavoidable in the manufacturing process of integrated circuits to generate a unique chip identifier as a "physical fingerprint". Because the process deviation in the production and manufacturing process cannot be controlled manually, the physical fingerprint of the PUF chip has the characteristics of unpredictable and difficult cloning; in addition, the physical fingerprint of the PUF chip has the characteristic of readable power on and power off, thereby further improving the safety; finally, the physical fingerprint of the PUF chip is completely dependent on the physical characteristics of the chip, so that no additional memory is needed to store identity information, the PUF chip has the advantage of low hardware cost, and lightweight security protection is realized in application scenes with scarce resources. The PUF chip has the advantages that the PUF chip can provide an inherent and unique trust root in applications such as identity authentication, information encryption and chip watermarking, and has wide development prospects in the fields of hardware security and internet of things security.

Currently, SRAM PUFs with static random access memory (Static Random Access Memory, SRAM) as a core circuit are a typical PUF security chip. SRAM PUFs take advantage of the randomness of the SRAM cells to store data at power up and read the power up initial value of a particular memory cell as a random response by setting a stimulus. The SRAM PUF has higher reliability and can provide relatively stable response output under the influence of factors such as temperature, supply voltage and the like. However, the number of stimulus-response relationships supported by the SRAM PUF is limited, and the number of stimulus-response relationships only has a linear increasing trend along with the increase of the number of SRAM cells, so that the application scenario of the SRAM PUF is limited.

Disclosure of Invention

Based on the above, the embodiment of the application provides the SRAM PUF safety chip, which can generate twice number of excitation-response relations under the condition of the same hardware resources, and expands the application scene of the SRAM PUF.

In order to achieve the above object, the embodiment of the present application provides the following solutions:

an SRAM PUF security chip comprising: an SRAM cell and a first precharge control circuit; the first precharge control circuit includes: a first tri-state gate, a second tri-state gate, a third tri-state gate, and a first NOT gate;

the input end of the first tri-state gate, the input end of the second tri-state gate and the input end of the third tri-state gate are all connected with a first power supply; the control end of the first tri-state gate and the control end of the second tri-state gate are connected with a precharge enabling signal; the input end of the first NOT gate is connected with the precharge enabling signal; the output end of the first NOT gate is connected with the control end of the third three-state gate; the output end of the first tri-state gate is connected with the bit line of the SRAM unit; the output end of the second tri-state gate is connected with the inverting bit line of the SRAM unit; the output end of the third tri-state gate is connected with a second power supply; the first power supply is used as a power supply of the security chip; the second power supply is used as a power supply of the SRAM unit.

Optionally, the SRAM cell comprises: a latch unit, a first transfer transistor, and a second transfer transistor;

the grid electrode of the first transmission transistor and the grid electrode of the second transmission transistor are connected with a word line; the drain electrode of the first transmission transistor is connected with a bit line; the drain electrode of the second transmission transistor is connected with the inverting bit line;

a first input end of the latch unit is connected with the second power supply; a second input end of the latch unit is connected with a source electrode of the first transmission transistor; a third input end of the latch unit is connected with a source electrode of the second transmission transistor; the logic voltage values of the second input terminal and the third input terminal are opposite.

Optionally, the latch unit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor;

the first transistor and the third transistor are connected to form a second NOT gate; the second transistor and the fourth transistor are connected to form a third NOT gate; the input end of the second NOT gate is connected with the output end of the third NOT gate; the input end of the third NOT gate is connected with the output end of the second NOT gate; the input end of the second NOT gate is used as a second input end of the latch unit; the input end of the third NOT gate is used as a third input end of the latch unit; the second NOT gate and the third NOT gate are both connected with the second power supply.

The application also provides an SRAM PUF safety chip, comprising: an SRAM array and a second precharge circuit; the SRAM array, comprising: 2 ^m SRAM cells of row, n columns; the second precharge circuit includes: n tri-state gate units, a fourth tri-state gate and a fourth NOT gate;

the tri-state gate unit includes: a fifth tri-state gate and a sixth tri-state gate; a column of SRAM units is correspondingly connected with a tri-state gate unit;

for the M-th row in the SRAM array, word lines of all SRAM cells in the M-th column are connected to form a word line connection end; m is more than or equal to 1 and less than or equal to 2 ^m ；

For the N-th column in the SRAM array, bit lines of all SRAM cells in the N-th column are connected to form bit line connection ends, and inverting bit lines of all SRAM cells in the N-th column are connected to form inverting bit line connection ends; the control ends of a fifth tri-state gate and a sixth tri-state gate in the N-th tri-state gate unit are connected with a precharge enabling signal; the input ends of a fifth tri-state gate and a sixth tri-state gate in the N-th tri-state gate unit are connected with a first power supply; the output end of a fifth tri-state gate in the Nth tri-state gate unit is connected with the bit line connecting end; the output end of a sixth tri-state gate in the Nth tri-state gate unit is connected with the inverting bit line connecting end; n is more than or equal to 1 and less than or equal to N;

the input end of the fourth NOT gate is connected with the precharge enabling signal; the output end of the fourth NOT gate is connected with the control end of the fourth three-state gate; the input end of the fourth tri-state gate is connected with the first power supply; the output end of the fourth tri-state gate is connected with a second power supply; the first power supply is used as a power supply of the security chip; the second power supply is used as a power supply of the SRAM unit.

Optionally, the SRAM PUF security chip further comprises: an m-bit address decoder;

the output end of the address decoder is connected with all word line connection ends.

Optionally, the SRAM PUF security chip further comprises: a data controller;

the data controller includes: n input/output bidirectional interfaces; one of the input-output bi-directional interfaces is connected with one tri-state gate unit.

According to the specific embodiment provided by the application, the application discloses the following technical effects:

according to the SRAM PUF safety chip provided by the embodiment of the application, the precharge control circuit is added into the chip, so that the SRAM units in the chip are subjected to precharge control when the chip is electrified to generate a variable excitation-response relationship, and the quantity of the excitation-response relationship is increased.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic circuit diagram of an SRAM PUF security chip according to an embodiment of the present application;

FIG. 2 is a schematic circuit diagram of an SRAM cell according to a first embodiment of the present application;

FIG. 3 is a schematic waveform diagram showing the control signal and the power-on initial value change of the SRAM cell provided in the first embodiment of the present application under the two conditions of no pre-charge and pre-charge;

fig. 4 is a schematic circuit diagram of an SRAM PUF security chip according to a second embodiment of the present application;

FIG. 5 is a graph showing the power-up initial value variation of an SRAM array provided in a second embodiment of the present application without pre-charging and without pre-charging;

fig. 6 is a schematic diagram of pin configuration of an SRAM PUF security chip (with a capacity of 1 KB) according to a second embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

In order to solve the problem that the quantity of the excitation-response relation of the SRAM PUF chip is limited, the application provides that a precharge control circuit is added into the SRAM PUF safety chip, and when the chip is powered on, the SRAM unit is precharged, and circuit parameters such as the drive current of transistors in the SRAM unit are changed to reconstruct the chip, so that different response outputs can be generated when the precharge is carried out and when the precharge is not carried out on the basis of the same SRAM PUF chip and under the condition of receiving the same excitation input. The output end of the precharge control circuit is connected with the data input ends of all SRAM units; one input end of the precharge control circuit is connected with a pin of the power supply input end of the chip, and the two input ends of the precharge control circuit are connected with an additional signal input pin of the chip for controlling whether the SRAM unit is precharged or not.

Therefore, the application aims to provide the SRAM PUF safety chip, which generates a variable excitation-response relation by adding the precharge control circuit into the chip, and generates twice as many excitation-response relations under the condition of the same hardware resource, thereby expanding the application field of the SRAM PUF.

In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.

Example 1

Referring to fig. 1, the SRAM PUF security chip of the present embodiment includes: an SRAM cell 100 and a first precharge control circuit; the first precharge control circuit includes: a first tri-state gate 101, a second tri-state gate 102, a third tri-state gate 103 and a first not gate 104.

The input end of the first tri-state gate 101, the input end of the second tri-state gate 102 and the input end of the third tri-state gate 103 are all connected with a first power supply VDD; the control end of the first tri-state gate 101 and the control end of the second tri-state gate 102 are both connected with a precharge enable signal ENB; the input end of the first NOT gate 104 is connected with the precharge enable signal; the output end of the first NOT gate 104 is connected with the control end of the third tri-state gate 103; the output end of the first tri-state gate 101 is connected with the bit line BL of the SRAM cell 100; the output end of the second tri-state gate 102 is connected with the inverting bit line BL of the SRAM cell 100; the output end of the third tri-state gate 103 is connected with the second power supply VDD _SRAM Connecting; the first power supply is used as a power supply of the security chip; the second power supply serves as a power supply for the SRAM cell 100; the SRAM cell 100 is also connected to a word line WL.

In one example, referring to fig. 2, the SRAM cell 100 includes: a latch unit, a first pass transistor T5 and a second pass transistor T6.

The grid electrode of the first transmission transistor T5 and the grid electrode of the second transmission transistor T6 are connected with a word line WL; the drain electrode of the first transmission transistor T5 is connected with a bit line BL; the drain electrode of the second transmission transistor T6 is opposite to the bit lineAnd (5) connection.

A first input terminal of the latch unit and the second power supply VDD _SRAM Connecting; a second input terminal a of the latch unit is connected with a source electrode of the first transmission transistor T5; the third input terminal b of the latch unit is connected with the source electrode of the second transmission transistor T6; the logic voltage values of the second input terminal and the third input terminal are opposite.

The latch unit is described below.

Still referring to fig. 2, the latch unit includes: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

The first transistor T1 and the third transistor T3 are connected to form a second NOT gate; the second transistor T2 and the fourth transistor T4 are connected to form a third NOT gate; the input end of the second NOT gate is connected with the output end of the third NOT gate; the input end of the third NOT gate is connected with the output end of the second NOT gate; the input of the second not gate is taken as a second input a (also called node a) of the latch unit; the input of the third not gate is taken as a third input b (also called node b) of the latch unit; the second NOT gate and the third NOT gate are both connected with the second power supply VDD _SRAM And (5) connection.

In this example, the SRAM cell 100 includes six transistors; the first transistor T1 and the third transistor T3 constitute one not gate, and the second transistor T2 and the fourth transistor T4 constitute the other not gate. The output of one NOT is coupled to the input of the other NOT to form a latch unit having nodes a and b with opposite logic voltage values.

The first and second pass transistors T5 and T6 are controlled by the word line signal WL to respectively connect the node a and the bit line BL and the node b and the inverted bit lineBit line BL and bit line of inversion->And the input/output bidirectional interface is connected. Data reading or writing to the SRAM cell 100 is performed through the bit lines BL and +.>To realize the method.

When the SRAM cell 100 is powered on, the power input terminal VDD of the SRAM cell 100 _SRAM The initial logic voltage values of node a and node b, i.e., the power-up initial value of the SRAM cell 100, are the power-up initial values for the cell. The power-up initial values of different SRAM cells 100 are different. Because the power-up initial value is determined by the driving capability of each transistor (T1, T2, T3 and T4) in the SRAM cell 100, it is dependent on the circuit manufacturing processThe machine process deviation.

The first precharge control circuit includes three tri-state gates and one not gate.

Wherein the first tri-state gate 101 and the second tri-state gate 102 are controlled by the precharge enable signal ENB, and respectively connect the bit line BL and the inverting bit line BL of the SRAM cell 100 to the chip power supply input terminal VDD (i.e., the first power supply) only when enb=1.

The first not gate 104 inverts the precharge enable signal ENB and controls the third tri-state gate 103: the chip power input terminal VDD and the SRAM cell 100 power input terminal VDD are connected only when ENB=0 _SRAM In communication, power is supplied to the SRAM cell 100.

The control signal and power-up initial value change condition of the SRAM cell 100 without precharging and without precharging is shown in fig. 3.

Referring to part (a) of fig. 3, when precharge is not performed, the precharge enable signal enb=0, the bit line BL and the inversion bit line of the sram cell 100Is not in communication with the chip power supply input VDD and the word line signal wl=0, thereby disconnecting node a and node b from the two bit lines. After the chip is powered on, the chip power input terminal VDD passes through the SRAM cell 100 power input terminal VDD _SRAM The SRAM cell 100 is powered. At this time, the power-up initial value of the SRAM cell 100 is determined by the driving capability of the transistors T1, T2, T3 and T4. In this example, the power-up initial values of node a and node b when not precharged are logic 0 and logic 1, respectively.

Referring to part (b) of fig. 3, in the precharge, the precharge enable signal ENB and the word line signal WL are each first 1. During this time, the chip power input VDD will be connected to node a and node b through two bit lines BL and BL, respectively, and precharge node a and node b after the chip is powered up. At the same time, the power input terminal VDD of the SRAM cell 100 _SRAM Disconnect from chip power supply input terminal VDD, thus VDD _SRAM There is no effect on the voltage values of node a and node b during precharge. Due to the SRAM cell 100The driving capability of the first pass transistor T5 and the second pass transistor T6 is affected by random process variations in the circuit manufacturing process and has randomness, and there will be random voltage differences between the node a and the node b during the same precharge time. When the precharge is completed, the precharge enable signal enb=0, and the word line signal wl=0. At this time, the chip power input terminal VDD starts to pass through the power input terminal VDD of the SRAM cell 100 _SRAM The SRAM cell 100 is powered. However, the voltage difference between node a and node b due to the precharge will likely change the original power-up initial values of the two nodes. In this example, the power-up initial values of node a and node b when precharging are respectively logic 1 and logic 0, as opposed to when not precharging.

Example two

Referring to fig. 4, the SRAM PUF security chip provided in this embodiment includes: an SRAM array and a second precharge circuit; the SRAM array, comprising: 2 ^m Row, n columns of SRAM cells 100; the second precharge circuit includes: n tri-state gate units, a fourth tri-state gate 403 and a fourth not gate 404.

The tri-state gate unit includes: a fifth tri-state gate 401 and a sixth tri-state gate 402; a column of SRAM cells 100 is correspondingly connected to a tri-state gate cell.

For the mth row in the SRAM array, word lines of all SRAM cells 100 in the mth column are connected to form one word line connection terminal; m is more than or equal to 1 and less than or equal to 2 ^m 。

For the nth column in the SRAM array, bit lines of all SRAM cells 100 in the nth column are connected to form bit line connection ends, and inverting bit lines of all SRAM cells 100 in the nth column are connected to form inverting bit line connection ends; the control ends of the fifth tri-state gate 401 and the sixth tri-state gate 402 in the nth tri-state gate unit are connected with the precharge enable signal; the input ends of the fifth tri-state gate 401 and the sixth tri-state gate 402 in the Nth tri-state gate unit are connected with a first power supply; the output end of the fifth tri-state gate 401 in the nth tri-state gate unit is connected with the bit line connection end; the output end of the sixth tri-state gate 402 in the nth tri-state gate unit is connected with the inverting bit line connecting end; n is more than or equal to 1 and less than or equal to N.

An input terminal of the fourth NOT gate 404 is connected with the precharge enable signal; the output end of the fourth not gate 404 is connected to the control end of the fourth tri-state gate 403; the input end of the fourth tri-state gate 403 is connected to the first power supply; the output end of the fourth tri-state gate 403 is connected to a second power supply; the first power supply is used as a power supply of the security chip; the second power source serves as a power source for the SRAM cell 100.

In this example, still referring to fig. 4, the SRAM PUF security chip further includes: m-bit address decoder 405 (A ₀ ...A _m-1 ) And a data controller 406.

The output of the address decoder 405 is connected to all word line connections.

The data controller 406 includes: n input/output two-way interface (corresponding to D) ₀ ...D _n-1 ) The method comprises the steps of carrying out a first treatment on the surface of the One of the input-output bi-directional interfaces is connected with one tri-state gate unit.

The address decoder 405 enables the word line signal WL of a specific row in the array by decoding the received address. The m-bit address can be controlled to 2 at most ^m SRAM arrays of rows.

The SRAM cells 100 of each column share two bit lines BL andthus, all SRAM cells 100 of each column are uniformly precharged with two tri-state gates (fifth tri-state gate 401 and sixth tri-state gate 402). All SRAM cells 100 in the array share the power supply input VDD _SRAM The power inputs of all SRAM cells 100 are thus controlled by one fourth tri-state gate 403 and one fourth not gate 404.

The data controller 406 has n input-output bi-directional interfaces to enable reading and writing of n-bit binary numbers. Each input-output bi-directional interface is connected with bit lines BL and BL of a specific column in the SRAM arrayData reading and writing are realized. Other input signals includeA chip select signal CS, a read enable signal OE, and a write enable signal WE. When the chip select signal CS is enabled, the SRAM array can perform read and write operations. When data reading operation is carried out, enabling OE and disabling WE are needed; when a data write operation is performed, WE is enabled and OE is disabled. n and n are all greater than 1, and the values of m and n are mutually independent and have no limit on the size relationship.

The change of the power-up initial value of the SRAM array in both the case where the precharge is not performed and the case where the precharge is performed is shown in fig. 5, and the change of the power-up initial value in the case where the precharge is not performed is shown in part (a) of fig. 5, and the change of the power-up initial value in the case where the precharge is performed is shown in part (b) of fig. 5. In this example, about 40% of the SRAM cells 100 have different power-up initial values, both without precharging and with precharging. The SRAM cell 100 distribution with the power-up initial value changed is random and unpredictable. The precharge enables reconstruction of the original stimulus-response relationship of the SRAM PUF.

SRAM PUF security chip pin configuration as shown in fig. 6, in this example, the SRAM PUF contains 1KB SRAM cells 100, which can be read or written to an 8-bit binary number at a time. Thus, the chips shareThe address input is provided by the pins (pins 1 to 10) and the data input and output bi-directional interface is provided by 8 pins (pins 16 to 23). Pins 11, 12, 14, 15 and 24 interface with the chip select signal CS, power ground GND, sense enable signal OE, write enable signal WE and chip power input VDD, respectively. Pin 13 is an additional pin to which the precharge enable signal ENB is connected.

The present embodiment mainly describes the differences from the first embodiment, and the same points are only required to refer to the first embodiment, and are not described herein again.

In existing SRAM PUF security chips, each SRAM cell has a specific power-on initial value and therefore can only produce a single response output. The SRAM PUF security chip of all the embodiments described above is a reconfigurable SRAM PUF security chip, having the advantage of low cost. Specifically, the SRAM PUF safety chip can enable partial SRAM units to generate different power-on initial values under the two conditions of pre-charging and non-pre-charging by adding the pre-charging control circuit. And the SRAM unit distribution of which the power-on initial value is changed is random and unpredictable. Therefore, under the condition of the same SRAM cell number, compared with the prior SRAM PUF security chip, the SRAM PUF security chip provided by the application can reconstruct a circuit through precharge, thereby generating twice the excitation-response relation. In other words, in order to realize the same number of stimulus-response relationships, compared with the existing SRAM PUF security chip, the SRAM PUF security chip provided by the application only needs to include half of the number of SRAM cells, so that the SRAM PUF security chip has the advantage of low cost.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present application and the core ideas thereof; also, it is within the scope of the present application to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the application.

Claims (6)

1. An SRAM PUF security chip comprising: an SRAM cell and a first precharge control circuit; the first precharge control circuit includes: a first tri-state gate, a second tri-state gate, a third tri-state gate, and a first NOT gate;

the input end of the first tri-state gate, the input end of the second tri-state gate and the input end of the third tri-state gate are all connected with a first power supply; the control end of the first tri-state gate and the control end of the second tri-state gate are connected with a precharge enabling signal; the input end of the first NOT gate is connected with the precharge enabling signal; the output end of the first NOT gate is connected with the control end of the third three-state gate; the output end of the first tri-state gate is connected with the bit line of the SRAM unit; the output end of the second tri-state gate is connected with the inverting bit line of the SRAM unit; the output end of the third tri-state gate is connected with a second power supply; the first power supply is used as a power supply of the security chip; the second power supply is used as a power supply of the SRAM unit.

2. The SRAM PUF security chip of claim 1, wherein said SRAM cell comprises: a latch unit, a first transfer transistor, and a second transfer transistor;

the grid electrode of the first transmission transistor and the grid electrode of the second transmission transistor are connected with a word line; the drain electrode of the first transmission transistor is connected with a bit line; the drain electrode of the second transmission transistor is connected with the inverting bit line;

a first input end of the latch unit is connected with the second power supply; a second input end of the latch unit is connected with a source electrode of the first transmission transistor; a third input end of the latch unit is connected with a source electrode of the second transmission transistor; the logic voltage values of the second input terminal and the third input terminal are opposite.

3. The SRAM PUF security chip of claim 2, wherein said latch unit comprises: a first transistor, a second transistor, a third transistor, and a fourth transistor;

the first transistor and the third transistor are connected to form a second NOT gate; the second transistor and the fourth transistor are connected to form a third NOT gate; the input end of the second NOT gate is connected with the output end of the third NOT gate; the input end of the third NOT gate is connected with the output end of the second NOT gate; the input end of the second NOT gate is used as a second input end of the latch unit; the input end of the third NOT gate is used as a third input end of the latch unit; the second NOT gate and the third NOT gate are both connected with the second power supply.

4. S, SRAM PUF security chip, characterized in that it comprises: an SRAM array and a second precharge circuit; the SRAM array, comprising: 2 ^m SRAM cells of row, n columns; the second precharge circuit includes: n tri-state gate units, a fourth tri-state gate and a fourth NOT gate;

the tri-state gate unit includes: a fifth tri-state gate and a sixth tri-state gate; a column of SRAM units is correspondingly connected with a tri-state gate unit;

for the M-th row in the SRAM array, word lines of all SRAM cells in the M-th column are connected to form a word line connection end; m is more than or equal to 1 and less than or equal to 2 ^m ；

For the N-th column in the SRAM array, bit lines of all SRAM cells in the N-th column are connected to form bit line connection ends, and inverting bit lines of all SRAM cells in the N-th column are connected to form inverting bit line connection ends; the control ends of a fifth tri-state gate and a sixth tri-state gate in the N-th tri-state gate unit are connected with a precharge enabling signal; the input ends of a fifth tri-state gate and a sixth tri-state gate in the N-th tri-state gate unit are connected with a first power supply; the output end of a fifth tri-state gate in the Nth tri-state gate unit is connected with the bit line connecting end; the output end of a sixth tri-state gate in the Nth tri-state gate unit is connected with the inverting bit line connecting end; n is more than or equal to 1 and less than or equal to N;

the input end of the fourth NOT gate is connected with the precharge enabling signal; the output end of the fourth NOT gate is connected with the control end of the fourth three-state gate; the input end of the fourth tri-state gate is connected with the first power supply; the output end of the fourth tri-state gate is connected with a second power supply; the first power supply is used as a power supply of the security chip; the second power supply is used as a power supply of the SRAM unit.

5. The SRAM PUF security chip of claim 4, further comprising: an m-bit address decoder;

the output end of the address decoder is connected with all word line connection ends.

6. The SRAM PUF security chip of claim 4, further comprising: a data controller;

the data controller includes: n input/output bidirectional interfaces; one of the input-output bi-directional interfaces is connected with one tri-state gate unit.