CN117032009A

CN117032009A - Embedded controller and output protection method

Info

Publication number: CN117032009A
Application number: CN202310832311.3A
Authority: CN
Inventors: 李歌航; 郭俊强; 应科科
Original assignee: 713rd Research Institute Of China Shipbuilding Corp ltd
Current assignee: 713rd Research Institute Of China Shipbuilding Corp ltd
Priority date: 2023-07-07
Filing date: 2023-07-07
Publication date: 2023-11-10

Abstract

The invention relates to an embedded controller and an output protection method, and belongs to the field of electrical control systems. After the DSP finishes initialization, the CPLD sends a digital handshake request signal to the CPLD, the CPLD verifies the received digital handshake request signal, the CPLD sends a monitoring signal to the DSP after the handshake is successful, the DSP controls the CPLD to stop outputting and alarm processing after monitoring abnormal conditions, and then the CPLD outputs a control enabling signal to an external circuit, so that the peripheral circuit works normally. Compared with the prior logic output mode, the invention can effectively stop the risk of abnormal output in the working process of the embedded controller, and greatly improves the reliability and safety of the output of the embedded controller.

Description

Embedded controller and output protection method

Technical Field

The invention relates to an embedded controller and an output protection method, and belongs to the field of electrical control systems.

Background

The embedded controller is a control system for executing specified independent control functions and having the capability of processing data in a complex manner, and can complete various automatic processing tasks such as monitoring, control and the like. The output module is used as an important component of the logic control system and plays a role in the safe and reliable work of the controlled object. When the output module outputs signals accidentally and abnormally in the starting process, the safety work of the controlled equipment is seriously influenced.

The protection of the embedded controller is mainly protection of embedded communication at present, and the embedded controller is protected to communicate by providing a security handshake or whether the embedded system operates normally or not is monitored by a monitoring operation program. Although the method can protect the embedded controller from safe communication, the abnormal signal output by the embedded controller cannot be controlled, and the peripheral state is uncontrollable due to the initialization time difference, so that the risk of outputting the abnormal signal exists.

Disclosure of Invention

The invention aims to provide an embedded controller and an output protection method, which are used for solving the problem of abnormal output in the current power-on process.

The invention provides an output protection method of an embedded controller for solving the technical problems, which comprises the following steps:

1) After the initialization is completed, the DSP sends a digital handshake request signal to the CPLD, and the CPLD verifies the received digital handshake request signal;

2) If the CPLD passes verification, the handshake is successful, and the CPLD outputs a control enabling signal to the external circuit so that the external circuit works normally.

The invention adds the digital handshake signal between the DSP and the CPLD in the embedded controller, adds the control enabling signal between the CPLD and the peripheral circuit, and outputs the control enabling signal to the peripheral circuit after the handshake between the DSP and the CPLD is successful, so that the peripheral circuit works normally. Therefore, the peripheral circuit can work when the DSP and the CPLD finish initialization and the state is stable, and compared with the traditional logic output mode, the peripheral circuit can effectively stop the risk of abnormal output in the working process of the embedded controller, and greatly improves the reliability and safety of the output of the embedded controller.

Further, the method also comprises the step that the CPLD sends a monitoring signal to the DSP after the handshake is successful, and the DSP controls the CPLD to stop outputting after monitoring the abnormal situation.

Further, the method also comprises alarm processing after the DSP detects the abnormal condition.

The DSP monitors the state of the CPLD in real time, and after the abnormal condition is detected, the CPLD stops outputting, and carries out alarm processing, so that problems can be found in time and the output of abnormal signals can be avoided.

Further, the control enable signal is sent to the peripheral circuitry via the 38 decoder.

The 38 decoder has the characteristics of high efficiency, stability and reliability, and can ensure the correctness and stability of output signals.

Further, the method also comprises the step of setting a delay switch on a power supply circuit of the peripheral circuit, wherein the delay time of the delay switch is longer than the initialization completion time of the whole embedded controller.

The delay starting time is longer than the initialization completion time of the whole embedded control area, so that the risk of uncontrollable state of the peripheral circuit and abnormal signal output in the stage caused by the fact that the CPLD and the DSP circuit are in uncertain states as the CPLD and the DSP circuit are not initialized yet when the peripheral circuit is powered on is avoided.

An embedded controller comprises a power supply, a DSP, a CPLD and a peripheral circuit, wherein the DSP is used for transmitting a digital handshake signal to the CPLD after initialization is completed; the CPLD is used for verifying the received digital handshake request signal and outputting a control enabling signal to an external circuit after the handshake is successful; the peripheral circuit works after receiving the control enabling signal.

Further, the CPLD sends a monitoring signal to the DSP after the handshake is successful, and the DSP controls the CPLD to stop outputting after monitoring the abnormal situation.

Further, the device also comprises an alarm, wherein the alarm is connected with the DSP and alarms when the DSP monitors abnormal signals.

Further, the apparatus includes a 38 decoder, and the control enable signal is sent to the peripheral circuit through the 38 decoder.

Further, the power supply loop of the peripheral circuit is also provided with a delay switch, and the delay time of the delay switch is longer than the initialization completion time of the whole embedded controller.

The delay switch is added, and after the initialization of the CPLD and the DSP is completed, the power is supplied to the peripheral circuit, so that the risk of outputting abnormal signals due to uncontrollable state of the peripheral circuit in the stage caused by the fact that the CPLD and the DSP output pins are in an uncertain state as the initialization of the CPLD and the DSP is not completed yet when the peripheral circuit is powered on is avoided

Drawings

FIG. 1 is a schematic diagram of the logic output of an embedded controller of the prior art;

fig. 2 is a logic output schematic diagram of the output protection method of the embedded controller of the present invention.

Detailed Description

The following describes the embodiments of the present invention further with reference to the drawings.

Embodiments of an embedded controller

The logic output principle of the existing embedded controller is shown in fig. 1, the DSP transmits an output signal to the CPLD through a data bus, an address bus or a GPIO signal, and the CPLD performs logic and time sequence processing to drive a peripheral circuit to output the signal to a controlled execution unit. The invention adds digital handshake, real-time monitoring, decoding control and delay starting to protect the output of the embedded controller based on the existing embedded controller.

The embedded controller comprises a power supply, a DSP, a CPLD and a peripheral circuit, wherein the DSP is used for sending a digital handshake signal to the CPLD after initialization is completed, monitoring a received monitoring signal, stopping outputting after abnormal conditions are monitored, and carrying out alarm processing; the CPLD is used for verifying the received digital handshake request signal, sending a monitoring signal to the DSP after handshake is successful, and outputting a control enabling signal to the external circuit; the peripheral circuit works after receiving the correct signal. The implementation principle of the device is shown in fig. 2, and is described below with reference to a specific example.

After the initialization is completed, the DSP sends a digital handshake request signal to the CPLD, and the CPLD verifies the received digital handshake request signal. The specific value of the signal can be freely set according to the requirement, is not larger than 16 bits in principle, and is assigned to the CPLD through write operation after the DSP completes initialization. The CPLD is allowed to perform the output task only after it has stably received the digital handshake signal and checked correctly. In this embodiment, in the DSP program, after the system initialization is completed, before the main program loops, handshake signals "0x10100101" and addresses are written to the XINTF area one (CPLD plug-in memory area) through the data bus: 0X40E1. In the CPLD program, when the area selection signal XZCS1, the address signal 0X40E1 and the write signal XWE are received at the same time, the CPLD stores the data written by the DSP and judges whether the data is 0X10100101, if the data is 0X10100101, the handshake is successful, the CPLD is allowed to execute the instruction signal from the DSP, otherwise, the CPLD is not executed.

After the handshake is successful, the CPLD sends a monitoring signal to the DSP, the DSP monitors the CPLD state in real time, stops outputting after abnormal conditions are monitored, and carries out alarm processing. In this embodiment, after the CPLD is powered on to complete initialization and handshake is successful, the CPLD sends a square wave signal to the GPIO input pin of the DSP through connecting one output signal of the DSP, the period is 200ms, the DSP detects and judges the signal at all times, and when 5 consecutive periods do not meet the requirements, the CPLD stops outputting, clears the handshake signal and reports a fault to the upper computer.

The embedded controller also comprises a 38 decoder, and the CPLD outputs a control enabling signal to the external circuit through the 38 decoder after the handshake is successful so that the external circuit works normally. When the CPLD executes the output task, five paths of signals are output to the 38 decoder, wherein three paths of signals control the 38 decoder selection end, two paths of signals control the 38 decoder enabling end, and only when the five paths of signals are correctly output according to the stipulation, the output end of the decoder connected with the peripheral circuit is pulled down, and the peripheral circuit works normally. In this embodiment, after the handshake between the DSP and the CPLD is successful, the CPLD sends a decoding control signal 10011 to the 38 decoder, so that the third path of the 38 decoder is enabled to output a low level, and the peripheral loop is driven to work normally.

The power supply loop of the peripheral circuit of the embedded controller also comprises a delay switch, a delay starting contact is arranged in the power supply loop of the peripheral circuit by adopting a redundant design, the power supply is delayed for a certain time to supply power to the peripheral circuit while supplying power to the embedded controller, and the time is required to be longer than the initialization completion time of the whole embedded controller.

Embodiments of an embedded controller output protection method

After the DSP finishes initialization, the digital handshake request signal is sent to the CPLD, and the CPLD verifies the received digital handshake request signal; after the handshake is successful, the CPLD sends a monitoring signal to the DSP, and after the DSP monitors an abnormal condition, the CPLD is controlled to stop outputting and alarm processing; and then the CPLD outputs a control enabling signal to the external circuit to enable the external circuit to work normally. The specific implementation manner of the method is described in detail in the embodiment of the embedded controller, and will not be described herein.

Claims

1. An output protection method for an embedded controller is characterized by comprising the following steps:

2. The method of claim 1, further comprising the step of the CPLD sending a monitoring signal to the DSP after the handshake is successful, and the DSP controlling the CPLD to stop outputting after detecting an abnormal condition.

3. The method of claim 2, further comprising performing an alarm process when an abnormal condition is detected.

4. The method of claim 1, wherein the control enable signal is sent to the peripheral circuit via a 38 decoder.

5. The method of any one of claims 1-4, further comprising providing a delay switch on a power supply loop of the peripheral circuit, the delay time of the delay switch being greater than an overall embedded controller initialization completion time.

6. An embedded controller comprises a power supply, a DSP, a CPLD and a peripheral circuit, and is characterized in that the DSP is used for transmitting a digital handshake signal to the CPLD after initialization is completed; the CPLD is used for verifying the received digital handshake request signal and outputting a control enabling signal to an external circuit after the handshake is successful; the peripheral circuit works after receiving the control enabling signal.

7. The embedded controller of claim 6, wherein the CPLD sends a monitoring signal to the DSP after the handshake is successful, and wherein the DSP controls the CPLD to stop outputting after detecting an abnormal condition.

8. The embedded controller of claim 6, further comprising an alarm coupled to the DSP, the alarm configured to alarm when the DSP detects an abnormal signal.

9. The embedded controller of claim 6, further comprising a 38 decoder, wherein the control enable signal is sent to the peripheral circuit via the 38 decoder.

10. The embedded controller of claim 6, wherein a delay switch is further provided on the power supply loop of the peripheral circuit, and the delay time of the delay switch is longer than the initialization completion time of the whole embedded controller.